Previously, the TDA reuse condition was wrong: for multiple TDAs with
different k2, the symbol allocation might be the same, in which the
previous logic was using the wrong TDA. Fix the condition, and insert an
assert to ensure the allocated TDA is correct.
Integration: `2025.w36`
* !3613 Speedup complex rotate for aarch64
* !3614 Ldpc encoder zc384 optimization
* !3625 gNB scheduler small fixes
* !3629 Fix for gNB max feedback time parameter
* !3619 Fix RA 2-Step MgsB Ack at UE
* !3626 Upgrade CI to Aerial 25-2
See merge request oai/openairinterface5g!3627
When FHI 7.2 is enabled, the EAL initialization is done by the FHI and
the attempt to init EAL by ldpc_aal will fail.
In that case, it is not necessary neither to provide a DPDK core list
for BBDEV.
This commit offers to skip EAL initialization if it is already initialized
in order to allow dropping the useless DPDK cores argument in that case.
The change relies on `rte_dev_probe` to detect if EAL was already
initialized.
Fix for gNB max feedback time parameter
This bug is causing assertions like the following
Assertion (curr_pucch->active == 0) failed!
In nr_csi_meas_reporting() /oai-ran/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c:282
CSI structure is scheduled in advance. It should be free!
because the PUCCH structure would be smaller than it should be causing
overlapping.
gNB scheduler small fixes
A couple of fixes in gNB scheduling function. Removing a superfluous input from
CCE function and adding a missing call to reset beam allocation.
Ldpc encoder zc384 optimization
This is a modification for the ldpc encoder which improves performance for
high-throughput cases. It contains a newly-generated file for innermost part of
the parity bit generation which, for AVX512, uses the mm512_permutex2var_epi8
instruction and for 128-bit (aarch64) the mm_alignr_epi8 (vextq_s8) in the
computation corresponding to each non-zero bit of the H matrix. This allows for
removing a very large memcpy and reduces the memory demand for the parity matrix
computation. For the moment this is limited to largest case in BG1, namely
Zc=384. This is the only format used when the number of segments after codeblock
segmentation is large (>8). This improves the timing required for ldpc parity
bits generation by more than a factor 2 with AVX512. This significantly reduces
the total time to generate the DLSCH/PDSCH.
See the merge request description for numbers.
Speedup complex rotate for aarch64
This is a simple optimization for aarch64 for the "rotate_cpx_vector" used for
the phase_rotation in 5G NR. It provides a speedup of around 1.5 on high-end
aarch64 targets compared to the SIMDe translated version. It is implemented with
native NEON intrinsics and was largely inspired by suggestions from ChatGPT 5 :-)
newly-generated files for innermost part of the parity bit
generation which, for AVX512, uses the mm512_permutex2var_epi8
instruction and for 128-bit (aarch64) the mm_alignr_epi8 (vextq_s8) in
the computation corresponding to each non-zero bit of the H matrix.
It is generated with ldpctest -n0 -g1. the changes for this are in a
future MR. I did these changes to compare with the GPU version
(ldpc_encoder_cuda), so that the CPU version is as fast as possible. The
generator will come when we merge the GPU encoder/decoder which also has
a generator for the CUDA version. it was difficult to extract the
changes in ldpctest/ldpc_encoder.c so I just took the generated file.
This allows for removing a very large memcpy and reduces the memory
demand for the parity matrix computation. For the moment this is limited
to largest case in BG1, namely Zc=384. This is the only format used when
the number of segments after codeblock segmentation is large (>8). This
improves the timing required for ldpc parity bits generation by more
than a factor 2 with AVX512. This significantly reduces the total time
to generate the DLSCH/PDSCH
Redirect to files and manual analysis as done in this Dockerfile is not
necessary since we just output all relevant build files to stdout.
Simplify to do the same here.
See: 35361db76b ("build_oai: don't redirect compilations to a file")
Fix OAIUE-OTA pipeline and increase tested traffic
I tried to "fix" the OAIUE pipeline in !3610 (merged) for making it more reliable, but inadvertently introduced many ULSCH DTX for UL traffic. Fix this, and increase DL traffic.
See merge request oai/openairinterface5g!3621
Integration: `2025.w35`
* !3604 Consider PDSCH EPRE to DMRS EPRE in NR UE
* !3606 Fix SRS TLV unpack
* !3602 Update RFsim CN
* !3516 [FHI72 M-plane] CM improvements and PM implementation
* !3538 add a new graphical T tracer to see gNB MAC scheduling decisions
* !3425 RFSim test for 10 UEs/process
Closes#950
See merge request oai/openairinterface5g!3610
RFSim test for 10 UEs/process
This MR adds a testcase and changes required to run 10 UEs in a single
process with RFSim
- Added deregistration for all connected UEs
- Refactored MAC/RRC instance handling
- made map_current_symbol thread safe
- made opeanir0_cfg thread safe and local
- Added 10UE/process testcase
Some code in T tracers is used by both LTE and NR.
In LTE, we expect 10 subframes per frame, and the logging is done with
this assumption. We have one tick per subframe.
In NR, we deal with slots, not subframes. And we have n ticks per frame
(depending on mu). As of today, only n=20 is tested (corresponding to
mu=1).
A previous commit introduced 'subframes_per_frame' which had the correct
meaning for LTE but was truly 'slots per frame' for NR. This creates
confusion.
Let's replace 'subframe' by 'tick' to reduce confusion.
Guido Casati