Commit Graph
836 Commits
Author SHA1 Message Date
Laurent OpenCells c0ef3e6f88 fix gcc reported issues 2021-04-03 23:37:58 +02:00
Laurent THOMAS 0317d6725b sanitize, calibration tool kickoff 2021-04-02 10:12:13 +02:00
Florian Kaltenberger 2e9ac3672d removing annoying printf 2021-03-29 10:35:00 +02:00
Thomas Schlichter dade64ea43 Merge remote-tracking branch 'develop' into NR_DL_MIMO 2021-03-19 11:18:02 +01:00
Thomas Schlichter b7ef903cb4 Merge remote-tracking branch 'develop' into NR_10MHz 2021-03-16 16:13:17 +01:00
Thomas Schlichter 3152df445e Merge remote-tracking branch 'develop' into NR_DL_MIMO 2021-03-16 13:37:07 +01:00
francescomani 97ed2dfe5b Merge remote-tracking branch 'origin/develop' into NR_10MHz 2021-03-02 14:31:12 +01:00
rmagueta 5f66269a8b Merge remote-tracking branch 'origin/develop' into develop-SA-RA
# Conflicts:
#	openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
2021-03-02 12:01:11 +00:00
hardy 8d05695722 Merge remote-tracking branch 'origin/benetel_driver_update' into integration_2021_wk09_b 2021-02-26 16:09:05 +01:00
Laurent Thomas b3e21ad87b only a printf 2021-02-10 17:58:10 +01:00
Laurent Thomas 2c5bd9fa8c improve rfsim 2021-02-10 17:49:14 +01:00
Thomas Schlichter 75cd4c79d9 update tx_sample_advance for 40 MHz and USRP X300 (3/4 sampling)
Testing RA with OAI gNB and UE both using X300 via PCIe link indicated a value of 15 was way too small.
The correct value for this setup seems to be 65.
2021-02-09 18:09:11 +01:00
Thomas Schlichter b9e99f1e64 update tx_sample_advance for 10 MHz and USRP X300
Tests with our USRP X300, connected via PCIe, show that tx_sample_advance of 45 is slightly too much.
Unfortunately, transmitting the PRACH preamble too early is very bad, slightly too late is no problem.
So change this value from 45 to 40. This helps receiving the PRACH preamble reliably.
2021-02-09 17:51:33 +01:00
Cedric Roux b7ea4e0f6d benetel 5g: support for two antennas 2021-02-05 16:48:30 +01:00
Cedric Roux a9f57407c7 benetel 4g: support two antennas 2021-02-03 17:07:18 +01:00
Thomas Schlichter 8b00361f56 fix warnings identified by CI 2021-02-03 10:50:38 +01:00
rmagueta 76b974508b Merge branch 'develop' into develop-sib1-update-ue
# Conflicts:
#	cmake_targets/CMakeLists.txt
2021-02-02 12:10:12 +00:00
luis_pereira87 6885668273 Fix AssertFatal in replay_node when file size is not a multiple of block size 2021-02-01 20:55:58 +00:00
Florian Kaltenberger 857f9179f3 shifting also the TX 4 bits to the left to exploit dynamic range. adapted ssb_block_power but proper calibration still necessary. 2021-02-01 10:24:22 +01:00
Florian Kaltenberger a5b5d6f9b0 fixing RRC power levels at 5G side to avoid saturation 2021-02-01 10:24:22 +01:00
Khodr Saaifan d4bd15f5ad increase CirSize to avoid overflow in the case of multi-transmit antennas for gNB 2021-02-01 10:12:38 +01:00
hardy 9c810b311d Merge remote-tracking branch 'origin/itti-enhancement' into integration_2021_wk04_b 2021-01-29 07:40:07 +01:00
Laurent 3b0c43c04b fix memory allocation error 2021-01-10 21:41:22 +01:00
Laurent ebccfe5117 add raw capture from UHD examples and fix a rfsim bug 2021-01-02 18:58:13 +01:00
Laurent c4a91bcc62 scope, dirty replay 2020-12-29 19:00:51 +01:00
hardy 69cc0767c0 Merge remote-tracking branch 'origin/ldpc_short_codeword_fixes' into integration_2020_wk51_2 2020-12-16 11:09:56 +01:00
Thomas Schlichter fda514b3ba rfsimulator: do not show "gap in reception" messages if complete slots are skipped (e.g. NR DL: gNB transmission, UE reception) 2020-12-14 12:06:11 +01:00
cig 52cb041693 Updated usage of channel model simulation in RFSIM 2020-12-09 09:35:41 +01:00
Raymond Knopp 2303a9bcf6 CPPcheck errors + some warnings 2020-11-27 18:54:09 +01:00
Raymond Knopp 7955cb4f8e tested IF4p5 on asterix/obelix (100 PRB via 1 Gbit/s) 2020-11-22 10:10:12 +01:00
Raymond Knopp 47a7186621 Merge remote-tracking branch 'origin/develop' into develop-oriecpriupdates 2020-11-19 18:35:52 +01:00
Raymond Knopp 98a96115c7 testing with AW2S RRU. 2020-11-18 10:50:03 +01:00
Florian Kaltenberger 6e1ad6e93b Merge remote-tracking branch 'origin/develop' into benetel_phase_rotation 2020-11-09 13:58:41 +01:00
hardy 3917b1ae0f Merge remote-tracking branch 'origin/NR_RRCConfiguration_FR2' into integration_2020_wk45_2 2020-11-05 16:53:13 +01:00
Raymond Knopp 8b92c53141 modifications for eCPRI radio units, increased averaging in eNodeB subband I0 measurements 2020-11-03 06:01:42 +01:00
Florian Kaltenberger 0609742e21 Merge remote-tracking branch 'origin/benetel_5g_prach_fix' into benetel_phase_rotation 2020-10-30 12:30:25 +01:00
Florian Kaltenberger a129f121cc dpdk changes for 18.11 2020-10-28 13:07:41 +01:00
Florian Kaltenberger 144e267541 fixing PRACH bug in benetel_5g driver 2020-10-28 11:08:26 +01:00
Raymond Knopp 6c414a80d4 wqMerge remote-tracking branch 'origin/develop' into develop-oriecpriupdates 2020-10-26 19:58:25 +01:00
Florian Kaltenberger 32c8c86730 fixing benetel drivers after introduction of multiple PRACH occastions 2020-10-23 13:28:48 +02:00
laurent 5cb8e9e14d Reduce difference with OSA develop branch for merge 2020-10-02 11:26:46 +02:00
Rakesh 5f7c30fb8c fix for get_slot_from_timestamp 2020-10-01 17:47:17 +02:00
Laurent 19c6229049 merge develop, compile ok 2020-09-22 16:24:49 +02:00
Rakesh 8ab1c0b9d4 Merge remote-tracking branch 'origin/develop' into NR_RRCConfiguration_FR2 2020-09-16 11:56:07 +02:00
Rakesh 42fe39ece5 moving gpio control to the rx 2020-09-08 22:43:42 +02:00
Raphael Defosseux e5bbc0f1e4 BUILD: fix compilation warning and circular dependency protection on header files
Signed-off-by: Raphael Defosseux <raphael.defosseux@eurecom.fr>
2020-09-07 10:54:49 +02:00
Thomas Schlichter 966cc20766 fix compile warning in rfsimulator 2020-09-04 14:05:26 +02:00
Raphael Defosseux 59ab6f3628 Merge remote-tracking branch 'origin/usrp_fix_adc_shift_and_pps_sync' into develop_integration_2020_w36 2020-09-03 16:50:21 +02:00
Raphael Defosseux 2dcf50a5bc Merge remote-tracking branch 'origin/benetel_integration' into develop_integration_2020_w36 2020-09-03 16:47:39 +02:00
Florian Kaltenberger 627da47786 fixing adc inpput shift and gain table for N310. adding pps sync. 2020-09-03 13:49:41 +02:00