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c66b09c8a3d5d14ca47e527bb9307b1b7694f9d5
Commit Graph
6390 Commits
Author SHA1 Message Date
Jaroslava Fiedlerova c66b09c8a3 T2: Fix buffer overflow and HARQ codeblock ID out of range 
- set size of buffers to max E
- change HARQ codeblock offset calculation for T2
- add constant for maximum code block size - max E
 2023-12-21 11:19:13 +01:00
Robert Schmidt b4b2389753 Merge remote-tracking branch 'origin/ue-fix-ul-first-tx' into integration_2023_w48 2023-12-05 07:39:51 +01:00
Robert Schmidt 5440d6671f Merge remote-tracking branch 'origin/t2-offload-mr' into integration_2023_w48 2023-12-04 17:16:51 +01:00
Thomas Schlichter 6ef5d27c08 NR_UE: fix usage of PUSCH new_data_indicator and cleanup 2023-12-01 16:02:17 +01:00
Robert Schmidt 11c853e760 Fix: All UEs can have a UCI in each slot 2023-11-29 08:59:36 +01:00
Jaroslava Fiedlerova 7c5b945766 Set RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE based on harq_to_be_cleared value 2023-11-28 09:37:37 +01:00
laurent 7bb529dcdf fix redundant member in ldpc decoder struct 2023-11-28 09:37:37 +01:00
laurent 10d7fe9cc6 fix regressions in cuda ldpc 2023-11-28 09:37:37 +01:00
Jaroslava Fiedlerova cf97acb8c7 Add T2 LDPC encoding/decoding offload 2023-11-28 09:37:37 +01:00
Laurent THOMAS 99ca87a1c1 Refactor LDPC API to make common API with various implementations 2023-11-28 09:37:37 +01:00
Jaroslava Fiedlerova e945b260f8 Remove T1 decoding offload 2023-11-28 09:37:37 +01:00
Robert Schmidt 610a886da7 Merge remote-tracking branch 'origin/multi-config' into integration_2023_w44 2023-11-12 05:14:36 +01:00
Robert Schmidt 3fd45922b7 Merge remote-tracking branch 'origin/NR_PTRS_improvements' into integration_2023_w44 2023-11-12 05:14:25 +01:00
Robert Schmidt 6fe68a574b Merge remote-tracking branch 'origin/NR_UE_resync_hotfix' into integration_2023_w44 2023-11-10 14:38:55 +01:00
Laurent THOMAS f50d5f5a9b make multiple config instead of one implicit global 2023-11-10 10:23:11 +01:00
Robert Schmidt e1e8e10d91 Merge remote-tracking branch 'origin/NR_UE_handling_MCS_for_retransmission_v2' into integration_2023_w44 2023-11-06 07:33:28 +01:00
francescomani 629825aca6 taking into account PTRS in computing G 2023-11-03 10:39:13 +01:00
francescomani d247abb53d code cleanup 2023-11-03 10:15:25 +01:00
francescomani a05baa3c77 fixes to avoid double synchronization call 2023-11-03 10:01:53 +01:00
Robert Schmidt 7420de8fc9 Merge remote-tracking branch 'origin/fix-doxygen' into integration_2023_w43 2023-10-30 10:23:45 +01:00
Robert Schmidt 803fcb59a9 Merge remote-tracking branch 'origin/assigned_value_is_garbage_or_undefined' into integration_2023_w43 2023-10-30 10:22:03 +01:00
Robert Schmidt a51c5299c6 Merge remote-tracking branch 'origin/polar-encoder-perf-improv' into integration_2023_w43 2023-10-27 14:21:23 +02:00
mir 364f98ac11 Avoid double initialization 2023-10-27 11:50:40 +02:00
Laurent THOMAS bba9aac079 fix most of doxygen warnings and errors 2023-10-26 16:47:19 +02:00
rmagueta e14903cd96 Call __builtin_popcountll function to count the number of bits set in uint64_t variable for polar codes 2023-10-26 12:23:20 +02:00
mir 2ccc58f6d3 Assigned value is garbage or undefined reportedt by scan-build 2023-10-25 11:51:33 +02:00
francescomani 73244eae4d storing TBS and R at MAC instead of PHY 2023-10-20 18:00:34 +02:00
Raphael Defosseux 80c2bc3fcb fix(arm-build): immintrin.h is not available 
Signed-off-by: Raphael Defosseux <raphael.defosseux@eurecom.fr>
 2023-10-20 11:36:39 +02:00
Robert Schmidt d6fe889abe Merge remote-tracking branch 'origin/Remove-convert-csirs-pdu-calloc' into integration_2023_w41 2023-10-13 11:05:43 +02:00
Robert Schmidt 7f0dbde135 Merge remote-tracking branch 'origin/break_dci_processing_function_in_smaller_pieces' into integration_2023_w41 2023-10-13 11:05:33 +02:00
Robert Schmidt e3b3495488 Merge remote-tracking branch 'origin/NR_UE_sanitize_PUCCH2' into integration_2023_w41 2023-10-12 20:57:48 +02:00
Rúben Soares da Silva 80a6a3e8c3 Fix memory leak and improve convert_csirs_pdu() 
- Remove calloc from convert_csirs_pdu function, change return value
  from 'nfapi_nr_dl_tti_csi_rs_pdu_rel15_t *' to
  'nfapi_nr_dl_tti_csi_rs_pdu_rel15_t' to not require call to 'free()'
- Set parameter pointer as const as it's not modified
- Remove cast to fapi_nr_dl_config_csirs_pdu_rel15_t in csi_rx.c as
  ue->csirs_vars[gNB_id]->csirs_config_pdu is already of type
  fapi_nr_dl_config_csirs_pdu_rel15_t.
- Remove casted parameter in call to convert_csirs_pdu and replace with
  csirs_config_pdu obtained earlier from
  ue->csirs_vars[gNB_id]->csirs_config_pdu.
 2023-10-12 20:52:17 +02:00
Robert Schmidt 8d2b8895df Review commit 2023-10-12 07:12:06 +00:00
Laurent THOMAS 6b56b46811 Break UE DCI processing function in smaller pieces 2023-10-12 07:46:45 +02:00
Laurent THOMAS 838b284aa4 remove-global-rx_spatial_power_in_gnb 2023-10-10 15:45:21 +02:00
Robert Schmidt 7957b466d4 Merge remote-tracking branch 'origin/pusch-llr-SIMDe' into integration_2023_w40 2023-10-09 16:48:37 +02:00
Robert Schmidt 2635cf4817 Merge remote-tracking branch 'origin/remove-dead-code-nrue' into integration_2023_w40 2023-10-09 08:12:43 +02:00
Robert Schmidt a8fa1b0e52 Merge remote-tracking branch 'origin/develop-pucch-power' into integration_2023_w40 2023-10-08 17:48:26 +02:00
Laurent THOMAS 584fb235cd remove-dead-code-nrue 2023-10-06 18:00:18 +02:00
Quency Lin f451f62c9c Fix cannot pass sanitizer, Align to 16 for 2 contiguous 256 SIMDe 2023-10-06 16:39:51 +02:00
Rúben Soares da Silva 9bee85dbe2 Remove previously added bwp_size and bwp_start fields from struct fapi_nr_dl_config_csirs_pdu_rel15_t. 
Create function to obtain nfapi_nr_dl_tti_csi_rs_pdu_rel15_t from fapi_nr_dl_config_csirs_pdu_rel15_t without bwp_size and bwp_start.
Replace previously problematic cast with call to created function.
 2023-10-04 18:46:54 +01:00
Quency Lin 999bdc01c8 fix: Remove miss-hardcoded #define USE_128BIT 2023-10-04 13:57:07 +02:00
Quency Lin e92c827820 fix: SISO 128 SIMDe due to rebase to 2023.w39 2023-10-03 23:49:30 +02:00
Quency Lin cdcb403538 Refactor: Caculate bit_met_s[0..63] in for-loop 2023-10-03 22:13:31 +02:00
Quency Lin 5424843190 misc: remove debug print and fix wrong index accessing array 
Before this MR, openair1/PHY/NR_TRANSPORT/nr_ulsch_llr_computation.c:
nr_ulsch_qam64_qam64():
    xmm3 = simde_mm256_max_epi16(bit_met_m5_p1, bit_met_m5_p1);

Should be instead:
    xmm3 = simde_mm256_max_epi16(bit_met_m5_p1, bit_met_m7_p1);
 2023-10-03 22:13:31 +02:00
Quency Lin 8b1f42423b Refactor: 16QAM LLR 128 SIMDe assign 2023-10-03 22:13:31 +02:00
Quency Lin e8bcd1882c Refactor: minor refactors 
* [x] `register simde__m128i xmm0;` -\> `simde__m128i xmm0;`
* [x] `simde__m128i xmm0 = simde_mm_abs_epi16(rxF\[i\]);` declaration in for loop
* [x] `int nb_re64 = nb_re >> 1;` would be better as `int last2re = (nb_re >> 1) - 1;`
* [x] `simde_m_punpckhdq()` is better known as `simde_mm_unpackhi_pi32()`
 2023-10-03 22:13:31 +02:00
Quency Lin 7d6a955b49 Fix: variable typo when referencing 2023-10-03 22:06:42 +02:00
Quency Lin 0c4993249f fix: CI failure due to SIMD misalignment 2023-10-03 22:03:40 +02:00
Quency Lin 797f8cec80 Refactor: Make qam64_qam64 more compact 
Use local arrays and for-loop to replace duplicated statements.
For reference, here is the table of index v.s. old local variable
qam64 qam64
psi_r_, psi_i_, a_r_, a_i_, psi_a_, a_sq_, bit_met_
 0 p7_p7    16 p3_p7    32 m1_p7    48 m5_p7
 1 p7_p5    17 p3_p5    33 m1_p5    49 m5_p5
 2 p7_p3    18 p3_p3    34 m1_p3    50 m5_p3
 3 p7_p1    19 p3_p1    35 m1_p1    51 m5_p1
 4 p7_m1    20 p3_m1    36 m1_m1    52 m5_m1
 5 p7_m3    21 p3_m3    37 m1_m3    53 m5_m3
 6 p7_m5    22 p3_m5    38 m1_m5    54 m5_m5
 7 p7_m7    23 p3_m7    39 m1_m7    55 m5_m7
 8 p5_p7    24 p1_p7    40 m3_p7    56 m7_p7
 9 p5_p5    25 p1_p5    41 m3_p5    57 m7_p5
10 p5_p3    26 p1_p3    42 m3_p3    58 m7_p3
11 p5_p1    27 p1_p1    43 m3_p1    59 m7_p1
12 p5_m1    28 p1_m1    44 m3_m1    60 m7_m1
13 p5_m3    29 p1_m3    45 m3_m3    61 m7_m3
14 p5_m5    30 p1_m5    46 m3_m5    62 m7_m5
15 p5_m7    31 p1_m7    47 m3_m7    63 m7_m7

y0
 0 y0_p_7_7   16 y0_p_3_7
 1 y0_p_7_5   17 y0_p_3_5
 2 y0_p_7_3   18 y0_p_3_3
 3 y0_p_7_1   19 y0_p_3_1
 4 y0_m_7_1   20 y0_m_3_1
 5 y0_m_7_3   21 y0_m_3_3
 6 y0_m_7_5   22 y0_m_3_5
 7 y0_m_7_7   23 y0_m_3_7
 8 y0_p_5_7   24 y0_p_1_7
 9 y0_p_5_5   25 y0_p_1_5
10 y0_p_5_3   26 y0_p_1_3
11 y0_p_5_1   27 y0_p_1_1
12 y0_m_5_1   28 y0_m_1_1
13 y0_m_5_3   29 y0_m_1_3
14 y0_m_5_5   30 y0_m_1_5
15 y0_m_5_7   31 y0_m_1_7

rho_r
 0 pi_7_7   16 pi_3_7
 1 pi_7_5   17 pi_3_5
 2 pi_7_3   18 pi_3_3
 3 pi_7_1   19 pi_3_1
 4 mi_7_1   20 mi_3_1
 5 mi_7_3   21 mi_3_3
 6 mi_7_5   22 mi_3_5
 7 mi_7_7   23 mi_3_7
 8 pi_5_7   24 pi_1_7
 9 pi_5_5   25 pi_1_5
10 pi_5_3   26 pi_1_3
11 pi_5_1   27 pi_1_1
12 mi_5_1   28 mi_1_1
13 mi_5_3   29 mi_1_3
14 mi_5_5   30 mi_1_5
15 mi_5_7   31 mi_1_7
 2023-10-03 22:03:40 +02:00