Add ulsch decoding measurements, which are reported by nr_ulsim. Start ulsch_decoding_stats measurement before
nr_ulsch_decoding is called and stop it after collection of all decoder tasks from Tpool. In the context of nr_ulsim,
ULSCH_id is allways == 0, testing is performed per one TB, therefore measurement is started and stopped only once per trial.
Reported ulsch decoding statistics show the mean ulsch decoding time over x trials (specified by -n command line option of nr_ulsim).
This measurement does not provide valid information in case of nr-softmodem, when the loop is done over multiple ULSCH IDs -
start of the measurement is done multiple times and stops only once in this case.
For unitary physical simulators, ULSCH processing loop is executed only once
- the max number of PUSCH is set to 1. This ensures exactly one start and stop
of the ULSCH decoding time measurement per processed TB.
Note: ulsch decoding statistics reports average time of segmentation, rate matching, interleaving and decoding of the TB
PUSCH decoding is started multiple times in nr_ulsch_procedures() for
each ULSCH segment, and stopped once inside
phy_procedures_gNB_uespec_RX(). Not only is it not clear if that works
with the API, it also might measure more than just PUSCH decoding.
Remove the PUSCH decoding, it is misleading. Check L1 RX processing
instead.
This commit introduces a separate thread (l1_tx_thread) that processes
gNB DL/TX slots. It receives a message from the ru_thread when a new
slot started, and starts processing.
The DL part of the scheduler is run in the l1_tx_thread. Therefore,
only call UL indication (for scheduler) in UL slots. The UL indication
previously triggered the DL scheduler -- hence, it had to be called in
every slot. Now, since the DL scheduler is moved into the DL thread, we
don't have to call the scheduler in every slot anymore.
The reorder thread is removed, as reordering with this scheme is not
necessary anymore.
The main advantage of this version is that the TX can be scheduled
earlier (sl_ahead). Further, there can no longer be race conditions in
the TX path, since the scheduler/L2, TX L1 processing and the RU tx
function are all execute in the same thread (L1_tX_thread).
Also, the scheduler prepares PRACH/PUSCH/PUCCH FAPI PDUs. As of this
commit, the scheduler runs in the TX processing chain, whereas these
PDUs are destined for RX processing. Thus, too avoid data races,
instead of triggering the RX processing at the same time as TX
processing in the RU thread, this commit changes the code to trigger RX
processing after the scheduler has been run in TX processing to avoid
data races.
Finally, we synchronize RU and L1 threads. This is important for
rfsimulator, since unlike most radios, rfsimulator can run slower or
faster, depending on I/O and CPU (it does not have a stable "tick").
Co-authored-by: kiran <saikiran@iitj.ac.in>
- avoid the finction duplication
- add the transform predoding to the nr_rx_pusch_tp
- add the MMSE for 2 layer which modulation greater than 16 qam
- can support to 256 qam for 1 layer and 2 layer
!SIB1 is not correctly filled! This commit does not work with COTS UEs!
The next commit fixes this.
- Move radio config (e.g., minRXTXTIME, SIB1 TDA, do_SRS, etc) down to
MAC.
- Some parameters in MAC are redundant: delete them.
- Remove call to nr_mac_config_scc() from RRC and simulators, the MAC
initialization routine calls it implicitly
The MasterInformationBlock is handled at the DU and sent to the CU in
the F1 Setup Response. Hence, move it down to the MAC. Furthermore:
- Change type because MIB_PDU_t is 4G type
- Simplify schedule_nr_mib()
Note: the reestablishment is broken, and a later commit fixes it.
The ServingCellConfigCommon is an inherently radio-related
configuration. As such, it should be handled by the DU, not the CU.
Therefore, move it "down" to the MAC.
Testing on Neoverse N1 (Ampere 3GHz). Tested only on a subset of phy-simulators.
- Changes:
- use SIMDE consistently
- adaptations of LDPC decoder generator for ARMv8 performance
- SIMDe modifications of Intel CRC to allow for aarch64 build.
optimizations for 128-bit to improve performance of LDPC encode/decode
on aarch64 (Neoverse 1)
- added BG2 files for 128-bit ldpc encoder (aarch64)
- testing on Xeon
- testing on x86
- minor changes to build/run on x86
- change in crc.h after returning to aarch64
- removed some warning in ldpc decoder generator for x86_64
- char
- Delete irrelevant constants
- Correctly declare variables
- Define stdbool for all architectures
- Remove definition of _MM_SHUFFLE and use SIMDE_MM_SHUFFLE
- Remove commented code
- Fix CMakeLists.txt
- Include SIMDE avx2 functions in tools_defs.h
Laurent THOMAS