Raymond Knopp
a7bc282302
Testing on Neoverse N1 (Ampere 3GHz). Tested only on a subset of phy-simulators. - Changes: - use SIMDE consistently - adaptations of LDPC decoder generator for ARMv8 performance - SIMDe modifications of Intel CRC to allow for aarch64 build. optimizations for 128-bit to improve performance of LDPC encode/decode on aarch64 (Neoverse 1) - added BG2 files for 128-bit ldpc encoder (aarch64) - testing on Xeon - testing on x86 - minor changes to build/run on x86 - change in crc.h after returning to aarch64 - removed some warning in ldpc decoder generator for x86_64 - char - Delete irrelevant constants - Correctly declare variables - Define stdbool for all architectures - Remove definition of _MM_SHUFFLE and use SIMDE_MM_SHUFFLE - Remove commented code - Fix CMakeLists.txt - Include SIMDE avx2 functions in tools_defs.h
90 lines
3.2 KiB
C
90 lines
3.2 KiB
C
/*******************************************************************************
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Copyright (c) 2009-2018, Intel Corporation
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Intel Corporation nor the names of its contributors
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may be used to endorse or promote products derived from this software
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without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/**
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* Header file with CRC external definitions
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*
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*/
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#ifndef __CRCEXT_H__
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#define __CRCEXT_H__
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#include "PHY/sse_intrin.h"
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#include "types.h"
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/**
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* Flag indicating availability of PCLMULQDQ instruction
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* Only valid after running CRCInit() function.
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*/
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extern int pclmulqdq_available;
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/**
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* Flag indicating availability of PCLMULQDQ instruction
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* Only valid after running CRCInit() function.
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*/
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extern simde__m128i crc_xmm_be_le_swap128;
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extern const uint8_t crc_xmm_shift_tab[48];
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/**
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* @brief Shifts right 128 bit register by specified number of bytes
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*
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* @param reg 128 bit value
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* @param num number of bytes to shift right \a reg by (0-16)
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*
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* @return \a reg >> (\a num * 8)
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*/
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__forceinline
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simde__m128i xmm_shift_right(simde__m128i reg, const unsigned int num)
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{
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const simde__m128i *p = (const simde__m128i *)(crc_xmm_shift_tab + 16 + num);
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return simde_mm_shuffle_epi8(reg, simde_mm_loadu_si128(p));
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}
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/**
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* @brief Shifts left 128 bit register by specified number of bytes
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*
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* @param reg 128 bit value
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* @param num number of bytes to shift left \a reg by (0-16)
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*
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* @return \a reg << (\a num * 8)
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*/
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__forceinline
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simde__m128i xmm_shift_left(simde__m128i reg, const unsigned int num)
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{
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const simde__m128i *p = (const simde__m128i *)(crc_xmm_shift_tab + 16 - num);
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return simde_mm_shuffle_epi8(reg, simde_mm_loadu_si128(p));
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}
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/**
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* @brief Initializes CRC module.
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* @note It is mandatory to run it before using any of CRC API's.
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*/
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extern void CRCInit(void);
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#endif /* __CRCEXT_H__ */
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