111 lines
4.0 KiB
Protocol Buffer
111 lines
4.0 KiB
Protocol Buffer
syntax = "proto2";
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package protocol;
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//
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// Message containing the DL DCI info
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//
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message flex_dl_dci {
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optional uint32 rnti = 1;
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optional uint32 res_alloc = 2; // Type of resource allocation
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optional uint32 rb_bitmap = 3; // Bitmap for RB allocation
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optional uint32 rb_shift = 4; // See TS 36.214, section 7.1.6.2
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repeated uint32 tbs_size = 5; // The size of each TBS
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repeated uint32 mcs = 6; // The MCS of each TB
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repeated uint32 ndi = 7; // New data indicator of each TB
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repeated uint32 rv = 8; // Redundancy version of each TB
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optional uint32 cce_index = 9; // CCE index used to send the DCI
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optional uint32 aggr_level = 10;
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optional uint32 precoding_info = 11; // 2 antenna ports:0..6,
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// 4 antenna ports:0..50
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optional uint32 format = 12; // DCI format. A FLDCIF_* value
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optional uint32 tpc = 13; // TS 36.213, sec 5.1.1.1
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optional uint32 harq_process = 14; // HARQ process ID
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optional uint32 dai = 15; // TDD only
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optional uint32 vrb_format = 16; // One of the FLVRBF_* values
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optional uint32 tb_swap = 17; // Boolean. TB to codeword swap flag
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optional uint32 sps_release = 18; // Flag value
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optional uint32 pdcch_order = 19;
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optional uint32 preamble_index = 20; // Only valid if pdcch_order = 1
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optional uint32 prach_mask_index = 21; // Only valid if pdcch_order = 1
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optional uint32 n_gap = 22; // One of the FLNGV_* values
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optional uint32 tbs_idx = 23; // The TBS index for Format 1A
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optional uint32 dl_power_offset = 24; // For format 1D
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optional uint32 pdcch_power_offset = 25; // DL PDCCH power boosting in dB
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optional uint32 cif_present = 26; // Boolean. Indication of CIF field
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optional uint32 cif = 27; // CIF for cross-carrier scheduling
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}
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message flex_ul_dci {
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optional uint32 rnti = 1;
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optional uint32 rb_start = 2; // The start RB allocated to the UE
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optional uint32 rb_len = 3; // The number of RBs allocated to the UE
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optional uint32 mcs = 4; // Modulation and coding scheme
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optional uint32 cyclic_shift2 = 5; // match DCI format 0/4 PDU
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optional uint32 freq_hop_flag = 6; // 0 no hopping, 1 hoppping
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optional uint32 freq_hop_map = 7; // Frequency hopping bits (0..4)
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optional uint32 ndi = 8; // New data indicator
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optional uint32 rv = 9; // Redundancy version
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optional uint32 harq_pid = 10; // The harq process id
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optional uint32 ultx_mode = 11; // A FLULM_* value
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optional uint32 tbs_size = 12; // The size of each TBS
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optional uint32 n_srs = 13; // Overlap indication with srs
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optional uint32 res_alloc = 14; // Type of resource allocation
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optional uint32 size = 15; // Size of the ULSCH PDU in bytes for UL Grant.
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optional uint32 dai = 16; // TDD only
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// optional uint32 tb_swap = 17; // Boolean. TB to codeword swap flag
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// optional uint32 pdcch_order = 19;
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// optional uint32 preamble_index = 20; // Only valid if pdcch_order = 1
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// optional uint32 prach_mask_index = 21; // Only valid if pdcch_order = 1
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// optional uint32 tbs_idx = 23; // The TBS index for Format 1A
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}
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//
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// Messages related to the creation of RLC PDUs
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//
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message flex_rlc_pdu {
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repeated flex_rlc_pdu_tb rlc_pdu_tb = 1; // list of parameters for the creation of RLC PDUs. One for each TB
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}
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message flex_rlc_pdu_tb {
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optional uint32 logical_channel_id = 1;
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optional uint32 size = 2; // Maximum RLC PDU to be created in bytes
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}
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//
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// MAC content types related enums
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//
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enum flex_dci_format {
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FLDCIF_1 = 0;
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FLDCIF_1A = 1;
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FLDCIF_1B = 2;
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FLDCIF_1C = 3;
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FLDCIF_1D = 4;
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FLDCIF_2 = 5;
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FLDCIF_2A = 6;
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FLDCIF_2B = 7;
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FLDCIF_3 = 8;
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FLDCIF_3A = 9;
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}
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enum flex_vrb_format {
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FLVRBF_LOCALIZED = 0;
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FLVRBF_DISTRIBUTED = 1;
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}
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enum flex_ngap_val {
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FLNGV_1 = 0;
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FLNGV_2 = 1;
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}
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