Navid Nikaein
2f2fde581d
* Add VCD timing for PDCP, RLC, and MAC * Update MAC-PHY interface * update eNB MAC DLSCH scheduler and preprocessor with component carrier * Add test case for dlsim performance git-svn-id: http://svn.eurecom.fr/openair4G/trunk@5708 818b1a75-f10b-46b9-bf7c-635c3b92a50f
119 lines
3.3 KiB
C
119 lines
3.3 KiB
C
/*******************************************************************************
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OpenAirInterface
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Copyright(c) 1999 - 2014 Eurecom
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OpenAirInterface is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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OpenAirInterface is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with OpenAirInterface.The full GNU General Public License is
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included in this distribution in the file called "COPYING". If not,
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see <http://www.gnu.org/licenses/>.
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Contact Information
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OpenAirInterface Admin: openair_admin@eurecom.fr
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OpenAirInterface Tech : openair_tech@eurecom.fr
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OpenAirInterface Dev : openair4g-devel@eurecom.fr
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Address : Eurecom, Compus SophiaTech 450, route des chappes, 06451 Biot, France.
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*******************************************************************************/
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/*! \file extern.h
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* \brief mac externs
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* \author Navid Nikaein and Raymond Knopp
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* \date 2010 - 2014
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* \version 1.0
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* \email navid.nikaein@eurecom.fr
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* @ingroup _mac
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*/
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#ifndef __MAC_EXTERN_H__
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#define __MAC_EXTERN_H__
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#ifdef USER_MODE
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//#include "stdio.h"
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#endif //USER_MODE
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#include "PHY/defs.h"
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#include "defs.h"
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#include "COMMON/mac_rrc_primitives.h"
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#ifdef PHY_EMUL
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//#include "SIMULATION/simulation_defs.h"
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#endif //PHY_EMUL
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#include "PHY_INTERFACE/defs.h"
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extern const uint32_t BSR_TABLE[BSR_TABLE_SIZE];
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//extern uint32_t EBSR_Level[63];
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extern UE_MAC_INST *UE_mac_inst;
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extern eNB_MAC_INST *eNB_mac_inst;
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extern MAC_RLC_XFACE *Mac_rlc_xface;
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extern uint8_t Is_rrc_registered;
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extern eNB_ULSCH_INFO eNB_ulsch_info[NUMBER_OF_eNB_MAX][NUMBER_OF_UE_MAX]; // eNBxUE = 8x8
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extern eNB_DLSCH_INFO eNB_dlsch_info[NUMBER_OF_eNB_MAX][NUMBER_OF_UE_MAX]; // eNBxUE = 8x8
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//#ifndef USER_MODE
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extern MAC_xface *mac_xface;
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extern RRC_XFACE *Rrc_xface;
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extern uint8_t Is_rrc_registered;
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#ifndef PHY_EMUL
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#ifndef PHYSIM
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#define NB_INST 1
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#else
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extern unsigned char NB_INST;
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#endif
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extern unsigned char NB_eNB_INST;
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extern unsigned char NB_UE_INST;
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extern unsigned char NB_RN_INST;
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extern unsigned short NODE_ID[1];
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extern void* bigphys_malloc(int);
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#else
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extern EMULATION_VARS *Emul_vars;
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#endif //PHY_EMUL
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extern int cqi_to_mcs[16];
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extern uint32_t RRC_CONNECTION_FLAG;
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extern DCI0_5MHz_TDD_1_6_t UL_alloc_pdu;
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extern DCI1A_5MHz_TDD_1_6_t RA_alloc_pdu;
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extern DCI1A_5MHz_TDD_1_6_t DLSCH_alloc_pdu1A;
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extern DCI1A_5MHz_TDD_1_6_t BCCH_alloc_pdu;
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extern DCI1A_5MHz_TDD_1_6_t CCCH_alloc_pdu;
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extern DCI1_5MHz_TDD_t DLSCH_alloc_pdu;
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extern DCI0_5MHz_FDD_t UL_alloc_pdu_fdd;
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extern DCI1A_5MHz_FDD_t DLSCH_alloc_pdu1A_fdd;
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extern DCI1A_5MHz_FDD_t RA_alloc_pdu_fdd;
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extern DCI1A_5MHz_FDD_t BCCH_alloc_pdu_fdd;
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extern DCI1A_5MHz_FDD_t CCCH_alloc_pdu_fdd;
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extern DCI1_5MHz_FDD_t DLSCH_alloc_pdu_fdd;
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extern DCI2_5MHz_2A_TDD_t DLSCH_alloc_pdu1;
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extern DCI2_5MHz_2A_TDD_t DLSCH_alloc_pdu2;
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extern DCI1E_5MHz_2A_M10PRB_TDD_t DLSCH_alloc_pdu1E;
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#endif //DEF_H
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