guibene
84fb51d88c
git-svn-id: http://svn.eurecom.fr/openair4G/trunk@4306 818b1a75-f10b-46b9-bf7c-635c3b92a50f
122 lines
2.7 KiB
Matlab
122 lines
2.7 KiB
Matlab
% Octave defines, according to pcie_interface.h
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% Parameters for rf_mode in structure exmimo_rf_t
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RXEN=1;
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TXEN=2;
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TXLPFENMASK=4;
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TXLPFEN=4;
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TXLPFMASK =15*(2^3);
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TXLPF14 =0;
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TXLPF10 =1*(2^3);
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TXLPF7 =2*(2^3);
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TXLPF6 =3*(2^3);
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TXLPF5 =4*(2^3);
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TXLPF4375 =5*(2^3);
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TXLPF35 =6*(2^3);
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TXLPF3 =7*(2^3);
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TXLPF275 =8*(2^3);
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TXLPF25 =9*(2^3);
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TXLPF192 =10*(2^3);
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TXLPF15 =11*(2^3);
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TXLPF1375 =12*(2^3);
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TXLPF125 =13*(2^3);
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TXLPF0875 =14*(2^3);
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TXLPF075 =15*(2^3);
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RXLPFENMASK=1*(2^7);
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RXLPFEN =128;
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RXLPFMASK =15*(2^8);
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RXLPF14 =0;
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RXLPF10 =1*(2^8);
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RXLPF7 =2*(2^8);
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RXLPF6 =3*(2^8);
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RXLPF5 =4*(2^8);
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RXLPF4375 =5*(2^8);
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RXLPF35 =6*(2^8);
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RXLPF3 =7*(2^8);
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RXLPF275 =8*(2^8);
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RXLPF25 =9*(2^8);
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RXLPF192 =10*(2^8);
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RXLPF15 =11*(2^8);
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RXLPF1375 =12*(2^8);
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RXLPF125 =13*(2^8);
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RXLPF0875 =14*(2^8);
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RXLPF075 =15*(2^8);
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LNAMASK=3*(2^12);
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LNADIS =0;
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LNA1ON =1*(2^12);
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LNA2ON =2*(2^12) ;
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LNA3ON =3*(2^12);
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LNAGAINMASK=3*(2^14);
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LNAByp =1*(2^14);
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LNAMed =2*(2^14);
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LNAMax =3*(2^14);
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RFBBMASK =7*(2^16);
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RFBBNORM =0;
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RFBBRXLPF =1*(2^16);
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RFBBRXVGA =2*(2^16);
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RFBBOUTPUT=3*(2^16);
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RFBBLNA1 =4*(2^16);
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RFBBLNA2 =5*(2^16);
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RFBBLNA3 =6*(2^16);
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RXLPFMODEMASK=3*(2^19);
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RXLPFNORM =0;
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RXLPFBYP =1*(2^19);
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RXLPFBPY2 =3*(2^19);
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TXLPFMODEMASK=1*(2^21);
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TXLPFNORM =0;
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TXLPFBYP =1*(2^21);
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RXOUTSW =1*(2^22);
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DMAMODE_TRXMASK =3*(2^23);
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DMAMODE_RX =1*(2^23);
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DMAMODE_TX =2*(2^23);
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rf_local = 31 + 31*(2^6) + 31*(2^12) + 31*(2^18);
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rf_rxdc = 0 + 0*(2^8); % DC offset ( DCOFF_I_RXFE [6:0], DCOFF_Q_RXFE[14:8] )
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rf_vcocal_19G = ((0xE)*(2^6)) + (0xE); % VCO calibration values for 1.9 GHz
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rf_vcocal_700 = ((0x24)*(2^6)) + (0x24); % 700 MHz
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rf_vcocal_850 = ((0x1d)*(2^6)) + (0x1d); %850 MHz
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rf_vcocal_859 = ((31)*(2^6)) + (31); %859.5 MHz
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%rf_vcocal_26G_eNB = ((0x1f)*(2^6)) + (0x13);
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%rf_vcocal_26G_UE = ((0x13)*(2^6)) + (0x1f);
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rf_vcocal_26G_UE = ((0x3)*(2^6)) + (0x26);
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rf_vcocal_26G_eNB = ((0x26)*(2^6)) + (0x0);
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% register values and masks for tdd_config
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DUPLEXMODE_MASK = 1*(2^0);
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DUPLEXMODE_FDD = 0;
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DUPLEXMODE_TDD = 2*(2^0);
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TXRXSWITCH_MASK = 3*(2^1);
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TXRXSWITCH_LSB = 0;
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TXRXSWITCH_FPGA = 1*(2^1);
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TXRXSWITCH_TESTRX = 2*(2^1);
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TXRXSWITCH_TESTTX = 3*(2^1);
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SWITCHSTATE_MASK = 1*(2^3);
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SWITCHSTATE_0 = 0;
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SWITCHSTATE_1 = 1*(2^3);
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TEST_ADACLOOP_MASK= 1*(2^4);
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TEST_ADACLOOP_EN = 1*(2^4);
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% multicard synchronization mode (multicard_syncmode)
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SYNCMODE_FREE = 0;
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SYNCMODE_MASTER = 1;
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SYNCMODE_SLAVE = 2;
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% external RF frontend
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TVWS_TDD = 0;
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DD_FDD = 1;
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DD_TDD = 2;
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B19G_TDD = 3;
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B24G_TDD = 4;
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B26G_TDD = 5;
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B26G_FDD = 6;
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B35G_TDD = 7;
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B50G_TDD = 8; |