Raymond Knopp
a7bc282302
Testing on Neoverse N1 (Ampere 3GHz). Tested only on a subset of phy-simulators. - Changes: - use SIMDE consistently - adaptations of LDPC decoder generator for ARMv8 performance - SIMDe modifications of Intel CRC to allow for aarch64 build. optimizations for 128-bit to improve performance of LDPC encode/decode on aarch64 (Neoverse 1) - added BG2 files for 128-bit ldpc encoder (aarch64) - testing on Xeon - testing on x86 - minor changes to build/run on x86 - change in crc.h after returning to aarch64 - removed some warning in ldpc decoder generator for x86_64 - char - Delete irrelevant constants - Correctly declare variables - Define stdbool for all architectures - Remove definition of _MM_SHUFFLE and use SIMDE_MM_SHUFFLE - Remove commented code - Fix CMakeLists.txt - Include SIMDE avx2 functions in tools_defs.h
This directory contains unitary testbenches/Monte Carlo Simulators for physical/transport channel processing: pbchsim.c // PBCH simulation testbench pdcchsim.c // PDCCH (DCI) simulation testbench, PCFICH + PHICH too (incomplete) dlsim.c // PDSCH simulation testbench ulsim.c // PUSCH simulation testbench pucchsim.c // PUCCH simulation testbench framegen.c // eNB Frame generator