354 lines
15 KiB
C
354 lines
15 KiB
C
/*
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* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership.
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* The OpenAirInterface Software Alliance licenses this file to You under
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* the OAI Public License, Version 1.0 (the "License"); you may not use this file
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* except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.openairinterface.org/?page_id=698
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*-------------------------------------------------------------------------------
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* For more information about the OpenAirInterface (OAI) Software Alliance:
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* contact@openairinterface.org
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*/
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/*! \file eNB_scheduler_dlsch.c
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* \brief procedures related to eNB for the DLSCH transport channel
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* \author Navid Nikaein and Raymond Knopp
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* \date 2010 - 2014
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* \email: navid.nikaein@eurecom.fr
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* \version 1.0
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* @ingroup _mac
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*/
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#include "assertions.h"
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#include "PHY/defs_eNB.h"
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#include "PHY/phy_extern.h"
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#include "PHY/LTE_TRANSPORT/transport_common_proto.h"
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#include "SCHED/sched_eNB.h"
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#include "LAYER2/MAC/mac.h"
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#include "LAYER2/MAC/mac_proto.h"
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#include "LAYER2/MAC/mac_extern.h"
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#include "common/utils/LOG/log.h"
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#include "common/utils/LOG/vcd_signal_dumper.h"
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#include "UTIL/OPT/opt.h"
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#include "OCG.h"
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#include "OCG_extern.h"
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#include "SIMULATION/TOOLS/sim.h" // for taus
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#include "T.h"
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extern RAN_CONTEXT_t RC;
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//------------------------------------------------------------------------------
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void
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schedule_ue_spec_phy_test(
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module_id_t module_idP,
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frame_t frameP,
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sub_frame_t subframeP,
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int* mbsfn_flag
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)
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//------------------------------------------------------------------------------
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{
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uint8_t CC_id;
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int UE_id=0;
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uint16_t N_RB_DL;
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uint16_t TBS;
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uint16_t nb_rb;
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unsigned char harq_pid = subframeP%5;
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uint16_t rnti = 0x1235;
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uint32_t rb_alloc = 0x1FFFFFFF;
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int32_t tpc = 1;
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int32_t mcs = 28;
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int32_t cqi = 15;
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int32_t ndi = subframeP/5;
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int32_t dai = 0;
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eNB_MAC_INST *eNB = RC.mac[module_idP];
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COMMON_channels_t *cc = eNB->common_channels;
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nfapi_dl_config_request_body_t *dl_req;
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nfapi_dl_config_request_pdu_t *dl_config_pdu;
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N_RB_DL = to_prb(cc->mib->message.dl_Bandwidth);
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for (CC_id=0; CC_id<MAX_NUM_CCs; CC_id++) {
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LOG_D(MAC, "doing schedule_ue_spec for CC_id %d\n",CC_id);
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dl_req = &eNB->DL_req[CC_id].dl_config_request_body;
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if (mbsfn_flag[CC_id]>0)
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continue;
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nb_rb = conv_nprb(0,rb_alloc,N_RB_DL);
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//printf("////////////////////////////////////*************************nb_rb = %d\n",nb_rb);
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TBS = get_TBS_DL(mcs,nb_rb);
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LOG_D(PHY,"schedule_ue_spec_phy_test: subframe %d/%d: nb_rb=%d, TBS=%d, mcs=%d (rb_alloc=%x, N_RB_DL=%d)\n",frameP,subframeP,nb_rb,TBS,mcs,rb_alloc,N_RB_DL);
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dl_config_pdu = &dl_req->dl_config_pdu_list[dl_req->number_pdu];
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memset((void*)dl_config_pdu,0,sizeof(nfapi_dl_config_request_pdu_t));
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dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE;
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dl_config_pdu->pdu_size = (uint8_t)(2+sizeof(nfapi_dl_config_dci_dl_pdu));
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dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.dci_format = NFAPI_DL_DCI_FORMAT_1;
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dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = get_aggregation(get_bw_index(module_idP,CC_id),cqi,format1);
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dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.resource_allocation_type = 0;
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dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.virtual_resource_block_assignment_flag = 0;
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dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.resource_block_coding = rb_alloc;
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dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti = rnti;
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dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = 1; // CRNTI : see Table 4-10 from SCF082 - nFAPI specifications
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dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.transmission_power = 6000; // equal to RS power
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dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.harq_process = harq_pid;
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dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tpc = tpc; // dont adjust power when retransmitting
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dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.new_data_indicator_1 = ndi;
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dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.mcs_1 = mcs;
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dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.redundancy_version_1 = 0;
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//deactivate second codeword
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dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.mcs_2 = 0;
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dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.redundancy_version_2 = 1;
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if (cc[CC_id].tdd_Config != NULL) { //TDD
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dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.downlink_assignment_index = dai;
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LOG_D(MAC,"[eNB %d] Initial transmission CC_id %d : harq_pid %d, dai %d, mcs %d\n",
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module_idP,CC_id,harq_pid,dai,mcs);
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} else {
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LOG_D(MAC,"[eNB %d] Initial transmission CC_id %d : harq_pid %d, mcs %d\n",
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module_idP,CC_id,harq_pid,mcs);
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}
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LOG_D(MAC,"Checking feasibility pdu %d (new sdu)\n",dl_req->number_pdu);
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if (!CCE_allocation_infeasible(module_idP,CC_id,1,subframeP,dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level,rnti)) {
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//ue_sched_ctl->round[CC_id][harq_pid] = 0;
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dl_req->number_dci++;
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dl_req->number_pdu++;
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// Toggle NDI for next time
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/*
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LOG_D(MAC,"CC_id %d Frame %d, subframeP %d: Toggling Format1 NDI for UE %d (rnti %x/%d) oldNDI %d\n",
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CC_id, frameP,subframeP,UE_id,
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rnti,harq_pid,UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid]);
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UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid]=1-UE_list->UE_template[CC_id][UE_id].oldNDI[harq_pid];
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UE_list->UE_template[CC_id][UE_id].oldmcs1[harq_pid] = mcs;
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UE_list->UE_template[CC_id][UE_id].oldmcs2[harq_pid] = 0;
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AssertFatal(UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated!=NULL,"physicalConfigDedicated is NULL\n");
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AssertFatal(UE_list->UE_template[CC_id][UE_id].physicalConfigDedicated->pdsch_ConfigDedicated!=NULL,"physicalConfigDedicated->pdsch_ConfigDedicated is NULL\n");
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*/
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fill_nfapi_dlsch_config(eNB,
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dl_req,
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TBS,
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eNB->pdu_index[CC_id],
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rnti,
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0, // type 0 allocation from 7.1.6 in 36.213
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0, // virtual_resource_block_assignment_flag
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rb_alloc, // resource_block_coding
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getQm(mcs),
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0, // redundancy version
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1, // transport blocks
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0, // transport block to codeword swap flag
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cc[CC_id].p_eNB == 1 ? 0 : 1, // transmission_scheme
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1, // number of layers
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1, // number of subbands
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// uint8_t codebook_index,
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4, // UE category capacity
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PDSCH_ConfigDedicated__p_a_dB0,
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0, // delta_power_offset for TM5
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0, // ngap
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0, // nprb
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cc[CC_id].p_eNB == 1 ? 1 : 2, // transmission mode
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0, //number of PRBs treated as one subband, not used here
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0 // number of beamforming vectors, not used here
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);
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eNB->TX_req[CC_id].sfn_sf = fill_nfapi_tx_req(&eNB->TX_req[CC_id].tx_request_body,
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(frameP*10)+subframeP,
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TBS,
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eNB->pdu_index[CC_id],
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eNB->UE_list.DLSCH_pdu[CC_id][0][(unsigned char)UE_id].payload[0]);
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}
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else {
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LOG_W(MAC,"[eNB_scheduler_phytest] DCI allocation infeasible!\n");
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}
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}
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}
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void schedule_ulsch_phy_test(module_id_t module_idP,frame_t frameP,sub_frame_t subframeP)
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{
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uint16_t first_rb[MAX_NUM_CCs];
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int UE_id = 0;
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uint8_t aggregation = 2;
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rnti_t rnti = 0x1235;
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uint8_t mcs = 0;
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uint8_t harq_pid = 0;
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uint32_t cqi_req = 0,cshift,ndi,tpc = 1;
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int32_t normalized_rx_power;
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int32_t target_rx_power= 178;
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int CC_id = 0;
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int nb_rb = 96;
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eNB_MAC_INST *eNB = RC.mac[module_idP];
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COMMON_channels_t *cc = eNB->common_channels;
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UE_list_t *UE_list=&eNB->UE_list;
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UE_TEMPLATE *UE_template;
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UE_sched_ctrl *UE_sched_ctrl;
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int sched_frame=frameP;
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int sched_subframe = (subframeP+4)%10;
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if (sched_subframe<subframeP) sched_frame++;
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nfapi_hi_dci0_request_body_t *hi_dci0_req = &eNB->HI_DCI0_req[CC_id][subframeP].hi_dci0_request_body;
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nfapi_hi_dci0_request_pdu_t *hi_dci0_pdu;
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//nfapi_ul_config_request_pdu_t *ul_config_pdu = &ul_req->ul_config_pdu_list[0];;
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nfapi_ul_config_request_body_t *ul_req = &eNB->UL_req[CC_id].ul_config_request_body;
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eNB->UL_req[CC_id].sfn_sf = (sched_frame<<4) + sched_subframe;
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eNB->HI_DCI0_req[CC_id][subframeP].sfn_sf = (frameP<<4)+subframeP;
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for (CC_id=0; CC_id<MAX_NUM_CCs; CC_id++) {
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//rnti = UE_RNTI(module_idP,UE_id);
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//leave out first RB for PUCCH
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first_rb[CC_id] = 1;
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// loop over all active UEs
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// if (eNB_UE_stats->mode == PUSCH) { // ue has a ulsch channel
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UE_template = &UE_list->UE_template[CC_id][UE_id];
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UE_sched_ctrl = &UE_list->UE_sched_ctrl[UE_id];
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harq_pid = subframe2harqpid(&cc[CC_id],sched_frame,sched_subframe);
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LOG_D(MAC,"Scheduling for frame %d, subframe %d => harq_pid %d\n",sched_frame,sched_subframe,harq_pid);
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RC.eNB[module_idP][CC_id]->pusch_stats_BO[UE_id][(frameP*10)+subframeP] = UE_template->TBS_UL[harq_pid];
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//power control
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//compute the expected ULSCH RX power (for the stats)
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// this is the normalized RX power and this should be constant (regardless of mcs
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normalized_rx_power = UE_sched_ctrl->pusch_snr[CC_id];
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// new transmission
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ndi = 1-UE_template->oldNDI_UL[harq_pid];
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UE_template->oldNDI_UL[harq_pid]=ndi;
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UE_list->eNB_UE_stats[CC_id][UE_id].normalized_rx_power=normalized_rx_power;
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UE_list->eNB_UE_stats[CC_id][UE_id].target_rx_power=target_rx_power;
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UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs1 = mcs;
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UE_template->mcs_UL[harq_pid] = mcs;//cmin (UE_template->pre_assigned_mcs_ul, openair_daq_vars.target_ue_ul_mcs); // adjust, based on user-defined MCS
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UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_mcs2 = mcs;
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// buffer_occupancy = UE_template->ul_total_buffer;
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UE_template->TBS_UL[harq_pid] = get_TBS_UL(mcs,nb_rb);
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UE_list->eNB_UE_stats[CC_id][UE_id].total_rbs_used_rx += nb_rb;
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UE_list->eNB_UE_stats[CC_id][UE_id].ulsch_TBS = get_TBS_UL(mcs,nb_rb);
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// buffer_occupancy -= TBS;
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// bad indices : 20 (40 PRB), 21 (45 PRB), 22 (48 PRB)
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//store for possible retransmission
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UE_template->nb_rb_ul[harq_pid] = nb_rb;
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UE_template->first_rb_ul[harq_pid] = first_rb[CC_id];
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UE_sched_ctrl->ul_scheduled |= (1<<harq_pid);
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// adjust total UL buffer status by TBS, wait for UL sdus to do final update
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//UE_template->ul_total_buffer = UE_template->TBS_UL[harq_pid];
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// Cyclic shift for DM RS
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cshift = 0;// values from 0 to 7 can be used for mapping the cyclic shift (36.211 , Table 5.5.2.1.1-1)
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// save it for a potential retransmission
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UE_template->cshift[harq_pid] = cshift;
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hi_dci0_pdu = &hi_dci0_req->hi_dci0_pdu_list[eNB->HI_DCI0_req[CC_id][subframeP].hi_dci0_request_body.number_of_dci+eNB->HI_DCI0_req[CC_id][subframeP].hi_dci0_request_body.number_of_hi];
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memset((void*)hi_dci0_pdu,0,sizeof(nfapi_hi_dci0_request_pdu_t));
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hi_dci0_pdu->pdu_type = NFAPI_HI_DCI0_DCI_PDU_TYPE;
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hi_dci0_pdu->pdu_size = 2+sizeof(nfapi_hi_dci0_dci_pdu);
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hi_dci0_pdu->dci_pdu.dci_pdu_rel8.dci_format = NFAPI_UL_DCI_FORMAT_0;
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hi_dci0_pdu->dci_pdu.dci_pdu_rel8.aggregation_level = aggregation;
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hi_dci0_pdu->dci_pdu.dci_pdu_rel8.rnti = rnti;
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hi_dci0_pdu->dci_pdu.dci_pdu_rel8.transmission_power = 6000;
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hi_dci0_pdu->dci_pdu.dci_pdu_rel8.resource_block_start = first_rb[CC_id];
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hi_dci0_pdu->dci_pdu.dci_pdu_rel8.number_of_resource_block = nb_rb;
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hi_dci0_pdu->dci_pdu.dci_pdu_rel8.mcs_1 = mcs;
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hi_dci0_pdu->dci_pdu.dci_pdu_rel8.cyclic_shift_2_for_drms = cshift;
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hi_dci0_pdu->dci_pdu.dci_pdu_rel8.frequency_hopping_enabled_flag = 0;
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hi_dci0_pdu->dci_pdu.dci_pdu_rel8.new_data_indication_1 = ndi;
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hi_dci0_pdu->dci_pdu.dci_pdu_rel8.tpc = tpc;
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hi_dci0_pdu->dci_pdu.dci_pdu_rel8.cqi_csi_request = cqi_req;
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hi_dci0_pdu->dci_pdu.dci_pdu_rel8.dl_assignment_index = UE_template->DAI_ul[sched_subframe];
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eNB->HI_DCI0_req[CC_id][subframeP].hi_dci0_request_body.number_of_dci++;
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// Add UL_config PDUs
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fill_nfapi_ulsch_config_request_rel8(&ul_req->ul_config_pdu_list[ul_req->number_of_pdus],
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cqi_req,
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cc,
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0,//UE_template->physicalConfigDedicated,
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get_tmode(module_idP,CC_id,UE_id),
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eNB->ul_handle,
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rnti,
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first_rb[CC_id], // resource_block_start
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nb_rb, // number_of_resource_blocks
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mcs,
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cshift, // cyclic_shift_2_for_drms
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0, // frequency_hopping_enabled_flag
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0, // frequency_hopping_bits
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ndi, // new_data_indication
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0, // redundancy_version
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harq_pid, // harq_process_number
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0, // ul_tx_mode
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0, // current_tx_nb
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0, // n_srs
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get_TBS_UL(mcs,nb_rb)
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);
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#if (RRC_VERSION >= MAKE_VERSION(14, 0, 0))
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if (UE_template->rach_resource_type>0) { // This is a BL/CE UE allocation
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fill_nfapi_ulsch_config_request_emtc(&ul_req->ul_config_pdu_list[ul_req->number_of_pdus],
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UE_template->rach_resource_type>2 ? 2 : 1,
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1, //total_number_of_repetitions
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1, //repetition_number
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(frameP*10)+subframeP);
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}
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#endif
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ul_req->number_of_pdus = 1;
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eNB->ul_handle++;
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add_ue_ulsch_info(module_idP,
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CC_id,
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UE_id,
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subframeP,
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S_UL_SCHEDULED);
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// increment first rb for next UE allocation
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first_rb[CC_id]+= nb_rb;
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} // loop of CC_id
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}
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