142 lines
5.6 KiB
C
142 lines
5.6 KiB
C
/*
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* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership.
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* The OpenAirInterface Software Alliance licenses this file to You under
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* the OAI Public License, Version 1.0 (the "License"); you may not use this file
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* except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.openairinterface.org/?page_id=698
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*-------------------------------------------------------------------------------
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* For more information about the OpenAirInterface (OAI) Software Alliance:
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* contact@openairinterface.org
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*/
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/*! \file vars.h
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* \brief mac vars
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* \author Navid Nikaein and Raymond Knopp
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* \date 2010 - 2014
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* \version 1.0
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* \email navid.nikaein@eurecom.fr
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* @ingroup _mac
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*/
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#ifndef __MAC_VARS_H__
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#define __MAC_VARS_H__
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#ifdef USER_MODE
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//#include "stdio.h"
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#endif //USER_MODE
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#include "PHY/defs.h"
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#include "defs.h"
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#include "COMMON/mac_rrc_primitives.h"
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const uint32_t BSR_TABLE[BSR_TABLE_SIZE]= {0,10,12,14,17,19,22,26,31,36,42,49,57,67,78,91,
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105,125,146,171,200,234,274,321,376,440,515,603,706,826,967,1132,
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1326,1552,1817,2127,2490,2915,3413,3995,4677,5467,6411,7505,8787,10287,12043,14099,
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16507,19325,22624,26487,31009,36304,42502,49759,58255,68201,79846,93479,109439, 128125,150000, 300000
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};
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// extended bsr table--currently not used
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const uint32_t Extended_BSR_TABLE[BSR_TABLE_SIZE] = {0,10,13,16,19,23,29,35,43,53,65,80,98,120,147,
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181,223,274,337,414,509,625,769,945,1162,1429,
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1757,2161,2657,3267,4017,4940,6074,7469,9185,
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11294,13888,17077,20999,25822,31752,39045,48012,
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59039,72598,89272,109774,134986,165989,204111,
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250990,308634,379519,466683,573866,705666,867737,
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1067031,1312097,1613447,1984009,2439678,3000000,
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6000000};
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//#define MAX_SIZE_OF_AGG3 576
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//#define MAX_SIZE_OF_AGG2 288
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//#define MAX_SIZE_OF_AGG1 144
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//#define MAX_SIZE_OF_AGG0 72
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/*
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* If the CQI is low, then scheduler will use a higher aggregation level and lower aggregation level otherwise
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* this is also dependent to transmission mode, where an offset could be defined
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*/
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// the follwoing three tables are calibrated for TXMODE 1 and 2
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const uint8_t cqi2fmt0_agg[MAX_SUPPORTED_BW][CQI_VALUE_RANGE]= {
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{3, 3, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0}, // 1.4_DCI0_CRC_Size= 37 bits
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//{3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0}, // 5_DCI0_CRC_SIZE = 41
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{3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, // 5_DCI0_CRC_SIZE = 41
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{3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0}, // 10_DCI0_CRC_SIZE = 43
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{3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0} // 20_DCI0_CRC_SIZE = 44
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};
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const uint8_t cqi2fmt1x_agg[MAX_SUPPORTED_BW][CQI_VALUE_RANGE]= {
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{3, 3, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0}, // 1.4_DCI0_CRC_Size < 38 bits
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{3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, // 5_DCI0_CRC_SIZE < 43
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{3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0}, // 10_DCI0_CRC_SIZE < 47
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{3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0} // 20_DCI0_CRC_SIZE < 55
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};
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const uint8_t cqi2fmt2x_agg[MAX_SUPPORTED_BW][CQI_VALUE_RANGE]= {
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{3, 3, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0}, // 1.4_DCI0_CRC_Size= 47 bits
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{3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, // 5_DCI0_CRC_SIZE = 55
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{3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0}, // 10_DCI0_CRC_SIZE = 59
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{3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 0, 0} // 20_DCI0_CRC_SIZE = 64
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};
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//uint32_t EBSR_Level[63]={0,10,13,16,19,23,29,35,43,53,65,80,98,120,147,181};
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uint32_t RRC_CONNECTION_FLAG;
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UE_MAC_INST *UE_mac_inst; //[NB_MODULE_MAX];
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MAC_RLC_XFACE *Mac_rlc_xface;
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/// Primary component carrier index of eNB
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int pCC_id[NUMBER_OF_eNB_MAX];
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eNB_ULSCH_INFO eNB_ulsch_info[NUMBER_OF_eNB_MAX][MAX_NUM_CCs][NUMBER_OF_UE_MAX]; // eNBxUE = 8x8
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eNB_DLSCH_INFO eNB_dlsch_info[NUMBER_OF_eNB_MAX][MAX_NUM_CCs][NUMBER_OF_UE_MAX]; // eNBxUE = 8x8
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#ifdef OPENAIR2
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unsigned char NB_eNB_INST=0;
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unsigned char NB_UE_INST=0;
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unsigned char NB_RN_INST=0;
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unsigned char NB_INST=0;
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#endif
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DCI0_5MHz_TDD_1_6_t UL_alloc_pdu;
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DCI1A_5MHz_TDD_1_6_t DLSCH_alloc_pdu1A;
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DCI1A_5MHz_TDD_1_6_t RA_alloc_pdu;
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DCI1A_5MHz_TDD_1_6_t BCCH_alloc_pdu;
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DCI1A_5MHz_TDD_1_6_t CCCH_alloc_pdu;
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DCI1_5MHz_TDD_t DLSCH_alloc_pdu;
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#if defined(Rel10) || defined(Rel14)
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DCI1C_5MHz_t MCCH_alloc_pdu;
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#endif
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DCI0_5MHz_FDD_t UL_alloc_pdu_fdd;
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DCI1A_5MHz_FDD_t DLSCH_alloc_pdu1A_fdd;
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DCI1A_5MHz_FDD_t RA_alloc_pdu_fdd;
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DCI1A_5MHz_FDD_t BCCH_alloc_pdu_fdd;
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DCI1A_5MHz_FDD_t CCCH_alloc_pdu_fdd;
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DCI1_5MHz_FDD_t DLSCH_alloc_pdu_fdd;
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DCI2_5MHz_2A_TDD_t DLSCH_alloc_pdu1;
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DCI2_5MHz_2A_TDD_t DLSCH_alloc_pdu2;
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DCI1E_5MHz_2A_M10PRB_TDD_t DLSCH_alloc_pdu1E;
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#endif
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