gauthier
c7518ecf42
git-svn-id: http://svn.eurecom.fr/openair4G/trunk@7885 818b1a75-f10b-46b9-bf7c-635c3b92a50f
119 lines
3.3 KiB
C
119 lines
3.3 KiB
C
/*******************************************************************************
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OpenAirInterface
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Copyright(c) 1999 - 2014 Eurecom
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OpenAirInterface is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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OpenAirInterface is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with OpenAirInterface.The full GNU General Public License is
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included in this distribution in the file called "COPYING". If not,
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see <http://www.gnu.org/licenses/>.
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Contact Information
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OpenAirInterface Admin: openair_admin@eurecom.fr
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OpenAirInterface Tech : openair_tech@eurecom.fr
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OpenAirInterface Dev : openair4g-devel@lists.eurecom.fr
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Address : Eurecom, Campus SophiaTech, 450 Route des Chappes, CS 50193 - 06904 Biot Sophia Antipolis cedex, FRANCE
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*******************************************************************************/
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#include "em1_drv.h"
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int em1_fifo_write(struct em1_private_s *pv, const uint32_t *buf, size_t count)
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{
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int retval = 0;
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size_t cnt = count;
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while (cnt > 0) {
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//read fifo state register
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uint32_t data = ioread32(pv->base + REG_FSTATUS);
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if (data & PUSH_FULL_STATUS_MSK) {
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/* Enable push fifo no full interrupt */
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pv->ie |= PUSH_NO_FULL_IRQ_MSK;
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iowrite32(pv->ie, pv->base + REG_FSTATUS);
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set_current_state(TASK_UNINTERRUPTIBLE);
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spin_unlock_irq(&pv->lock);
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// printk(KERN_DEBUG "sleep %08x %i", data, current->state);
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schedule();
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// printk(KERN_DEBUG "wake");
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spin_lock_irq(&pv->lock);
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continue;
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}
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data = *buf++;
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cnt--;
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iowrite32(data, pv->base + REG_FCMD);
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if (!pv->fifo_write_left) {
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/* Size must be retrieved from POP fifo entry */
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pv->fifo_write_left = data & 0xFF;
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} else {
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pv->fifo_write_left--;
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}
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if (!pv->fifo_write_left)
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break;
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}
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pv->ie &= ~PUSH_NO_FULL_IRQ_MSK;
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iowrite32(pv->ie, pv->base + REG_FSTATUS);
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return retval;
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}
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int em1_fifo_read(struct em1_private_s *pv, uint32_t *buf, size_t count)
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{
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int retval = 0;
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size_t cnt = count;
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while (cnt > 0) {
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//read fifo state register
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uint32_t data = ioread32(pv->base + REG_FSTATUS);
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if (data & POP_EMPTY_STATUS_MSK) {
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/* Enable pop fifo no empty interrupt */
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pv->ie |= POP_NO_EMPTY_IRQ_MSK;
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iowrite32(pv->ie, pv->base + REG_FSTATUS);
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set_current_state(TASK_UNINTERRUPTIBLE);
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spin_unlock_irq(&pv->lock);
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schedule();
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spin_lock_irq(&pv->lock);
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continue;
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}
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data = ioread32(pv->base + REG_FCMD);
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*buf++ = data;
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cnt--;
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if (!pv->fifo_read_left) {
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/* Size must be retrieved from POP fifo entry */
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pv->fifo_read_left = data & 0xFF;
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} else {
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pv->fifo_read_left--;
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}
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if (!pv->fifo_read_left)
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break;
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}
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pv->ie &= ~POP_NO_EMPTY_IRQ_MSK;
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iowrite32(pv->ie, pv->base + REG_FSTATUS);
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return retval;
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}
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