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Use special dlsim preprocessor

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This commit is contained in:
Robert Schmidt
2020-11-03 14:23:50 +01:00
parent b389e43eea
commit 0deb5d291d
1 changed files with 55 additions and 17 deletions
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openair1/SIMULATION/NR_PHY/dlsim.c
+55 -17
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@@ -150,6 +150,42 @@ int is_x2ap_enabled(void)
openair0_config_t openair0_cfg[MAX_CARDS];
/* specific dlsim DL preprocessor: uses rbStart/rbSize/mcs from command line of
dlsim, does not search for CCE/PUCCH occasion but simply sets to 0 */
int g_mcsIndex = -1, g_rbStart = -1, g_rbSize = -1;
void nr_dlsim_preprocessor(module_id_t module_id,
frame_t frame,
sub_frame_t slot,
int num_slots_per_tdd) {
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
AssertFatal(UE_info->num_UEs == 1, "can have only a single UE\n");
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[0];
/* manually set free CCE to 0 */
const int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
sched_ctrl->search_space = get_searchspace(sched_ctrl->active_bwp, target_ss);
uint8_t nr_of_candidates;
find_aggregation_candidates(&sched_ctrl->aggregation_level,
&nr_of_candidates,
sched_ctrl->search_space);
sched_ctrl->coreset = get_coreset(
sched_ctrl->active_bwp, sched_ctrl->search_space, 1 /* dedicated */);
sched_ctrl->cce_index = 0;
/* set "any" value for PUCCH (simulator evaluates PDSCH only) */
sched_ctrl->pucch_sched_idx = 0;
sched_ctrl->pucch_occ_idx = 0;
sched_ctrl->rbStart = g_rbStart;
sched_ctrl->rbSize = g_rbSize;
sched_ctrl->mcs = g_mcsIndex;
sched_ctrl->time_domain_allocation = 2;
sched_ctrl->mcsTableIdx = 0;
AssertFatal(sched_ctrl->rbStart >= 0, "invalid rbStart %d\n", sched_ctrl->rbStart);
AssertFatal(sched_ctrl->rbSize > 0, "invalid rbSize %d\n", sched_ctrl->rbSize);
AssertFatal(sched_ctrl->mcs >= 0, "invalid sched_ctrl->mcs %d\n", sched_ctrl->mcs);
sched_ctrl->numDmrsCdmGrpsNoData = 1;
}
int main(int argc, char **argv)
@@ -197,8 +233,6 @@ int main(int argc, char **argv)
//double pbch_sinr;
//int pbch_tx_ant;
int N_RB_DL=106,mu=1;
nfapi_nr_dl_tti_pdsch_pdu_rel15_t dlsch_config;
NR_sched_pucch pucch_sched;
//unsigned char frame_type = 0;
@@ -227,7 +261,6 @@ int main(int argc, char **argv)
randominit(0);
int mcsIndex_set=0,rbStart_set=0,rbSize_set=0;
int print_perf = 0;
FILE *scg_fd=NULL;
@@ -393,18 +426,15 @@ int main(int argc, char **argv)
case 'a':
dlsch_config.rbStart = atoi(optarg);
rbStart_set=1;
g_rbStart = atoi(optarg);
break;
case 'b':
dlsch_config.rbSize = atoi(optarg);
rbSize_set=1;
g_rbSize = atoi(optarg);
break;
case 'e':
dlsch_config.mcsIndex[0] = atoi(optarg);
mcsIndex_set=1;
g_mcsIndex = atoi(optarg);
break;
case 'm':
@@ -483,6 +513,7 @@ int main(int argc, char **argv)
RC.nb_nr_mac_CC[i] = 1;
mac_top_init_gNB();
gNB_mac = RC.nrmac[0];
gNB_mac->pre_processor_dl = nr_dlsim_preprocessor;
gNB_RRC_INST rrc;
memset((void*)&rrc,0,sizeof(rrc));
@@ -560,6 +591,12 @@ int main(int argc, char **argv)
// nr_phy_config_request_sim(gNB,N_RB_DL,N_RB_DL,mu,Nid_cell,SSB_positions);
// call MAC to configure common parameters
/* rrc_mac_config_req_gNB() has created one user, so set the scheduling
* parameters from command line in global variables that will be picked up by
* scheduling preprocessor */
if (g_mcsIndex < 0) g_mcsIndex = 9;
if (g_rbStart < 0) g_rbStart=0;
if (g_rbSize < 0) g_rbSize = N_RB_DL - g_rbStart;
double fs,bw;
@@ -687,11 +724,6 @@ int main(int argc, char **argv)
AssertFatal(input_fd==NULL,"Not ready for input signal file\n");
gNB->pbch_configured = 1;
gNB->ssb_pdu.ssb_pdu_rel15.bchPayload=0x001234;
if (mcsIndex_set==0) dlsch_config.mcsIndex[0]=9;
if (rbStart_set==0) dlsch_config.rbStart=0;
if (rbSize_set==0) dlsch_config.rbSize=N_RB_DL-dlsch_config.rbStart;
//Configure UE
rrc.carrier.MIB = (uint8_t*) malloc(4);
@@ -788,8 +820,14 @@ int main(int argc, char **argv)
for (int i=0; i<MAX_NUM_CORESET; i++)
gNB_mac->UE_info.num_pdcch_cand[0][i] = 0;
if (css_flag == 0) nr_schedule_uss_dlsch_phytest(0,frame,slot,&pucch_sched,&dlsch_config);
else nr_schedule_css_dlsch_phytest(0,frame,slot);
if (css_flag == 0) {
const uint8_t slots_per_frame[5] = {10, 20, 40, 80, 160};
const NR_TDD_UL_DL_Pattern_t *tdd_pattern = &scc->tdd_UL_DL_ConfigurationCommon->pattern1;
const int num_slots_per_tdd = slots_per_frame[*scc->ssbSubcarrierSpacing] >> (7 - tdd_pattern->dl_UL_TransmissionPeriodicity);
nr_schedule_ue_spec(0, frame, slot, num_slots_per_tdd);
} else {
nr_schedule_css_dlsch_phytest(0,frame,slot);
}
Sched_INFO.module_id = 0;
Sched_INFO.CC_id = 0;
Sched_INFO.frame = frame;
@@ -986,7 +1024,7 @@ int main(int argc, char **argv)
if (print_perf==1) {
printf("\ngNB TX function statistics (per %d us slot, NPRB %d, mcs %d, TBS %d, Kr %d (Zc %d))\n",
1000>>*scc->ssbSubcarrierSpacing,dlsch_config.rbSize,dlsch_config.mcsIndex[0],
1000>>*scc->ssbSubcarrierSpacing, g_rbSize, g_mcsIndex,
gNB->dlsch[0][0]->harq_processes[0]->pdsch_pdu.pdsch_pdu_rel15.TBSize[0]<<3,
gNB->dlsch[0][0]->harq_processes[0]->K,
gNB->dlsch[0][0]->harq_processes[0]->K/((gNB->dlsch[0][0]->harq_processes[0]->pdsch_pdu.pdsch_pdu_rel15.TBSize[0]<<3)>3824?22:10));