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fix: UE dosen't respond to pdcch order(contention based)

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This commit is contained in:
naoi
2018-02-07 20:40:06 +09:00
parent 3ea62dbdee
commit 0efa1185f3
2 changed files with 11 additions and 2 deletions
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openair1/PHY/LTE_TRANSPORT/dci_tools.c
+9 -1
View File
@@ -907,6 +907,7 @@ void fill_pdcch_order(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_a
((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->TPC = rel8->tpc;
((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid = rel8->harq_process;
((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index;
((DCI1A_1_5MHz_TDD_1_6_t *)dci_pdu)->padding = 0;
} else {
dci_alloc->dci_length = sizeof_DCI1A_1_5MHz_FDD_t;
((DCI1A_1_5MHz_FDD_t *)dci_pdu)->type = 1;
@@ -917,6 +918,7 @@ void fill_pdcch_order(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_a
((DCI1A_1_5MHz_FDD_t *)dci_pdu)->rv = rel8->redundancy_version_1;
((DCI1A_1_5MHz_FDD_t *)dci_pdu)->TPC = rel8->tpc;
((DCI1A_1_5MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process;
((DCI1A_1_5MHz_FDD_t *)dci_pdu)->padding = 0;
// printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
}
break;
@@ -931,7 +933,8 @@ void fill_pdcch_order(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_a
((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->rv = rel8->redundancy_version_1;
((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->TPC = rel8->tpc;
((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->harq_pid = rel8->harq_process;
((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index;
((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index;
((DCI1A_5MHz_TDD_1_6_t *)dci_pdu)->padding = 0;
// printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
} else {
dci_alloc->dci_length = sizeof_DCI1A_5MHz_FDD_t;
@@ -943,6 +946,7 @@ void fill_pdcch_order(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_a
((DCI1A_5MHz_FDD_t *)dci_pdu)->rv = rel8->redundancy_version_1;
((DCI1A_5MHz_FDD_t *)dci_pdu)->TPC = rel8->tpc;
((DCI1A_5MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process;
((DCI1A_5MHz_FDD_t *)dci_pdu)->padding = 0;
// printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
}
break;
@@ -958,6 +962,7 @@ void fill_pdcch_order(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_a
((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->TPC = rel8->tpc;
((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->harq_pid = rel8->harq_process;
((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index;
((DCI1A_10MHz_TDD_1_6_t *)dci_pdu)->padding = 0;
// printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
} else {
dci_alloc->dci_length = sizeof_DCI1A_10MHz_FDD_t;
@@ -969,6 +974,7 @@ void fill_pdcch_order(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_a
((DCI1A_10MHz_FDD_t *)dci_pdu)->rv = rel8->redundancy_version_1;
((DCI1A_10MHz_FDD_t *)dci_pdu)->TPC = rel8->tpc;
((DCI1A_10MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process;
((DCI1A_10MHz_FDD_t *)dci_pdu)->padding = 0;
// printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
}
break;
@@ -984,6 +990,7 @@ void fill_pdcch_order(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_a
((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->TPC = rel8->tpc;
((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->harq_pid = rel8->harq_process;
((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->dai = rel8->downlink_assignment_index;
((DCI1A_20MHz_TDD_1_6_t *)dci_pdu)->padding = 0;
// printf("TDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
} else {
dci_alloc->dci_length = sizeof_DCI1A_20MHz_FDD_t;
@@ -995,6 +1002,7 @@ void fill_pdcch_order(PHY_VARS_eNB *eNB,eNB_rxtx_proc_t *proc,DCI_ALLOC_t *dci_a
((DCI1A_20MHz_FDD_t *)dci_pdu)->rv = rel8->redundancy_version_1;
((DCI1A_20MHz_FDD_t *)dci_pdu)->TPC = rel8->tpc;
((DCI1A_20MHz_FDD_t *)dci_pdu)->harq_pid = rel8->harq_process;
((DCI1A_20MHz_FDD_t *)dci_pdu)->padding = 0;
// printf("FDD 1A: mcs %d, rballoc %x,rv %d, NPRB %d\n",mcs,rballoc,rv,NPRB);
}
break;
openair2/LAYER2/MAC/eNB_scheduler.c
+2 -1
View File
@@ -550,7 +550,8 @@ check_ul_failure(module_id_t module_idP, int CC_id, int UE_id,
UE_list->UE_sched_ctrl[UE_id].ul_failure_timer++;
// check threshold
if (UE_list->UE_sched_ctrl[UE_id].ul_failure_timer > 20000) {
if (UE_list->UE_sched_ctrl[UE_id].ul_failure_timer > 4000) {
// note: probably ul_failure_timer is should be less than UE radio link failure time(see T310/N310/N311)
// inform RRC of failure and clear timer
LOG_I(MAC,
"UE %d rnti %x: UL Failure after repeated PDCCH orders: Triggering RRC \n",