CCE list
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@@ -411,6 +411,9 @@ typedef struct {
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uint8_t n_symb;
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uint8_t rb_offset;
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uint8_t cr_mapping_type;
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uint8_t reg_bundle_size;
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uint8_t interleaver_size;
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uint8_t shift_index;
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uint8_t mux_pattern;
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uint8_t precoder_granularity;
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uint8_t first_slot;
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@@ -161,7 +161,7 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
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nfapi_nr_config_request_t config)
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{
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uint16_t mod_dmrs[NR_MAX_PDCCH_DMRS_LENGTH>>1];
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int16_t mod_dmrs[NR_MAX_PDCCH_DMRS_LENGTH>>1];
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uint8_t idx=0;
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uint16_t a;
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int k,l,k_prime,dci_idx, dmrs_idx;
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@@ -211,7 +211,7 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
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nr_pdcch_scrambling(dci_alloc.dci_pdu, dci_alloc.size, Nid, n_RNTI, scrambled_payload);
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// QPSK modulation
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uint16_t mod_dci[NR_MAX_DCI_SIZE>>1];
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int16_t mod_dci[NR_MAX_DCI_SIZE>>1];
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for (int i=0; i<encoded_length>>1; i++) {
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idx = (((scrambled_payload[i<<1]>>(i<<1))&1)<<1) ^ ((scrambled_payload[(i<<1)+1]>>((i<<1)+1))&1);
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mod_dci[i<<1] = nr_mod_table[(NR_MOD_TABLE_QPSK_OFFSET + idx)<<1];
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@@ -33,7 +33,7 @@ uint16_t nr_get_dci_size(nfapi_nr_dci_format_e format,
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nfapi_nr_config_request_t* config);
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uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
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t_nrPolar_paramsPtr *nrPolar_params,
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t_nrPolar_paramsPtr *nrPolar_params,
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uint32_t *gold_pdcch_dmrs,
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int32_t** txdataF,
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int16_t amp,
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@@ -46,4 +46,14 @@ void nr_pdcch_scrambling(uint32_t *in,
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uint32_t n_RNTI,
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uint32_t* out);
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void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
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int frame,
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int subframe,
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gNB_rxtx_proc_t *proc,
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NR_gNB_DCI_ALLOC_t *dci_alloc,
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nfapi_nr_dl_config_request_pdu_t *pdu);
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void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m);
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#endif //__PHY_NR_TRANSPORT_DCI__H
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@@ -33,6 +33,54 @@
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#include "nr_dci.h"
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void nr_fill_cce_list(NR_gNB_DCI_ALLOC_t* dci_alloc, uint16_t n_shift, uint8_t m) {
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nr_cce_t* cce;
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nr_reg_t* reg;
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nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params = &dci_alloc->pdcch_params;
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uint8_t L = dci_alloc->L;
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uint8_t bsize = pdcch_params->reg_bundle_size;
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uint8_t R = pdcch_params->interleaver_size;
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uint16_t N_reg = pdcch_params->n_rb * pdcch_params->n_symb;
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uint16_t Y, N_cce, M_s_max, n_CI=0, tmp, C;
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if (pdcch_params->config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1)
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AssertFatal(L>=4, "Invalid aggregation level for SIB1 configured PDCCH %d\n", L);
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N_cce = N_reg / NR_NB_REG_PER_CCE;
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/*Max number of candidates per aggregation level*/
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M_s_max = (L==4)?4:(L==8)?2:1;
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if (pdcch_params->search_space_type == NFAPI_NR_SEARCH_SPACE_TYPE_COMMON)
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Y = 0;
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else { //NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC
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}
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AssertFatal((N_reg%(bsize*R))==0, "CCE to REG interleaving: Invalid configuration leading to non integer C\n");
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C = N_reg/(bsize*R);
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tmp = L * (( Y + (uint16_t)(floor((m*N_cce)/(L*M_s_max))) + n_CI ) % ((uint16_t)floor(N_cce/L)));
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LOG_I(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d tmp %d\n", m, bsize, R, tmp);
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for (uint8_t cce_idx=0; cce_idx<L; cce_idx++) {
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cce = &dci_alloc->cce_list[cce_idx];
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cce->cce_idx = tmp + cce_idx;
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LOG_I(PHY, "cce_idx %d\n", cce->cce_idx);
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for (uint8_t reg_idx=0; reg_idx<NR_NB_REG_PER_CCE; reg_idx++) {
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reg = &cce->reg_list[reg_idx];
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if (pdcch_params->cr_mapping_type == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) {
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}
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else { // NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED
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}
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}
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}
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}
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void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
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int frame,
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int subframe,
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@@ -41,6 +89,7 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
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nfapi_nr_dl_config_request_pdu_t *pdu)
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{
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NR_DL_FRAME_PARMS *fp = &gNB->frame_parms;
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uint8_t n_shift;
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uint32_t *dci_pdu = dci_alloc->dci_pdu;
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memset((void*)dci_pdu,0,4*sizeof(uint32_t));
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nfapi_nr_dl_config_dci_dl_pdu_rel15_t *pdu_rel15 = &pdu->dci_dl_pdu.dci_dl_pdu_rel15;
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@@ -48,7 +97,7 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
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nfapi_nr_config_request_t *cfg = &gNB->gNB_config;
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uint16_t N_RB = fp->initial_bwp_dl.N_RB;
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uint8_t fsize=0, pos=0;
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uint8_t fsize=0, pos=0, cand_idx=0;
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/// Payload generation
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switch(params_rel15->dci_format) {
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@@ -89,12 +138,15 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
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dci_pdu[0], dci_pdu[1], dci_pdu[2], dci_pdu[3]);
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/// rest of DCI alloc
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dci_alloc->L = 2;
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dci_alloc->L = 4;
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memcpy((void*)&dci_alloc->pdcch_params, (void*)params_rel15, sizeof(nfapi_nr_dl_config_pdcch_parameters_rel15_t));
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dci_alloc->size = nr_get_dci_size(dci_alloc->pdcch_params.dci_format,
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dci_alloc->pdcch_params.rnti_type,
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&fp->initial_bwp_dl,
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cfg);
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n_shift = (dci_alloc->pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_MIB_SIB1)?
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cfg->sch_config.physical_cell_id.value : dci_alloc->pdcch_params.shift_index;
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nr_fill_cce_list(dci_alloc, n_shift, cand_idx);
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LOG_I(PHY, "DCI type %d payload (size %d) generated\n", dci_alloc->pdcch_params.dci_format, dci_alloc->size);
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@@ -144,4 +196,3 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
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return;
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}
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@@ -168,6 +168,8 @@ void nr_configure_css_dci_from_mib(nfapi_nr_dl_config_pdcch_parameters_rel15_t*
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pdcch_params->config_type = NFAPI_NR_CSET_CONFIG_MIB_SIB1;
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pdcch_params->cr_mapping_type = NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED;
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pdcch_params->precoder_granularity = NFAPI_NR_CSET_SAME_AS_REG_BUNDLE;
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pdcch_params->reg_bundle_size = 6;
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pdcch_params->interleaver_size = 2;
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}
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void nr_configure_css_dci_from_pdcch_config(nfapi_nr_dl_config_pdcch_parameters_rel15_t* pdcch_params,
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