Check for CCE allocation in UL PP
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@@ -1353,7 +1353,7 @@ schedule_ulsch_rnti(module_id_t module_idP,
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if (UE_template_ptr->pre_allocated_nb_rb_ul < 1)
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continue;
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int dci_ul_pdu_idx = -1;
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int dci_ul_pdu_idx = UE_template_ptr->pre_dci_ul_pdu_idx;
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if (dci_ul_pdu_idx < 0) {
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dci_ul_pdu_idx = CCE_try_allocate_ulsch(
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module_idP, CC_id, subframeP, UE_id, UE_sched_ctrl_ptr->dl_cqi[CC_id]);
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@@ -831,6 +831,9 @@ typedef struct {
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/// index of Allocated RBs by the ulsch preprocessor
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int8_t pre_allocated_rb_table_index_ul;
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/// index of allocated HI_DCI0
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int pre_dci_ul_pdu_idx;
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/// total allocated RBs
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int8_t total_allocated_rbs;
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@@ -509,6 +509,11 @@ int round_robin_ul(module_id_t Mod_id,
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UE_info->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid]);
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continue;
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}
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const uint8_t cqi = UE_info->UE_sched_ctrl[UE_id].dl_cqi[CC_id];
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const int idx = CCE_try_allocate_ulsch(Mod_id, CC_id, subframe, UE_id, cqi);
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if (idx < 0)
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continue; // cannot allocate CCE
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UE_template->pre_dci_ul_pdu_idx = idx;
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if (rbs[0].length >= nb_rb) { // fits in first contiguous region
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UE_template->pre_first_nb_rb_ul = rbs[0].start;
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rbs[0].length -= nb_rb;
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@@ -531,6 +536,8 @@ int round_robin_ul(module_id_t Mod_id,
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"cannot allocate UL retransmission for UE %d (nb_rb %d)\n",
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UE_id,
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nb_rb);
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UE_template->pre_dci_ul_pdu_idx = -1; // do not need CCE
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RC.mac[Mod_id]->HI_DCI0_req[CC_id][subframe].hi_dci0_request_body.number_of_dci--;
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continue;
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}
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LOG_D(MAC, "%4d.%d UE %d retx %d RBs at start %d\n",
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@@ -640,8 +647,15 @@ int round_robin_ul(module_id_t Mod_id,
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while (num_ue_sched < nr[r]) {
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while (rb_idx_required[sUE_id] == 0)
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sUE_id = next_ue_list_looped(UE_list, sUE_id);
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/* TODO: check that CCE allocated is feasible. If it is not, reduce
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* nr[r] by one as this would been one opportunity */
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const int cqi = UE_info->UE_sched_ctrl[sUE_id].dl_cqi[CC_id];
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const int idx = CCE_try_allocate_ulsch(Mod_id, CC_id, subframe, sUE_id, cqi);
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if (idx < 0) {
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LOG_D(MAC, "cannot allocate CCE for UE %d, skipping\n", sUE_id);
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nr[r]--;
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sUE_id = next_ue_list_looped(UE_list, sUE_id); // next candidate
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continue;
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}
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UE_info->UE_template[CC_id][sUE_id].pre_dci_ul_pdu_idx = idx;
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*cur_UE = sUE_id;
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cur_UE = &UE_sched.next[sUE_id];
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rb_idx_given[sUE_id] = min(start_idx, rb_idx_required[sUE_id]);
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@@ -729,6 +743,7 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id,
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UE_template->pre_allocated_nb_rb_ul = 0;
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UE_template->pre_allocated_rb_table_index_ul = -1;
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UE_template->pre_first_nb_rb_ul = 0;
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UE_template->pre_dci_ul_pdu_idx = -1;
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const rnti_t rnti = UE_RNTI(Mod_id, UE_id);
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if (rnti == NOT_A_RNTI) {
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@@ -775,7 +790,7 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id,
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sched_frameP,
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sched_subframeP,
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&UE_to_sched,
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3, // max_num_ue
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4, // max_num_ue
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n_contig,
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rbs);
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