Dynamic PDCCH aggregation level
The aggregation level search order for PDCCH candidates is modified: - the search starts from desired_agg_level_index, which is a value from 0 to 4 proportial to pdcch_cl_adjust. - pdcch_cl_adjust is a value between 0 and 1 that indicates PDCCH channel quality by averaging HARQ DTX rate. A value of 0 means perfect channel, a value o 1 means impaired channel.
This commit is contained in:
@@ -38,6 +38,28 @@ The actual scheduler implementation can be found in functions `pf_dl()` and
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[`gNB_scheduler_ulsch.c`](../../openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c)
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(for UL), respectively.
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## PDDCH aggregation level
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PDCCH aggregation level is selected using closed loop controller, where DL HARQ
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feedback is the controller feedback signal. It is used to increment `pdcch_cl_adjust`
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variable if no feedback is detected and decrement the variable when feedback is detected.
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`pdcch_cl_adjust` is later mapped PDCCH aggregation level range.
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The value of `pdcch_cl_adjust` is clamped to range <0,1>, the increment value is 0.05 while
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the decrement value is 0.01.
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### Examples:
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#### Example 1:
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Say we have 90% PDCCH success rate at aggregation level 1, `pdcch_cl_adjust` will stay at 0
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for most of the time. 2 consecutive PDCCH failures will not result in increasing the aggregation
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level (because (0.05 + 0.05) * 4 = 0.4 which is closer to 0 than to 1). If PDCCH fails 3 times
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in a row the aggregation level will change to 2 and hopefully back to 1 once more PDDCH successes
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happen.
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### Example 2
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Say we have 0% PDCCH success rate (radio link failure scenario) but `pdcch_cl_adjust` is 0 indicating
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perfect PDCCH channel. it would take ~18 PDCCH failures to reach maximum aggregation level.
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# Periodic output and interpretation
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The scheduler periodically outputs statistics that can help you judge the radio
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@@ -99,7 +99,7 @@ static void nr_generate_dci(PHY_VARS_gNB *gNB,
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if (dci_pdu->RNTI != 0xFFFF)
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LOG_D(NR_PHY_DCI,
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"DL_DCI : rb_offset %d, nb_rb %d, DMRS length per symbol %d\t DCI encoded length %d (precoder_granularity %d, "
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"reg_mapping %d), Scrambling_Id %d, ScramblingRNTI %x, PayloadSizeBits %d\n",
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"reg_mapping %d), Scrambling_Id %d, ScramblingRNTI %x, PayloadSizeBits %d AggregationLevel %d\n",
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rb_offset,
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n_rb,
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dmrs_length,
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@@ -108,7 +108,8 @@ static void nr_generate_dci(PHY_VARS_gNB *gNB,
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pdcch_pdu_rel15->CceRegMappingType,
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dci_pdu->ScramblingId,
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dci_pdu->ScramblingRNTI,
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dci_pdu->PayloadSizeBits);
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dci_pdu->PayloadSizeBits,
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dci_pdu->AggregationLevel);
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dmrs_length += rb_offset*6; // To accommodate more DMRS symbols in case of rb offset
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/// DMRS QPSK modulation
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@@ -874,7 +874,8 @@ static void nr_generate_Msg3_retransmission(module_id_t module_idP,
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ss,
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coreset,
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&ra->sched_pdcch,
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true);
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true,
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0);
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if (CCEIndex < 0) {
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LOG_E(NR_MAC, "UE %04x cannot find free CCE!\n", ra->rnti);
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return;
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@@ -1484,7 +1485,7 @@ static void nr_generate_Msg2(module_id_t module_idP,
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}
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uint8_t aggregation_level;
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int CCEIndex = get_cce_index(nr_mac, CC_id, slotP, 0, &aggregation_level, beam.idx, ss, coreset, &ra->sched_pdcch, true);
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int CCEIndex = get_cce_index(nr_mac, CC_id, slotP, 0, &aggregation_level, beam.idx, ss, coreset, &ra->sched_pdcch, true, 0);
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if (CCEIndex < 0) {
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LOG_W(NR_MAC, "UE %04x: %d.%d cannot find free CCE for Msg2!\n", ra->rnti, frameP, slotP);
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@@ -2006,7 +2007,8 @@ static void nr_generate_Msg4_MsgB(module_id_t module_idP,
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ss,
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coreset,
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&ra->sched_pdcch,
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true);
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true,
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0);
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if (CCEIndex < 0) {
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LOG_E(NR_MAC, "Cannot find free CCE for RA RNTI 0x%04x!\n", ra->rnti);
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@@ -553,7 +553,8 @@ static bool allocate_dl_retransmission(module_id_t module_id,
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sched_ctrl->search_space,
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sched_ctrl->coreset,
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&sched_ctrl->sched_pdcch,
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false);
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false,
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sched_ctrl->pdcch_cl_adjust);
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if (CCEIndex<0) {
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LOG_D(NR_MAC, "[UE %04x][%4d.%2d] could not find free CCE for DL DCI retransmission\n", UE->rnti, frame, slot);
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return false;
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@@ -817,7 +818,8 @@ static void pf_dl(module_id_t module_id,
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sched_ctrl->search_space,
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sched_ctrl->coreset,
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&sched_ctrl->sched_pdcch,
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false);
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false,
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sched_ctrl->pdcch_cl_adjust);
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if (CCEIndex < 0) {
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LOG_D(NR_MAC, "[UE %04x][%4d.%2d] could not find free CCE for DL DCI\n", rnti, frame, slot);
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reset_beam_status(&mac->beam_info,
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@@ -148,7 +148,8 @@ void nr_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_t s
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sched_ctrl->search_space,
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sched_ctrl->coreset,
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&sched_ctrl->sched_pdcch,
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false);
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false,
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0);
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AssertFatal(CCEIndex >= 0, "Could not find CCE for UE %04x\n", UE->rnti);
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NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch;
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@@ -312,7 +313,8 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
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sched_ctrl->search_space,
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sched_ctrl->coreset,
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&sched_ctrl->sched_pdcch,
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false);
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false,
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0);
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if (CCEIndex < 0) {
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LOG_E(MAC, "%s(): CCE list not empty, couldn't schedule PUSCH\n", __func__);
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return false;
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@@ -119,6 +119,9 @@ static const uint16_t cqi_table3[16][2] = {{0, 0},
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{6, 6660},
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{6, 7720}};
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static void determine_aggregation_level_search_order(int agg_level_search_order[NUM_PDCCH_AGG_LEVELS],
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float pdcch_cl_adjust);
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uint8_t get_dl_nrOfLayers(const NR_UE_sched_ctrl_t *sched_ctrl,
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const nr_dci_format_t dci_format) {
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@@ -550,15 +553,18 @@ int get_cce_index(const gNB_MAC_INST *nrmac,
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const NR_SearchSpace_t *ss,
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const NR_ControlResourceSet_t *coreset,
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NR_sched_pdcch_t *sched_pdcch,
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bool is_common)
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bool is_common,
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float pdcch_cl_adjust)
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{
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const uint32_t Y = is_common ? 0 : get_Y(ss, slot, rnti);
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uint8_t nr_of_candidates;
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for (int i = 0; i < 5; i++) {
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// for now taking the lowest value among the available aggregation levels
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find_aggregation_candidates(aggregation_level, &nr_of_candidates, ss, 1 << i);
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if(nr_of_candidates > 0)
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int agg_level_search_order[NUM_PDCCH_AGG_LEVELS];
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determine_aggregation_level_search_order(agg_level_search_order, pdcch_cl_adjust);
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for (int i = 0; i < NUM_PDCCH_AGG_LEVELS; i++) {
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find_aggregation_candidates(aggregation_level, &nr_of_candidates, ss, 1 << agg_level_search_order[i]);
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if (nr_of_candidates > 0)
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break;
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}
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int CCEIndex = find_pdcch_candidate(nrmac, CC_id, *aggregation_level, nr_of_candidates, beam_idx, sched_pdcch, coreset, Y);
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@@ -2516,6 +2522,7 @@ NR_UE_info_t *add_new_nr_ue(gNB_MAC_INST *nr_mac, rnti_t rntiP, NR_CellGroupConf
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sched_ctrl->ta_update = 31;
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sched_ctrl->sched_srs.frame = -1;
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sched_ctrl->sched_srs.slot = -1;
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sched_ctrl->pdcch_cl_adjust = 0;
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// initialize LCID structure
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seq_arr_init(&sched_ctrl->lc_config, sizeof(nr_lc_config_t));
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@@ -3524,3 +3531,31 @@ bool nr_mac_get_new_rnti(NR_UEs_t *UEs, const NR_RA_t *ra_base, int ra_count, rn
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} while (loop < 100 && (exist_connected_ue || exist_in_pending_ra_ue));
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return loop < 100; // nothing found: loop count 100
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}
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/// @brief Orders PDCCH aggregation levels so that we first check desired aggregation level according to
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/// pdcch_cl_adjust
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/// @param agg_level_search_order in/out 5-element array of aggregation levels from 0 to 4
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/// @param pdcch_cl_adjust value from 0 to 1 indication channel impariments (0 - good channel, 1 - bad channel)
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static void determine_aggregation_level_search_order(int agg_level_search_order[NUM_PDCCH_AGG_LEVELS], float pdcch_cl_adjust)
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{
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int desired_agg_level_index = round(4 * pdcch_cl_adjust);
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int agg_level_search_index = 0;
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for (int i = desired_agg_level_index; i < NUM_PDCCH_AGG_LEVELS; i++) {
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agg_level_search_order[agg_level_search_index++] = i;
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}
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for (int i = desired_agg_level_index - 1; i >= 0; i--) {
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agg_level_search_order[agg_level_search_index++] = i;
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}
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}
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/// @brief Update PDCCH closed loop adjust for UE depending on detection of feedback.
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/// @param sched_ctrl UE scheduling control info
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/// @param feedback_not_detected Whether feedback (PUSCH or HARQ) was detected
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void nr_mac_update_pdcch_closed_loop_adjust(NR_UE_sched_ctrl_t *sched_ctrl, bool feedback_not_detected)
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{
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if (feedback_not_detected) {
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sched_ctrl->pdcch_cl_adjust = min(1, sched_ctrl->pdcch_cl_adjust + 0.05);
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} else {
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sched_ctrl->pdcch_cl_adjust = max(0, sched_ctrl->pdcch_cl_adjust - 0.01);
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}
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}
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@@ -787,6 +787,7 @@ void handle_nr_uci_pucch_0_1(module_id_t mod_id,
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const int8_t pid = sched_ctrl->feedback_dl_harq.head;
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remove_front_nr_list(&sched_ctrl->feedback_dl_harq);
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LOG_D(NR_MAC,"%4d.%2d bit %d pid %d ack/nack %d\n",frame, slot, harq_bit,pid,harq_value);
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nr_mac_update_pdcch_closed_loop_adjust(sched_ctrl, harq_confidence != 0);
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handle_dl_harq(UE, pid, harq_value == 0 && harq_confidence == 0, nrmac->dl_bler.harq_round_max);
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if (!UE->Msg4_MsgB_ACKed && harq_value == 0 && harq_confidence == 0)
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UE->Msg4_MsgB_ACKed = true;
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@@ -1742,7 +1742,8 @@ static bool allocate_ul_retransmission(gNB_MAC_INST *nrmac,
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sched_ctrl->search_space,
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sched_ctrl->coreset,
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&sched_ctrl->sched_pdcch,
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false);
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false,
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sched_ctrl->pdcch_cl_adjust);
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if (CCEIndex<0) {
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LOG_D(NR_MAC, "[UE %04x][%4d.%2d] no free CCE for retransmission UL DCI UE\n", UE->rnti, frame, slot);
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return false;
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@@ -1926,7 +1927,8 @@ static void pf_ul(module_id_t module_id,
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sched_ctrl->search_space,
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sched_ctrl->coreset,
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&sched_ctrl->sched_pdcch,
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false);
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false,
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sched_ctrl->pdcch_cl_adjust);
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if (CCEIndex < 0) {
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LOG_D(NR_MAC, "[UE %04x][%4d.%2d] no free CCE for UL DCI (BSR 0)\n", UE->rnti, frame, slot);
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reset_beam_status(&nrmac->beam_info, sched_frame, sched_slot, UE->UE_beam_index, n, beam.new_beam);
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@@ -2073,7 +2075,8 @@ static void pf_ul(module_id_t module_id,
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sched_ctrl->search_space,
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sched_ctrl->coreset,
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&sched_ctrl->sched_pdcch,
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false);
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false,
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sched_ctrl->pdcch_cl_adjust);
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if (CCEIndex < 0) {
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reset_beam_status(&nrmac->beam_info, frame, slot, iterator->UE->UE_beam_index, n_dl, dci_beam.new_beam);
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@@ -433,7 +433,8 @@ int get_cce_index(const gNB_MAC_INST *nrmac,
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const NR_SearchSpace_t *ss,
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const NR_ControlResourceSet_t *coreset,
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NR_sched_pdcch_t *sched_pdcch,
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bool is_common);
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bool is_common,
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float pdcch_cl_adjust);
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bool nr_find_nb_rb(uint16_t Qm,
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uint16_t R,
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@@ -493,5 +494,6 @@ bool nr_mac_add_lcid(NR_UE_sched_ctrl_t *sched_ctrl, const nr_lc_config_t *c);
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bool nr_mac_remove_lcid(NR_UE_sched_ctrl_t *sched_ctrl, long lcid);
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bool nr_mac_get_new_rnti(NR_UEs_t *UEs, const NR_RA_t *ra_base, int ra_count, rnti_t *rnti);
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void nr_mac_update_pdcch_closed_loop_adjust(NR_UE_sched_ctrl_t *sched_ctrl, bool feedback_not_detected);
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#endif /*__LAYER2_NR_MAC_PROTO_H__*/
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@@ -125,6 +125,15 @@ typedef enum {
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nrRA_WAIT_Msg4_MsgB_ACK,
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} RA_gNB_state_t;
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typedef enum {
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PDCCH_AGG_LEVEL1 = 0,
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PDCCH_AGG_LEVEL2,
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PDCCH_AGG_LEVEL4,
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PDCCH_AGG_LEVEL8,
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PDCCH_AGG_LEVEL16,
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NUM_PDCCH_AGG_LEVELS
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} Pdcch_Aggregation_Level_t;
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static const char *const nrra_text[] =
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{"IDLE", "Msg2", "WAIT_MsgA_PUSCH", "WAIT_Msg3", "Msg3_retransmission", "Msg3_dcch_dtch", "Msg4", "MsgB", "WAIT_Msg4_ACK"};
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@@ -675,6 +684,10 @@ typedef struct {
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/// per-LC configuration
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seq_arr_t lc_config;
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// pdcch closed loop adjust for PDCCH aggregation level, range <0, 1>
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// 0 - good channel, 1 - bad channel
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float pdcch_cl_adjust;
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} NR_UE_sched_ctrl_t;
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typedef struct {
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