Fixes when handling with multiple Coresets

This commit is contained in:
luis_pereira87
2022-01-18 00:12:56 +00:00
parent 2b6c64c98c
commit 1bd68ef261
4 changed files with 16 additions and 13 deletions
+5 -2
View File
@@ -307,8 +307,11 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
}
memset(RC.nrmac[module_idP]->cce_list[0][0],0,MAX_NUM_CCE*sizeof(int)); // coreset0
for(int i_bwp = 0; i_bwp < MAX_NUM_BWP; i_bwp++)
memset(RC.nrmac[module_idP]->cce_list[i_bwp][1],0,MAX_NUM_CCE*sizeof(int)); // coresetid i (0 to coreset1 on initialBWP)
for(int i_bwp = 0; i_bwp < MAX_NUM_BWP; i_bwp++) {
for (int i_coreset = 1; i_coreset < MAX_NUM_CORESET; i_coreset++) {
memset(RC.nrmac[module_idP]->cce_list[i_bwp][i_coreset],0,MAX_NUM_CCE*sizeof(int)); // coresetid i (0 to coreset1 on initialBWP)
}
}
NR_UE_info_t *UE_info = &RC.nrmac[module_idP]->UE_info;
for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id])
@@ -1117,7 +1117,7 @@ void prepare_dci(const NR_CellGroupConfig_t *CellGroup,
if (pdsch_Config->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList != NULL)
AssertFatal(1==0,"Aperiodic ZP CSI-RS currently not supported\n");
// transmission configuration indication
if (pdcch_Config->controlResourceSetToAddModList->list.array[controlResourceSetId-1]->tci_PresentInDCI != NULL)
if (pdcch_Config->controlResourceSetToAddModList->list.array[0]->tci_PresentInDCI != NULL)
AssertFatal(1==0,"TCI in DCI currently not supported\n");
//srs resource set
if (CellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->carrierSwitching!=NULL) {
@@ -1852,18 +1852,18 @@ int find_nr_UE_id(module_id_t mod_idP, rnti_t rntiP)
return -1;
}
void set_Y(int Y[3][160], rnti_t rnti) {
void set_Y(int Y[MAX_NUM_CORESET][160], rnti_t rnti) {
const int A[3] = {39827, 39829, 39839};
const int D = 65537;
Y[0][0] = (A[0] * rnti) % D;
Y[1][0] = (A[1] * rnti) % D;
Y[2][0] = (A[2] * rnti) % D;
for (int i = 0; i < MAX_NUM_CORESET; i++) {
Y[i][0] = (A[i%3] * rnti) % D;
}
for (int s = 1; s < 160; s++) {
Y[0][s] = (A[0] * Y[0][s - 1]) % D;
Y[1][s] = (A[1] * Y[1][s - 1]) % D;
Y[2][s] = (A[2] * Y[2][s - 1]) % D;
for (int i = 0; i < MAX_NUM_CORESET; i++) {
Y[i][s] = (A[i%3] * Y[i][s - 1]) % D;
}
}
}
+2 -2
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@@ -73,7 +73,7 @@
/* Defs */
#define MAX_NUM_BWP 5
#define MAX_NUM_CORESET 2
#define MAX_NUM_CORESET 12
#define MAX_NUM_CCE 90
#define MAX_HARQ_ROUNDS 4
/*!\brief Maximum number of random access process */
@@ -654,7 +654,7 @@ typedef struct {
rnti_t rnti[MAX_MOBILES_PER_GNB];
NR_CellGroupConfig_t *CellGroup[MAX_MOBILES_PER_GNB];
/// CCE indexing
int Y[MAX_MOBILES_PER_GNB][3][160];
int Y[MAX_MOBILES_PER_GNB][MAX_NUM_CORESET][160];
int m[MAX_MOBILES_PER_GNB];
int num_pdcch_cand[MAX_MOBILES_PER_GNB][MAX_NUM_CORESET];
// UE selected beam index
+1 -1
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@@ -1608,7 +1608,7 @@ void fill_initial_SpCellConfig(rnti_t rnti,
NR_PUCCH_Resource_t *pucchres0=calloc(1,sizeof(*pucchres0));
pucchres0->pucch_ResourceId=0;
//pucchres0->startingPRB=0;
pucchres0->startingPRB=(8+rnti) % curr_bwp;
pucchres0->startingPRB=(8+uid) % curr_bwp;
LOG_D(NR_RRC, "pucchres0->startPRB %ld rnti %d curr_bwp %d\n", pucchres0->startingPRB, rnti, curr_bwp);
pucchres0->intraSlotFrequencyHopping=NULL;
pucchres0->secondHopPRB=NULL;