FlexRAN: add slice configuration protobuf messages
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@@ -58,6 +58,87 @@ enum flex_qam {
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FLEQ_MOD_64QAM = 1;
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}
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//
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// Slice config related structures and enums
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//
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enum flex_dl_sorting {
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CR_ROUND = 0; // Highest HARQ first
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CR_SRB12 = 1; // Highest SRB1+2 first
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CR_HOL = 2; // Highest HOL first
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CR_LC = 3; // Greatest RLC buffer first
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CR_CQI = 4; // Highest CQI first
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CR_LCP = 5; // Highest LC priority first
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}
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enum flex_ul_sorting {
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CRU_ROUND = 0; // Highest HARQ first
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CRU_BUF = 1; // Highest BSR first
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CRU_BTS = 2; // More bytes to schedule first
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CRU_MCS = 3; // Highest MCS first
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CRU_LCP = 4; // Highest LC priority first
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CRU_HOL = 5; // Highest HOL first
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}
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enum flex_dl_accounting_policy {
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POL_FAIR = 0;
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POL_GREEDY = 1;
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POL_NUM = 2;
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}
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enum flex_ul_accounting_policy {
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POLU_FAIR = 0;
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POLU_GREEDY = 1;
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POLU_NUM = 2;
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}
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enum flex_slice_label {
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xMBB = 0;
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URLLC = 1;
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mMTC = 2;
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xMTC = 3;
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Other = 4;
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}
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message flex_dl_slice {
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optional uint32 id = 1;
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optional flex_slice_label label = 2;
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// should be between 0 and 100
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optional uint32 percentage = 3;
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// whether this slice should be exempted form interslice sharing
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optional bool isolation = 4;
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// increasing value means increasing prio
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optional uint32 priority = 5;
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// min and max RB to use (in frequency) in the range [0, N_RBG_MAX]
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optional uint32 position_low = 6;
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optional uint32 position_high = 7;
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// maximum MCS to be allowed in this slice
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optional uint32 maxmcs = 8;
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repeated flex_dl_sorting sorting = 9;
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optional flex_dl_accounting_policy accounting = 10;
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optional string scheduler_name = 11;
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}
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message flex_ul_slice {
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optional uint32 id = 1;
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optional flex_slice_label label = 2;
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// should be between 0 and 100
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optional uint32 percentage = 3;
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// whether this slice should be exempted form interslice sharing
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optional bool isolation = 4;
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// increasing value means increasing prio
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optional uint32 priority = 5;
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// RB start to use (in frequency) in the range [0, N_RB_MAX]
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optional uint32 first_rb = 6;
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// TODO RB number
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//optional uint32 length_rb = 7;
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// maximum MCS to be allowed in this slice
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optional uint32 maxmcs = 8;
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repeated flex_ul_sorting sorting = 9;
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optional flex_ul_accounting_policy accounting = 10;
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optional string scheduler_name = 11;
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}
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//
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// UE config related structures and enums
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//
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@@ -177,4 +258,4 @@ enum flex_ue_state_change_type {
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FLUESC_ACTIVATED = 1;
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FLUESC_DEACTIVATED = 2;
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FLUESC_MOVED = 3;
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}
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}
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@@ -43,6 +43,19 @@ message flex_cell_config {
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optional uint32 eutra_band= 37; // operating band
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optional int32 dl_pdsch_power = 38; // operating downlink power
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optional int32 ul_pusch_power = 39; // operating uplink power
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// whether remaining RBs after first intra-slice allocation will
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// be allocated to UEs of the same slice
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optional bool intraslice_share_active = 40;
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// whether remaining RBs after slice allocation will be allocated
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// to UEs of another slice. Isolated slices will be ignored.
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optional bool interslice_share_active = 41;
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optional flex_slice_config slice_config = 42;
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}
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message flex_slice_config {
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repeated flex_dl_slice dl = 1;
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repeated flex_ul_slice ul = 2;
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}
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message flex_ue_config {
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@@ -82,6 +95,8 @@ message flex_ue_config {
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repeated flex_scell_config scell_config = 28; // Secondary cells configuration
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optional uint32 scell_deactivation_timer = 29;// Deactivation timer for secondary cell
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optional uint64 imsi = 30;
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optional uint32 dl_slice_id = 31;
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optional uint32 ul_slice_id = 32;
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}
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message flex_lc_ue_config {
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