fix dlsim compilation
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@@ -314,15 +314,6 @@ void nr_dlsim_preprocessor(module_id_t module_id,
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AssertFatal(CCEIndex>=0, "%4d.%2d could not find CCE for DL DCI UE %d/RNTI %04x\n", frame, slot, 0, UE_info->rnti);
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sched_ctrl->cce_index = CCEIndex;
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NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
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nr_set_pdsch_semi_static(current_BWP,
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scc,
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/* tda = */ 0,
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g_nrOfLayers,
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sched_ctrl,
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ps);
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NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch;
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sched_pdsch->rbStart = g_rbStart;
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sched_pdsch->rbSize = g_rbSize;
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@@ -332,16 +323,27 @@ void nr_dlsim_preprocessor(module_id_t module_id,
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* configuration */
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current_BWP->mcsTableIdx = g_mcsTableIdx;
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sched_pdsch->time_domain_allocation = get_dl_tda(RC.nrmac[module_id], scc, slot);
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AssertFatal(sched_pdsch->time_domain_allocation>=0,"Unable to find PDSCH time domain allocation in list\n");
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NR_pdsch_tda_info_t *tda_info = &sched_pdsch->tda_info;
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nr_get_pdsch_tda_info(current_BWP, sched_pdsch->time_domain_allocation, tda_info);
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set_dl_dmrs_params(&sched_pdsch->dmrs_parms,
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scc,
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current_BWP,
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tda_info,
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sched_pdsch->nrOfLayers);
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sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, current_BWP->mcsTableIdx);
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sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, current_BWP->mcsTableIdx);
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sched_pdsch->tb_size = nr_compute_tbs(sched_pdsch->Qm,
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sched_pdsch->R,
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sched_pdsch->rbSize,
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ps->nrOfSymbols,
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ps->N_PRB_DMRS * ps->N_DMRS_SLOT,
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tda_info->nrOfSymbols,
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sched_pdsch->dmrs_parms.N_PRB_DMRS * sched_pdsch->dmrs_parms.N_DMRS_SLOT,
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0 /* N_PRB_oh, 0 for initialBWP */,
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0 /* tb_scaling */,
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ps->nrOfLayers) >> 3;
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sched_pdsch->nrOfLayers) >> 3;
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/* the simulator assumes the HARQ PID is equal to the slot number */
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sched_pdsch->dl_harq_pid = slot;
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