Avoid use of FAPI message buffers in msgDataTx
Note: after this commit, monolithic works but nFAPI operation is broken and fixed in the next commit, to keep the changes small(er). All simulators work. This commit removes the use of msgDataTx's intermediate buffers for FAPI messages and the call of the "Schedule response". The latter incurs an additional copy of FAPI messages for the TX chain (for the RX chain, it is and will remain there) which we can avoid. Instead, it uses an NR_Sched_Rsp_t-typed variable sched_response to store the results of the scheduler when called from tx_func(). Thus, the scheduler remains unchanged (it gets a pointer to where to put FAPI messages), but we don't call nr_schedule_response() to then copy FAPI messages into the L1, but have them in a local variable sched_response. sched_response on on the data segment, as it is big and would overflow the stack; at the same time, this is ok because only one tx_func() runs at a time. Since we don't use allocate_sched_response() anymore, we don't need deref_sched_response(). clear_slot_beamid() is moved to tx_func(), as it was called in nr_schedule_response(). Since the "intermediate" NR_gNB_DLSCH_t structure groups both the DL_tti_pdsch and TX_data.req structures, a pointer has been created to point to pdsch_pdu. This affects a number of simulators, as they have to put some messages on the stack: - nr_dlschsim: put the corresponding variable on the stack - nr_pbchsim: a new array for the SSB PDUs has been introduced Further, these changes are now necessary: - nr_dlsim: there were variables "rel15" and "pdsch_pdu_rel15" that point to the same PDSCH PDU. At least "rel15" would not exist, as the corresponding pointer is now populated in phy_procedures_gNB_TX(), and we therefore refer to the single PDSCH PDU variable with "pdsch_pdu_rel15", but at the place where "rel15" used to be initialized. - nr_ulsim: use nr_save_ul_tti_req() to load PDUs into the RX chain instead of nr_schedule_response(), which does not exist anymore.
This commit is contained in:
+17
-14
@@ -82,8 +82,6 @@ static void tx_func(processingData_L1tx_t *info)
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int slot_rx = info->slot_rx;
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LOG_D(NR_PHY, "%d.%d running tx_func\n", frame_tx, slot_tx);
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PHY_VARS_gNB *gNB = info->gNB;
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module_id_t module_id = gNB->Mod_id;
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uint8_t CC_id = gNB->CC_id;
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NR_IF_Module_t *ifi = gNB->if_inst;
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nfapi_nr_config_request_scf_t *cfg = &gNB->gNB_config;
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@@ -94,15 +92,22 @@ static void tx_func(processingData_L1tx_t *info)
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reset_active_ulsch(gNB, frame_rx);
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}
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clear_slot_beamid(gNB, slot_tx);
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nfapi_nr_slot_indication_scf_t ind = {.sfn = frame_tx, .slot = slot_tx};
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start_meas(&gNB->slot_indication_stats);
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ifi->NR_slot_indication(module_id, CC_id, frame_tx, slot_tx);
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// this variable is very big (multiple MB), so we put it into static storage
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// to not overflow the stack while still having it in local (function) scope
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// also, tx_func() is only executed by one thread, serially
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static NR_Sched_Rsp_t sched_response;
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ifi->NR_slot_indication(&ind, &sched_response);
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stop_meas(&gNB->slot_indication_stats);
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gNB->msgDataTx->timestamp_tx = info->timestamp_tx;
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info = gNB->msgDataTx;
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info->gNB = gNB;
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// At this point, MAC scheduler just ran, including scheduling
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// PRACH/PUCCH/PUSCH, so trigger RX chain processing
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nr_save_ul_tti_req(gNB, &sched_response.UL_tti_req);
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LOG_D(NR_PHY, "Trigger RX for %d.%d\n", frame_rx, slot_rx);
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notifiedFIFO_elt_t *res = newNotifiedFIFO_elt(sizeof(processingData_L1_t), 0, &gNB->resp_L1, NULL);
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processingData_L1_t *syncMsg = NotifiedFifoData(res);
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@@ -119,7 +124,13 @@ static void tx_func(processingData_L1tx_t *info)
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if (tx_slot_type == NR_DOWNLINK_SLOT || tx_slot_type == NR_MIXED_SLOT || get_softmodem_params()->continuous_tx || IS_SOFTMODEM_RFSIM
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|| cfg->analog_beamforming_ve.analog_beam_list) {
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start_meas(&info->gNB->phy_proc_tx);
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phy_procedures_gNB_TX(info, frame_tx, slot_tx, 1);
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phy_procedures_gNB_TX(info->gNB,
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&sched_response.DL_req,
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&sched_response.TX_req,
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&sched_response.UL_dci_req,
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frame_tx,
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slot_tx,
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1);
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PHY_VARS_gNB *gNB = info->gNB;
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processingData_RU_t syncMsgRU;
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@@ -131,14 +142,6 @@ static void tx_func(processingData_L1tx_t *info)
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ru_tx_func((void *)&syncMsgRU);
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stop_meas(&info->gNB->phy_proc_tx);
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}
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if (NFAPI_MODE == NFAPI_MONOLITHIC) {
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/* this thread is done with the sched_info, decrease the reference counter.
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* This only applies for monolithic; in the PNF, the memory is allocated in
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* a ring buffer that should never be overwritten (one frame duration). */
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LOG_D(NR_PHY, "Calling deref_sched_response for id %d (tx_func) in %d.%d\n", info->sched_response_id, frame_tx, slot_tx);
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deref_sched_response(info->sched_response_id);
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}
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}
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void *L1_rx_thread(void *arg)
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@@ -555,7 +555,7 @@ static int do_one_dlsch(unsigned char *input_ptr, PHY_VARS_gNB *gNB, NR_gNB_DLSC
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time_stats_t *dlsch_scrambling_stats = &gNB->dlsch_scrambling_stats;
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time_stats_t *dlsch_modulation_stats = &gNB->dlsch_modulation_stats;
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const nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &dlsch->pdsch_pdu.pdsch_pdu_rel15;
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const nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &dlsch->pdsch_pdu->pdsch_pdu_rel15;
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const int layerSz = frame_parms->N_RB_DL * NR_SYMBOLS_PER_SLOT * NR_NB_SC_PER_RB;
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const int symbol_sz=frame_parms->ofdm_symbol_size;
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const int dmrs_Type = rel15->dmrsConfigType;
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@@ -789,7 +789,7 @@ void nr_generate_pdsch(PHY_VARS_gNB *gNB, int n_dlsch, NR_gNB_DLSCH_t *dlsch_arr
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for (int i = 0; i < n_dlsch; i++) {
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NR_gNB_DLSCH_t *dlsch = &dlsch_array[i];
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const nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &dlsch->pdsch_pdu.pdsch_pdu_rel15;
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const nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &dlsch->pdsch_pdu->pdsch_pdu_rel15;
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LOG_D(PHY,
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"pdsch: BWPStart %d, BWPSize %d, rbStart %d, rbsize %d\n",
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@@ -138,7 +138,7 @@ int nr_dlsch_encoding(PHY_VARS_gNB *gNB,
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NR_gNB_DLSCH_t *dlsch = &dlsch_array[i];
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unsigned int crc = 1;
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const nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &dlsch->pdsch_pdu.pdsch_pdu_rel15;
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const nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &dlsch->pdsch_pdu->pdsch_pdu_rel15;
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uint32_t A = rel15->TBSize[0] << 3;
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unsigned char *a = dlsch->pdu;
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if (rel15->rnti != SI_RNTI) {
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@@ -224,7 +224,7 @@ int nr_dlsch_encoding(PHY_VARS_gNB *gNB,
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for (int i = 0; i < n_dlsch; i++) {
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NR_gNB_DLSCH_t *dlsch = &dlsch_array[i];
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const nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &dlsch->pdsch_pdu.pdsch_pdu_rel15;
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const nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &dlsch->pdsch_pdu->pdsch_pdu_rel15;
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nrLDPC_TB_encoding_parameters_t *TB_parameters = &TBs[i];
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@@ -54,7 +54,7 @@ void nr_fill_dlsch_tx_req(processingData_L1tx_t *msgTx, int idx, uint8_t *sdu)
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/* not sure if FAPI could transmit DL_TTI_req and TX_req in different orders.
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* for the moment, assume they are in the same order (and check!) */
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NR_gNB_DLSCH_t *dlsch = &msgTx->gNB->dlsch[idx];
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nfapi_nr_dl_tti_pdsch_pdu *pdsch = &dlsch->pdsch_pdu;
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const nfapi_nr_dl_tti_pdsch_pdu *pdsch = dlsch->pdsch_pdu;
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AssertFatal(pdsch->pdsch_pdu_rel15.pduIndex == idx, "PDSCH PDU index %d does not match %d\n", pdsch->pdsch_pdu_rel15.pduIndex, idx);
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dlsch->pdu = sdu;
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}
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@@ -98,7 +98,7 @@ typedef struct {
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typedef struct {
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/// Nfapi DLSCH PDU
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nfapi_nr_dl_tti_pdsch_pdu pdsch_pdu;
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const nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu;
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/// pointer to pdu from MAC interface (this is "a" in 36.212)
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uint8_t *pdu;
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/// Pointer to the payload
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@@ -243,12 +243,14 @@ static void nr_generate_csi_rs_gNB(PHY_VARS_gNB *gNB,
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gNB->common_vars.txdataF[beam_nb]);
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}
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void phy_procedures_gNB_TX(processingData_L1tx_t *msgTx,
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void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB,
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const nfapi_nr_dl_tti_request_t *DL_req,
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const nfapi_nr_tx_data_request_t *TX_req,
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const nfapi_nr_ul_dci_request_t *UL_dci_req,
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int frame,
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int slot,
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int do_meas)
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{
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PHY_VARS_gNB *gNB = msgTx->gNB;
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NR_DL_FRAME_PARMS *fp = &gNB->frame_parms;
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nfapi_nr_config_request_scf_t *cfg = &gNB->gNB_config;
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int slot_prs = 0;
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@@ -282,44 +284,41 @@ void phy_procedures_gNB_TX(processingData_L1tx_t *msgTx,
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}
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}
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VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_COMMON_TX,1);
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for (int i = 0; i < msgTx->n_ssb_pdu; i++)
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nr_common_signal_procedures(gNB, frame, slot, &msgTx->ssb_pdu[i]);
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msgTx->n_ssb_pdu = 0;
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for (int i = 0; i < UL_dci_req->numPdus; ++i)
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nr_generate_dci(gNB, &UL_dci_req->ul_dci_pdu_list[i].pdcch_pdu.pdcch_pdu_rel15, txdataF_offset, &gNB->frame_parms, slot);
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VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_COMMON_TX,0);
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int num_pdcch_pdus = msgTx->num_ul_pdcch + msgTx->num_dl_pdcch;
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if (num_pdcch_pdus > 0) {
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LOG_D(PHY, "[gNB %d] Frame %d slot %d Calling nr_generate_dci() (number of UL/DL PDCCH PDUs %d/%d)\n",
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gNB->Mod_id, frame, slot, msgTx->num_ul_pdcch, msgTx->num_dl_pdcch);
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VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_PDCCH_TX,1);
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start_meas(&gNB->dci_generation_stats);
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for (int i = 0; i < msgTx->num_dl_pdcch; ++i)
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nr_generate_dci(gNB, &msgTx->pdcch_pdu[i].pdcch_pdu_rel15, txdataF_offset, &gNB->frame_parms, slot);
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for (int i = 0; i < msgTx->num_ul_pdcch; ++i)
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nr_generate_dci(gNB, &msgTx->ul_pdcch_pdu[i].pdcch_pdu_rel15, txdataF_offset, &gNB->frame_parms, slot);
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stop_meas(&gNB->dci_generation_stats);
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VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_gNB_PDCCH_TX,0);
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int num_pdsch = 0;
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for (int i = 0; i < DL_req->dl_tti_request_body.nPDUs; ++i) {
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const nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdu = &DL_req->dl_tti_request_body.dl_tti_pdu_list[i];
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switch (dl_tti_pdu->PDUType) {
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case NFAPI_NR_DL_TTI_SSB_PDU_TYPE:
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nr_common_signal_procedures(gNB, frame, slot, &dl_tti_pdu->ssb_pdu);
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break;
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case NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE:
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nr_generate_dci(gNB, &dl_tti_pdu->pdcch_pdu.pdcch_pdu_rel15, txdataF_offset, &gNB->frame_parms, slot);
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break;
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case NFAPI_NR_DL_TTI_CSI_RS_PDU_TYPE:
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nr_generate_csi_rs_gNB(gNB, slot, cfg, &dl_tti_pdu->csi_rs_pdu);
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break;
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case NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE: {
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int tx_data_idx = dl_tti_pdu->pdsch_pdu.pdsch_pdu_rel15.pduIndex;
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DevAssert(tx_data_idx < TX_req->Number_of_PDUs);
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// reuse dlsch variables, as there are multiple very large memory
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// buffers
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gNB->dlsch[num_pdsch].pdsch_pdu = &dl_tti_pdu->pdsch_pdu;
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gNB->dlsch[num_pdsch].pdu = (uint8_t *)TX_req->pdu_list[tx_data_idx].TLVs[0].value.direct;
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DevAssert(num_pdsch < gNB->max_nb_pdsch);
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num_pdsch++;
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} break;
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}
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}
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msgTx->num_dl_pdcch = 0;
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msgTx->num_ul_pdcch = 0;
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if (msgTx->num_pdsch_slot > 0) {
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if (num_pdsch > 0) {
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VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,1);
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LOG_D(PHY, "PDSCH generation started (%d) in frame %d.%d\n", msgTx->num_pdsch_slot,frame,slot);
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nr_generate_pdsch(gNB, msgTx->num_pdsch_slot, gNB->dlsch, frame, slot);
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LOG_D(PHY, "PDSCH generation started (%d) in frame %d.%d\n", num_pdsch, frame, slot);
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nr_generate_pdsch(gNB, num_pdsch, gNB->dlsch, frame, slot);
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VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,0);
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}
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msgTx->num_pdsch_slot = 0;
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for (int i = 0; i < msgTx->n_csirs_pdu; i++)
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nr_generate_csi_rs_gNB(gNB, slot, cfg, &msgTx->csirs_pdu[i]);
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msgTx->n_csirs_pdu = 0;
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//apply the OFDM symbol rotation here
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start_meas(&gNB->phase_comp_stats);
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@@ -1293,3 +1292,40 @@ int phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, N
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VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PHY_PROCEDURES_gNB_UESPEC_RX,0);
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return pusch_DTX;
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}
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void nr_save_ul_tti_req(PHY_VARS_gNB *gNB, nfapi_nr_ul_tti_request_t *UL_tti_req)
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{
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DevAssert(gNB != NULL);
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DevAssert(UL_tti_req != NULL);
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int frame = UL_tti_req->SFN;
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int slot = UL_tti_req->Slot;
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for (int i = 0; i < UL_tti_req->n_pdus; i++) {
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int type = UL_tti_req->pdus_list[i].pdu_type;
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LOG_D(NR_PHY,
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"frame %d, slot %d got %s for %d.%d\n",
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frame,
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slot,
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txt_nfapi_nr_ul_config_pdu_type[type],
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UL_tti_req->SFN,
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UL_tti_req->Slot);
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switch (type) {
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case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE:
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nr_fill_ulsch(gNB, UL_tti_req->SFN, UL_tti_req->Slot, &UL_tti_req->pdus_list[i].pusch_pdu);
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break;
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case NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE:
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nr_fill_pucch(gNB, UL_tti_req->SFN, UL_tti_req->Slot, &UL_tti_req->pdus_list[i].pucch_pdu);
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break;
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case NFAPI_NR_UL_CONFIG_PRACH_PDU_TYPE: {
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nfapi_nr_prach_pdu_t *prach_pdu = &UL_tti_req->pdus_list[i].prach_pdu;
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prach_item_t *prach = nr_schedule_rx_prach(gNB, UL_tti_req->SFN, UL_tti_req->Slot, prach_pdu);
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if (!prach)
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LOG_W(NR_PHY_RACH, "Error in scheduling rach\n");
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} break;
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case NFAPI_NR_UL_CONFIG_SRS_PDU_TYPE:
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nr_fill_srs(gNB, UL_tti_req->SFN, UL_tti_req->Slot, &UL_tti_req->pdus_list[i].srs_pdu);
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break;
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}
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}
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}
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@@ -33,7 +33,14 @@
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#include "phy_frame_config_nr.h"
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void nr_set_ssb_first_subcarrier(nfapi_nr_config_request_scf_t *cfg, NR_DL_FRAME_PARMS *fp);
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void phy_procedures_gNB_TX(processingData_L1tx_t *msgTx, int frame_tx, int slot_tx, int do_meas);
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void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB,
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const nfapi_nr_dl_tti_request_t *DL_req,
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const nfapi_nr_tx_data_request_t *TX_req,
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const nfapi_nr_ul_dci_request_t *UL_dci_req,
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int frame,
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int slot,
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int do_meas);
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void nr_save_ul_tti_req(PHY_VARS_gNB *gNB, nfapi_nr_ul_tti_request_t *UL_tti_req);
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int phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, NR_UL_IND_t *UL_INFO);
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void L1_nr_prach_procedures(PHY_VARS_gNB *gNB, int frame, int slot, nfapi_nr_rach_indication_t *rach_ind);
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void nr_common_signal_procedures (PHY_VARS_gNB *gNB,int frame,int slot, const nfapi_nr_dl_tti_ssb_pdu *ssb_pdu);
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@@ -439,10 +439,7 @@ int main(int argc, char **argv)
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nr_init_dl_harq_processes(UE->dl_harq_processes, 8, nb_rb);
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unsigned char harq_pid = 0; //dlsch->harq_ids[subframe];
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processingData_L1tx_t msgDataTx = {0};
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msgDataTx.gNB = gNB;
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NR_gNB_DLSCH_t *dlsch = &msgDataTx.gNB->dlsch[0];
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nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &dlsch->pdsch_pdu.pdsch_pdu_rel15;
|
||||
NR_gNB_DLSCH_t *dlsch = &gNB->dlsch[0];
|
||||
//time_stats_t *rm_stats, *te_stats, *i_stats;
|
||||
unsigned int TBS = 8424;
|
||||
uint8_t nb_re_dmrs = 6; // No data in dmrs symbol
|
||||
@@ -459,19 +456,24 @@ int main(int argc, char **argv)
|
||||
TBS = nr_compute_tbs(mod_order,rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, 0, Nl);
|
||||
printf("available bits %u TBS %u mod_order %d\n", available_bits, TBS, mod_order);
|
||||
//dlsch->harq_ids[subframe]= 0;
|
||||
rel15->rbSize = nb_rb;
|
||||
rel15->NrOfSymbols = nb_symb_sch;
|
||||
rel15->qamModOrder[0] = mod_order;
|
||||
rel15->nrOfLayers = Nl;
|
||||
rel15->TBSize[0] = TBS>>3;
|
||||
rel15->targetCodeRate[0] = rate;
|
||||
rel15->NrOfCodewords = 1;
|
||||
rel15->dmrsConfigType = NFAPI_NR_DMRS_TYPE1;
|
||||
rel15->dlDmrsSymbPos = 4;
|
||||
rel15->mcsIndex[0] = Imcs;
|
||||
rel15->numDmrsCdmGrpsNoData = 1;
|
||||
rel15->maintenance_parms_v3.tbSizeLbrmBytes = Tbslbrm;
|
||||
rel15->maintenance_parms_v3.ldpcBaseGraph = get_BG(TBS, rate);
|
||||
nfapi_nr_dl_tti_pdsch_pdu pdsch_pdu = {
|
||||
.pdsch_pdu_rel15 = {
|
||||
.rbSize = nb_rb,
|
||||
.NrOfSymbols = nb_symb_sch,
|
||||
.qamModOrder[0] = mod_order,
|
||||
.nrOfLayers = Nl,
|
||||
.TBSize[0] = TBS >> 3,
|
||||
.targetCodeRate[0] = rate,
|
||||
.NrOfCodewords = 1,
|
||||
.dmrsConfigType = NFAPI_NR_DMRS_TYPE1,
|
||||
.dlDmrsSymbPos = 4,
|
||||
.mcsIndex[0] = Imcs,
|
||||
.numDmrsCdmGrpsNoData = 1,
|
||||
.maintenance_parms_v3.tbSizeLbrmBytes = Tbslbrm,
|
||||
.maintenance_parms_v3.ldpcBaseGraph = get_BG(TBS, rate),
|
||||
},
|
||||
};
|
||||
dlsch->pdsch_pdu = &pdsch_pdu;
|
||||
double modulated_input[16 * 68 * 384]; // [hna] 16 segments, 68*Zc
|
||||
short channel_output_fixed[16 * 68 * 384];
|
||||
//unsigned char *estimated_output;
|
||||
@@ -512,7 +514,7 @@ int main(int argc, char **argv)
|
||||
|
||||
//printf("crc32: [0]->0x%08x\n",crc24c(test_input, 32));
|
||||
// generate signal
|
||||
unsigned char output[rel15->rbSize * NR_SYMBOLS_PER_SLOT * NR_NB_SC_PER_RB * NR_MAX_NB_LAYERS] __attribute__((aligned(64)));
|
||||
unsigned char output[nb_rb * NR_SYMBOLS_PER_SLOT * NR_NB_SC_PER_RB * NR_MAX_NB_LAYERS] __attribute__((aligned(64)));
|
||||
bzero(output, sizeof(output));
|
||||
if (input_fd == NULL) {
|
||||
nr_dlsch_encoding(gNB, 1, dlsch, frame, slot, frame_parms, output, NULL, NULL, NULL, NULL, NULL, NULL, NULL);
|
||||
|
||||
@@ -62,7 +62,6 @@
|
||||
#include "PHY/defs_nr_common.h"
|
||||
#include "PHY/impl_defs_nr.h"
|
||||
#include "PHY/phy_vars_nr_ue.h"
|
||||
#include "SCHED_NR/fapi_nr_l1.h"
|
||||
#include "SCHED_NR/sched_nr.h"
|
||||
#include "SCHED_NR_UE/defs.h"
|
||||
#include "SCHED_NR_UE/fapi_nr_ue_l1.h"
|
||||
@@ -286,7 +285,6 @@ nrUE_params_t *get_nrUE_params(void) {
|
||||
return &nrUE_params;
|
||||
}
|
||||
|
||||
|
||||
void validate_input_pmi(nfapi_nr_config_request_scf_t *gNB_config,
|
||||
nr_pdsch_AntennaPorts_t pdsch_AntennaPorts,
|
||||
int nrOfLayers,
|
||||
@@ -974,12 +972,6 @@ int main(int argc, char **argv)
|
||||
int ret = 1;
|
||||
initNamedTpool(gNBthreads, &gNB->threadPool, true, "gNB-tpool");
|
||||
initNotifiedFIFO(&gNB->L1_tx_out);
|
||||
// we create 2 threads for L1 tx processing
|
||||
processingData_L1tx_t *msgDataTx = malloc(sizeof(processingData_L1tx_t));
|
||||
msgDataTx->slot = slot;
|
||||
msgDataTx->frame = frame;
|
||||
msgDataTx->gNB = gNB;
|
||||
gNB->msgDataTx = msgDataTx;
|
||||
|
||||
// Buffers to store internal memory of slot process
|
||||
int rx_size = (((14 * UE->frame_parms.N_RB_DL * 12 * sizeof(int32_t)) + 15) >> 4) << 4;
|
||||
@@ -1058,8 +1050,13 @@ int main(int argc, char **argv)
|
||||
n_false_positive = 0;
|
||||
if (n_trials== 1) num_rounds = 1;
|
||||
|
||||
NR_gNB_DLSCH_t *gNB_dlsch = &msgDataTx->gNB->dlsch[0];
|
||||
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &gNB_dlsch->pdsch_pdu.pdsch_pdu_rel15;
|
||||
NR_gNB_DLSCH_t *gNB_dlsch = &gNB->dlsch[0];
|
||||
memset(Sched_INFO, 0, sizeof(*Sched_INFO));
|
||||
Sched_INFO->sched_response_id = -1;
|
||||
nfapi_nr_dl_tti_request_body_t *dl_req = &Sched_INFO->DL_req.dl_tti_request_body;
|
||||
// scheduler will place PDSCH second (after PDCCH), verification below
|
||||
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[1];
|
||||
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15;
|
||||
|
||||
for (trial = 0; trial < n_trials && !stop; trial++) {
|
||||
|
||||
@@ -1081,11 +1078,9 @@ int main(int argc, char **argv)
|
||||
UE_harq_process->DLround = round;
|
||||
UE_harq_process->first_rx = 1;
|
||||
|
||||
memset(Sched_INFO, 0, sizeof(*Sched_INFO));
|
||||
Sched_INFO->sched_response_id = -1;
|
||||
|
||||
while (round < num_rounds && !UE_harq_process->decodeResult && !stop) {
|
||||
clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot, &Sched_INFO->DL_req, &Sched_INFO->TX_req, &Sched_INFO->UL_dci_req);
|
||||
reset_sched_response(Sched_INFO, frame, slot, 0, 0);
|
||||
clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot);
|
||||
UE_info->UE_sched_ctrl.harq_processes[harq_pid].ndi = !(trial&1);
|
||||
UE_info->UE_sched_ctrl.harq_processes[harq_pid].round = round;
|
||||
|
||||
@@ -1093,18 +1088,13 @@ int main(int argc, char **argv)
|
||||
NR_SCHED_LOCK(&gNB_mac->sched_lock);
|
||||
nr_schedule_ue_spec(0, frame, slot, &Sched_INFO->DL_req, &Sched_INFO->TX_req);
|
||||
NR_SCHED_UNLOCK(&gNB_mac->sched_lock);
|
||||
Sched_INFO->module_id = 0;
|
||||
Sched_INFO->CC_id = 0;
|
||||
Sched_INFO->frame = frame;
|
||||
Sched_INFO->slot = slot;
|
||||
Sched_INFO->UL_dci_req.numPdus = 0;
|
||||
nr_schedule_response(Sched_INFO);
|
||||
|
||||
/* check that second message is indeed PDSCH */
|
||||
DevAssert(dl_tti_pdsch_pdu->PDUType == NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE);
|
||||
|
||||
/* PTRS values for DLSIM calculations */
|
||||
nfapi_nr_dl_tti_request_body_t *dl_req = &Sched_INFO->DL_req.dl_tti_request_body;
|
||||
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[1];
|
||||
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15;
|
||||
pdu_bit_map = pdsch_pdu_rel15->pduBitmap;
|
||||
// This is already in DL procedures??
|
||||
if(pdu_bit_map & 0x1) {
|
||||
set_ptrs_symb_idx(&dlPtrsSymPos,
|
||||
pdsch_pdu_rel15->NrOfSymbols,
|
||||
@@ -1112,16 +1102,12 @@ int main(int argc, char **argv)
|
||||
1<<pdsch_pdu_rel15->PTRSTimeDensity,
|
||||
pdsch_pdu_rel15->dlDmrsSymbPos);
|
||||
ptrsSymbPerSlot = get_ptrs_symbols_in_slot(dlPtrsSymPos, pdsch_pdu_rel15->StartSymbolIndex, pdsch_pdu_rel15->NrOfSymbols);
|
||||
ptrsRePerSymb = ((rel15->rbSize + rel15->PTRSFreqDensity - 1) / rel15->PTRSFreqDensity);
|
||||
ptrsRePerSymb = ((pdsch_pdu_rel15->rbSize + pdsch_pdu_rel15->PTRSFreqDensity - 1) / pdsch_pdu_rel15->PTRSFreqDensity);
|
||||
LOG_D(PHY,"[DLSIM] PTRS Symbols in a slot: %2u, RE per Symbol: %3u, RE in a slot %4d\n", ptrsSymbPerSlot, ptrsRePerSymb, ptrsSymbPerSlot * ptrsRePerSymb);
|
||||
}
|
||||
|
||||
msgDataTx->ssb_pdu[0].ssb_pdu_rel15.bchPayload = 0x001234;
|
||||
msgDataTx->ssb_pdu[0].ssb_pdu_rel15.SsbBlockIndex = 0;
|
||||
msgDataTx->gNB = gNB;
|
||||
|
||||
start_meas(&gNB->phy_proc_tx);
|
||||
phy_procedures_gNB_TX(msgDataTx,frame,slot,1);
|
||||
phy_procedures_gNB_TX(gNB, &Sched_INFO->DL_req, &Sched_INFO->TX_req, &Sched_INFO->UL_dci_req, frame, slot, 1);
|
||||
stop_meas(&gNB->phy_proc_tx);
|
||||
|
||||
int txdataF_offset = slot * frame_parms->samples_per_slot_wCP;
|
||||
@@ -1196,9 +1182,9 @@ int main(int argc, char **argv)
|
||||
|
||||
double ts = 1.0/(frame_parms->subcarrier_spacing * frame_parms->ofdm_symbol_size);
|
||||
//Compute AWGN variance
|
||||
sigma2_dB = 10 * log10((double)txlev_sum * ((double)UE->frame_parms.ofdm_symbol_size/(12*rel15->rbSize))) - SNR;
|
||||
sigma2_dB = 10 * log10((double)txlev_sum * ((double)UE->frame_parms.ofdm_symbol_size/(12*pdsch_pdu_rel15->rbSize))) - SNR;
|
||||
sigma2 = pow(10, sigma2_dB/10);
|
||||
if (n_trials==1) printf("sigma2 %f (%f dB), txlev_sum %f (factor %f)\n",sigma2,sigma2_dB,10*log10((double)txlev_sum),(double)(double)UE->frame_parms.ofdm_symbol_size/(12*rel15->rbSize));
|
||||
if (n_trials==1) printf("sigma2 %f (%f dB), txlev_sum %f (factor %f)\n",sigma2,sigma2_dB,10*log10((double)txlev_sum),(double)(double)UE->frame_parms.ofdm_symbol_size/(12*pdsch_pdu_rel15->rbSize));
|
||||
|
||||
for (aa = 0; aa < n_rx; aa++) {
|
||||
bzero(r_re[aa], slot_length * sizeof(double));
|
||||
@@ -1240,17 +1226,17 @@ int main(int argc, char **argv)
|
||||
|
||||
int16_t *UE_llr = (int16_t*)UE->phy_sim_pdsch_llr;
|
||||
|
||||
TBS = dlsch0->dlsch_config.TBS;//rel15->TBSize[0];
|
||||
TBS = dlsch0->dlsch_config.TBS;
|
||||
uint16_t length_dmrs = get_num_dmrs(dlsch0->dlsch_config.dlDmrsSymbPos);
|
||||
uint16_t nb_rb = dlsch0->dlsch_config.number_rbs;
|
||||
uint8_t nb_re_dmrs = dlsch0->dlsch_config.dmrsConfigType == NFAPI_NR_DMRS_TYPE1 ? 6*dlsch0->dlsch_config.n_dmrs_cdm_groups : 4*dlsch0->dlsch_config.n_dmrs_cdm_groups;
|
||||
uint8_t mod_order = dlsch0->dlsch_config.qamModOrder;
|
||||
uint8_t nb_symb_sch = dlsch0->dlsch_config.number_symbols;
|
||||
uint32_t unav_res = ptrsSymbPerSlot * ptrsRePerSymb;
|
||||
available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, unav_res, mod_order, rel15->nrOfLayers);
|
||||
available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, unav_res, mod_order, pdsch_pdu_rel15->nrOfLayers);
|
||||
if (pdu_bit_map & 0x1) {
|
||||
if (trial == 0 && round == 0) {
|
||||
printf("[DLSIM][PTRS] Available bits are: %5u, removed PTRS bits are: %5u \n", available_bits, (ptrsSymbPerSlot * ptrsRePerSymb * rel15->nrOfLayers * mod_order));
|
||||
printf("[DLSIM][PTRS] Available bits are: %5u, removed PTRS bits are: %5u \n", available_bits, (ptrsSymbPerSlot * ptrsRePerSymb * pdsch_pdu_rel15->nrOfLayers * mod_order));
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1269,8 +1255,8 @@ int main(int argc, char **argv)
|
||||
} // round
|
||||
|
||||
if (test_input_bit == NULL) {
|
||||
test_input_bit = (unsigned char *)malloc16(8 * rel15->TBSize[0]);
|
||||
estimated_output_bit = (unsigned char *)malloc16(8 * rel15->TBSize[0]);
|
||||
test_input_bit = (unsigned char *)malloc16(8 * pdsch_pdu_rel15->TBSize[0]);
|
||||
estimated_output_bit = (unsigned char *)malloc16(8 * pdsch_pdu_rel15->TBSize[0]);
|
||||
}
|
||||
for (i = 0; i < TBS; i++) {
|
||||
|
||||
@@ -1319,7 +1305,7 @@ int main(int argc, char **argv)
|
||||
printf("), Channel BER (%e", berStats[0]);
|
||||
for (int r = 1; r < num_rounds; r++)
|
||||
printf(",%e", berStats[r]);
|
||||
printf(") Avg round %.2f, Eff Rate %.4f bits/slot, Eff Throughput %.2f, TBS %u bits/slot\n", roundStats, effRate, effRate / (8 * rel15->TBSize[0]) * 100, 8 * rel15->TBSize[0]);
|
||||
printf(") Avg round %.2f, Eff Rate %.4f bits/slot, Eff Throughput %.2f, TBS %u bits/slot\n", roundStats, effRate, effRate / (8 * pdsch_pdu_rel15->TBSize[0]) * 100, 8 * pdsch_pdu_rel15->TBSize[0]);
|
||||
printf("*****************************************\n");
|
||||
printf("\n");
|
||||
// writing to csv file
|
||||
@@ -1327,7 +1313,7 @@ int main(int argc, char **argv)
|
||||
fprintf(csv_file,"%f,%d/%d,",SNR,n_false_positive,n_trials);
|
||||
for (int r = 0; r < num_rounds; r++)
|
||||
fprintf(csv_file,"%d/%d,%u/%u,%f,%e,",n_errors[r], round_trials[r], errors_scrambling[r], available_bits * round_trials[r],blerStats[r],berStats[r]);
|
||||
fprintf(csv_file,"%.2f,%.4f,%.2f,%u\n", roundStats, effRate, effRate / (8 * rel15->TBSize[0]) * 100, 8 * rel15->TBSize[0]);
|
||||
fprintf(csv_file,"%.2f,%.4f,%.2f,%u\n", roundStats, effRate, effRate / (8 * pdsch_pdu_rel15->TBSize[0]) * 100, 8 * pdsch_pdu_rel15->TBSize[0]);
|
||||
}
|
||||
if (print_perf==1) {
|
||||
printf("\ngNB TX function statistics (per %d us slot, NPRB %d, mcs %d, C %d, block %d)\n",
|
||||
@@ -1335,7 +1321,7 @@ int main(int argc, char **argv)
|
||||
g_rbSize,
|
||||
g_mcsIndex,
|
||||
UE->dl_harq_processes[0][slot].C,
|
||||
8 * rel15->TBSize[0]);
|
||||
8 * pdsch_pdu_rel15->TBSize[0]);
|
||||
printDistribution(&gNB->phy_proc_tx,table_tx,"PHY proc tx");
|
||||
printStatIndent2(&gNB->dci_generation_stats, "DCI encoding time");
|
||||
printStatIndent2(&gNB->dlsch_encoding_stats,"DLSCH encoding time");
|
||||
@@ -1377,8 +1363,8 @@ int main(int argc, char **argv)
|
||||
const uint32_t numReSym = (g_rbSize * 12 + 15) & (~15);
|
||||
for (int l = 0; l < g_nrOfLayers; l++) {
|
||||
for (int r = 0; r < n_rx; r++) {
|
||||
const int s = rel15->StartSymbolIndex;
|
||||
const int n = rel15->NrOfSymbols;
|
||||
const int s = pdsch_pdu_rel15->StartSymbolIndex;
|
||||
const int n = pdsch_pdu_rel15->NrOfSymbols;
|
||||
for (int i = s; i < s + n; i++) {
|
||||
const uint32_t dmrsBitMap = phy_data.dlsch[0].dlsch_config.dlDmrsSymbPos;
|
||||
const uint32_t dmrsCfg = phy_data.dlsch[0].dlsch_config.dmrsConfigType;
|
||||
@@ -1414,7 +1400,7 @@ int main(int argc, char **argv)
|
||||
break;
|
||||
}
|
||||
|
||||
if (effRate >= (eff_tp_check * 8 * rel15->TBSize[0])) {
|
||||
if (effRate >= (eff_tp_check * 8 * pdsch_pdu_rel15->TBSize[0])) {
|
||||
printf("PDSCH test OK\n");
|
||||
ret = 0;
|
||||
break;
|
||||
|
||||
@@ -519,10 +519,10 @@ int main(int argc, char **argv)
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
processingData_L1tx_t msgDataTx;
|
||||
// generate signal
|
||||
const uint32_t rxdataF_sz = UE->frame_parms.samples_per_slot_wCP;
|
||||
__attribute__ ((aligned(32))) c16_t rxdataF[UE->frame_parms.nb_antennas_rx][rxdataF_sz];
|
||||
nfapi_nr_dl_tti_ssb_pdu ssb_pdu[64] = {0};
|
||||
if (input_fd==NULL) {
|
||||
|
||||
for (i=0; i<frame_parms->Lmax; i++) {
|
||||
@@ -530,10 +530,10 @@ int main(int argc, char **argv)
|
||||
|
||||
const int sc_offset = frame_parms->freq_range == FR1 ? ssb_subcarrier_offset<<mu : ssb_subcarrier_offset;
|
||||
const int prb_offset = frame_parms->freq_range == FR1 ? gNB->gNB_config.ssb_table.ssb_offset_point_a.value<<mu : gNB->gNB_config.ssb_table.ssb_offset_point_a.value << (mu - 2);
|
||||
msgDataTx.ssb_pdu[i].ssb_pdu_rel15.bchPayload = 0x55dd33;
|
||||
msgDataTx.ssb_pdu[i].ssb_pdu_rel15.SsbBlockIndex = i;
|
||||
msgDataTx.ssb_pdu[i].ssb_pdu_rel15.SsbSubcarrierOffset = sc_offset;
|
||||
msgDataTx.ssb_pdu[i].ssb_pdu_rel15.ssbOffsetPointA = prb_offset;
|
||||
ssb_pdu[i].ssb_pdu_rel15.bchPayload = 0x55dd33;
|
||||
ssb_pdu[i].ssb_pdu_rel15.SsbBlockIndex = i;
|
||||
ssb_pdu[i].ssb_pdu_rel15.SsbSubcarrierOffset = sc_offset;
|
||||
ssb_pdu[i].ssb_pdu_rel15.ssbOffsetPointA = prb_offset;
|
||||
|
||||
start_symbol = nr_get_ssb_start_symbol(frame_parms,i);
|
||||
int slot = start_symbol/14;
|
||||
@@ -541,7 +541,7 @@ int main(int argc, char **argv)
|
||||
for (aa=0; aa<gNB->frame_parms.nb_antennas_tx; aa++)
|
||||
memset(gNB->common_vars.txdataF[0][aa], 0, frame_parms->samples_per_slot_wCP * sizeof(int32_t));
|
||||
|
||||
nr_common_signal_procedures (gNB,frame,slot, &msgDataTx.ssb_pdu[i]);
|
||||
nr_common_signal_procedures (gNB,frame,slot, &ssb_pdu[i]);
|
||||
|
||||
int samp = frame_parms->get_samples_slot_timestamp(slot, frame_parms, 0);
|
||||
for (aa=0; aa<gNB->frame_parms.nb_antennas_tx; aa++) {
|
||||
@@ -744,7 +744,7 @@ int main(int argc, char **argv)
|
||||
gNB->gNB_config.ssb_table.ssb_subcarrier_offset.value,
|
||||
frame_parms->Lmax);
|
||||
int payload_ret = (result.xtra_byte == xtra_byte);
|
||||
nfapi_nr_dl_tti_ssb_pdu_rel15_t *pdu = &msgDataTx.ssb_pdu[ssb_index].ssb_pdu_rel15;
|
||||
nfapi_nr_dl_tti_ssb_pdu_rel15_t *pdu = &ssb_pdu[ssb_index].ssb_pdu_rel15;
|
||||
for (int i = 0; i < 3; i++)
|
||||
payload_ret += (result.decoded_output[i] == ((pdu->bchPayload >> (8 * i)) & 0xff));
|
||||
// printf("ret %d\n", payload_ret);
|
||||
|
||||
@@ -60,7 +60,6 @@
|
||||
#include "PHY/defs_nr_common.h"
|
||||
#include "PHY/impl_defs_nr.h"
|
||||
#include "PHY/phy_vars_nr_ue.h"
|
||||
#include "SCHED_NR/fapi_nr_l1.h"
|
||||
#include "SCHED_NR/sched_nr.h"
|
||||
#include "SCHED_NR_UE/defs.h"
|
||||
#include "SCHED_NR_UE/fapi_nr_ue_l1.h"
|
||||
@@ -727,11 +726,6 @@ int main(int argc, char *argv[])
|
||||
else
|
||||
initNamedTpool(gNBthreads, &gNB->threadPool, true, "gNB-tpool");
|
||||
|
||||
processingData_L1tx_t *msgDataTx = malloc(sizeof(processingData_L1tx_t));
|
||||
msgDataTx->slot = -1;
|
||||
gNB->msgDataTx = msgDataTx;
|
||||
//gNB_config = &gNB->gNB_config;
|
||||
|
||||
NR_UL_IND_t UL_INFO = {0};
|
||||
UL_INFO.crc_ind.crc_list = UL_INFO.crc_pdu_list;
|
||||
UL_INFO.rx_ind.pdu_list = UL_INFO.rx_pdu_list;
|
||||
@@ -1284,6 +1278,9 @@ int main(int argc, char *argv[])
|
||||
srs_pdu->beamforming.prg_size = 1;
|
||||
}
|
||||
|
||||
/* load FAPI into RX of L1 */
|
||||
nr_save_ul_tti_req(gNB, &Sched_INFO->UL_tti_req);
|
||||
|
||||
/// UE UL PDUs
|
||||
|
||||
UE->ul_harq_processes[harq_pid].round = round;
|
||||
@@ -1291,9 +1288,6 @@ int main(int argc, char *argv[])
|
||||
UE_proc.frame_tx = frame;
|
||||
UE_proc.gNB_id = 0;
|
||||
|
||||
// prepare ULSCH/PUSCH reception
|
||||
nr_schedule_response(Sched_INFO);
|
||||
|
||||
// --------- setting parameters for UE --------
|
||||
nr_scheduled_response_t scheduled_response = {.ul_config = &ul_config, .phy_data = (void *)&phy_data};
|
||||
|
||||
|
||||
@@ -59,13 +59,7 @@ uint8_t nr_get_rv(int rel_round)
|
||||
return nr_rv_round_map[rel_round];
|
||||
}
|
||||
|
||||
void clear_nr_nfapi_information(gNB_MAC_INST *gNB,
|
||||
int CC_idP,
|
||||
frame_t frameP,
|
||||
slot_t slotP,
|
||||
nfapi_nr_dl_tti_request_t *DL_req,
|
||||
nfapi_nr_tx_data_request_t *TX_req,
|
||||
nfapi_nr_ul_dci_request_t *UL_dci_req)
|
||||
void clear_nr_nfapi_information(gNB_MAC_INST *gNB, int CC_idP, frame_t frameP, slot_t slotP)
|
||||
{
|
||||
/* called below and in simulators, so we assume a lock but don't require it */
|
||||
const int num_slots = gNB->frame_structure.numb_slots_frame;
|
||||
@@ -75,16 +69,8 @@ void clear_nr_nfapi_information(gNB_MAC_INST *gNB,
|
||||
|
||||
gNB->pdu_index[CC_idP] = 0;
|
||||
|
||||
DL_req[CC_idP].SFN = frameP;
|
||||
DL_req[CC_idP].Slot = slotP;
|
||||
DL_req[CC_idP].dl_tti_request_body.nPDUs = 0;
|
||||
DL_req[CC_idP].dl_tti_request_body.nGroup = 0;
|
||||
memset(pdcch, 0, sizeof(*pdcch) * MAX_NUM_CORESET);
|
||||
|
||||
UL_dci_req[CC_idP].SFN = frameP;
|
||||
UL_dci_req[CC_idP].Slot = slotP;
|
||||
UL_dci_req[CC_idP].numPdus = 0;
|
||||
|
||||
/* advance last round's future UL_tti_req to be ahead of current frame/slot */
|
||||
const int size = gNB->UL_tti_req_ahead_size;
|
||||
const int prev_slot = frameP * num_slots + slotP + size - 1;
|
||||
@@ -100,8 +86,6 @@ void clear_nr_nfapi_information(gNB_MAC_INST *gNB,
|
||||
future_ul_tti_req->n_ulsch = 0;
|
||||
future_ul_tti_req->n_ulcch = 0;
|
||||
future_ul_tti_req->n_group = 0;
|
||||
|
||||
TX_req[CC_idP].Number_of_PDUs = 0;
|
||||
}
|
||||
|
||||
static void clear_beam_information(NR_beam_info_t *beam_info, int frame, int slot, int slots_per_frame)
|
||||
@@ -191,7 +175,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frame, slot_t slo
|
||||
uint16_t *vrb_map_UL = cc[CC_id].vrb_map_UL[i];
|
||||
memcpy(&vrb_map_UL[prev_slot % size * MAX_BWP_SIZE], &gNB->ulprbbl, sizeof(uint16_t) * MAX_BWP_SIZE);
|
||||
}
|
||||
clear_nr_nfapi_information(gNB, CC_id, frame, slot, &sched_info->DL_req, &sched_info->TX_req, &sched_info->UL_dci_req);
|
||||
clear_nr_nfapi_information(gNB, CC_id, frame, slot);
|
||||
}
|
||||
|
||||
bool wait_prach_completed = gNB->num_scheduled_prach_rx >= NUM_PRACH_RX_FOR_NOISE_ESTIMATE;
|
||||
|
||||
@@ -68,13 +68,7 @@ int nr_mac_get_reconfig_delay_slots(NR_SubcarrierSpacing_t scs);
|
||||
int nr_mac_interrupt_ue_transmission(gNB_MAC_INST *mac, NR_UE_info_t *UE, int slots);
|
||||
int nr_transmission_action_indicator_stop(gNB_MAC_INST *mac, NR_UE_info_t *UE_info);
|
||||
|
||||
void clear_nr_nfapi_information(gNB_MAC_INST *gNB,
|
||||
int CC_idP,
|
||||
frame_t frameP,
|
||||
slot_t slotP,
|
||||
nfapi_nr_dl_tti_request_t *DL_req,
|
||||
nfapi_nr_tx_data_request_t *TX_req,
|
||||
nfapi_nr_ul_dci_request_t *UL_dci_req);
|
||||
void clear_nr_nfapi_information(gNB_MAC_INST *gNB, int CC_idP, frame_t frameP, slot_t slotP);
|
||||
|
||||
void nr_mac_update_timers(module_id_t module_id, frame_t frame, slot_t slot);
|
||||
|
||||
|
||||
@@ -380,48 +380,22 @@ static void match_crc_rx_pdu(nfapi_nr_rx_data_indication_t *rx_ind, nfapi_nr_crc
|
||||
}
|
||||
|
||||
extern void handle_nr_slot_ind(uint16_t sfn, uint16_t slot);
|
||||
static void pnf_send_slot_ind(module_id_t module_id, int CC_id, int frame, int slot)
|
||||
static void pnf_send_slot_ind(const nfapi_nr_slot_indication_scf_t *ind, NR_Sched_Rsp_t *rsp)
|
||||
{
|
||||
(void)module_id;
|
||||
(void)CC_id;
|
||||
handle_nr_slot_ind(frame, slot);
|
||||
module_id_t module_id = 0;
|
||||
int CC_id = 0;
|
||||
reset_sched_response(rsp, ind->sfn, ind->slot, module_id, CC_id);
|
||||
handle_nr_slot_ind(ind->sfn, ind->slot);
|
||||
|
||||
// TODO copy messages from FAPI buffers
|
||||
}
|
||||
|
||||
static void run_scheduler_monolithic(module_id_t module_id, int CC_id, int frame, int slot)
|
||||
static void run_scheduler_monolithic(const nfapi_nr_slot_indication_scf_t *ind, NR_Sched_Rsp_t *rsp)
|
||||
{
|
||||
NR_IF_Module_t *ifi = nr_if_inst[module_id];
|
||||
|
||||
LOG_D(NR_MAC, "Calling scheduler for %d.%d\n", frame, slot);
|
||||
NR_Sched_Rsp_t *sched_info = allocate_sched_response();
|
||||
|
||||
// clear UL DCI prior to handling ULSCH
|
||||
sched_info->UL_dci_req.numPdus = 0;
|
||||
gNB_dlsch_ulsch_scheduler(module_id, frame, slot, sched_info);
|
||||
ifi->CC_mask = 0;
|
||||
sched_info->module_id = module_id;
|
||||
sched_info->CC_id = CC_id;
|
||||
sched_info->frame = frame;
|
||||
sched_info->slot = slot;
|
||||
/*
|
||||
sched_info->DL_req = &mac->DL_req[CC_id];
|
||||
sched_info->UL_dci_req = &mac->UL_dci_req[CC_id];
|
||||
|
||||
sched_info->UL_tti_req = mac->UL_tti_req[CC_id];
|
||||
|
||||
sched_info->TX_req = &mac->TX_req[CC_id];
|
||||
*/
|
||||
#ifdef DUMP_FAPI
|
||||
dump_dl(sched_info);
|
||||
#endif
|
||||
|
||||
AssertFatal(ifi->NR_Schedule_response != NULL, "nr_schedule_response is null (mod %d, cc %d)\n", module_id, CC_id);
|
||||
ifi->NR_Schedule_response(sched_info);
|
||||
|
||||
LOG_D(NR_PHY,
|
||||
"NR_Schedule_response: SFN SLOT:%d %d dl_pdus:%d\n",
|
||||
sched_info->frame,
|
||||
sched_info->slot,
|
||||
sched_info->DL_req.dl_tti_request_body.nPDUs);
|
||||
module_id_t module_id = 0;
|
||||
int CC_id = 0;
|
||||
reset_sched_response(rsp, ind->sfn, ind->slot, module_id, CC_id);
|
||||
gNB_dlsch_ulsch_scheduler(rsp->module_id, ind->sfn, ind->slot, rsp);
|
||||
}
|
||||
|
||||
void NR_UL_indication(NR_UL_IND_t *UL_info) {
|
||||
@@ -515,3 +489,33 @@ NR_IF_Module_t *NR_IF_Module_init(int Mod_id) {
|
||||
|
||||
return nr_if_inst[Mod_id];
|
||||
}
|
||||
|
||||
void reset_sched_response(NR_Sched_Rsp_t *sched_response, int frame, int slot, int module_id, int CC_id)
|
||||
{
|
||||
sched_response->module_id = module_id;
|
||||
sched_response->CC_id = CC_id;
|
||||
sched_response->frame = frame;
|
||||
sched_response->slot = slot;
|
||||
|
||||
|
||||
nfapi_nr_dl_tti_request_t *DL_req = &sched_response->DL_req;
|
||||
DL_req->SFN = frame;
|
||||
DL_req->Slot = slot;
|
||||
DL_req->dl_tti_request_body.nPDUs = 0;
|
||||
DL_req->dl_tti_request_body.nGroup = 0;
|
||||
|
||||
nfapi_nr_ul_dci_request_t *UL_dci_req = &sched_response->UL_dci_req;
|
||||
UL_dci_req->SFN = frame;
|
||||
UL_dci_req->Slot = slot;
|
||||
UL_dci_req->numPdus = 0;
|
||||
|
||||
nfapi_nr_ul_tti_request_t *UL_tti_req = &sched_response->UL_tti_req;
|
||||
UL_tti_req->SFN = frame;
|
||||
UL_tti_req->Slot = slot;
|
||||
UL_tti_req->n_pdus = 0;
|
||||
|
||||
nfapi_nr_tx_data_request_t *TX_req = &sched_response->TX_req;
|
||||
TX_req->SFN = frame;
|
||||
TX_req->Slot = slot;
|
||||
TX_req->Number_of_PDUs = 0;
|
||||
}
|
||||
|
||||
@@ -111,6 +111,7 @@ typedef struct {
|
||||
/// Pointers to DL SDUs
|
||||
nfapi_nr_tx_data_request_t TX_req;
|
||||
} NR_Sched_Rsp_t;
|
||||
void reset_sched_response(NR_Sched_Rsp_t *sched_response, int frame, int slot, int module_id, int CC_id);
|
||||
|
||||
typedef struct {
|
||||
uint8_t Mod_id;
|
||||
@@ -122,7 +123,7 @@ typedef struct NR_IF_Module_s {
|
||||
//define the function pointer
|
||||
void (*NR_UL_indication)(NR_UL_IND_t *UL_INFO);
|
||||
void (*NR_Schedule_response)(NR_Sched_Rsp_t *Sched_INFO);
|
||||
void (*NR_slot_indication)(module_id_t module_idP, int CC_id, int frame, int slot);
|
||||
void (*NR_slot_indication)(const nfapi_nr_slot_indication_scf_t *ind, NR_Sched_Rsp_t *rsp);
|
||||
void (*NR_PHY_config_req)(NR_PHY_Config_t *config_INFO);
|
||||
uint32_t CC_mask;
|
||||
uint16_t current_frame;
|
||||
|
||||
Reference in New Issue
Block a user