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separate dl and ul bwp structures

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This commit is contained in:
francescomani
2022-06-15 18:41:36 +02:00
parent 1be8caaf69
commit 40049db9c9
11 changed files with 241 additions and 238 deletions
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openair1/SIMULATION/NR_PHY/dlsim.c
+6 -6
View File
@@ -272,7 +272,7 @@ void nr_dlsim_preprocessor(module_id_t module_id,
NR_UE_info_t *UE_info = RC.nrmac[module_id]->UE_info.list[0];
AssertFatal(RC.nrmac[module_id]->UE_info.list[1]==NULL, "can have only a single UE\n");
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl;
NR_UE_BWP_t *BWP = &UE_info->current_BWP;
NR_UE_DL_BWP_t *BWP = &UE_info->current_DL_BWP;
NR_ServingCellConfigCommon_t *scc = RC.nrmac[0]->common_channels[0].ServingCellConfigCommon;
/* manually set free CCE to 0 */
@@ -299,10 +299,10 @@ void nr_dlsim_preprocessor(module_id_t module_id,
sched_pdsch->mcs = g_mcsIndex;
/* the following might override the table that is mandated by RRC
* configuration */
ps->mcsTableIdx = g_mcsTableIdx;
BWP->mcsTableIdx = g_mcsTableIdx;
sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, ps->mcsTableIdx);
sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, ps->mcsTableIdx);
sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, BWP->mcsTableIdx);
sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, BWP->mcsTableIdx);
sched_pdsch->tb_size = nr_compute_tbs(sched_pdsch->Qm,
sched_pdsch->R,
sched_pdsch->rbSize,
@@ -330,7 +330,7 @@ void nr_dlsim_preprocessor(module_id_t module_id,
AssertFatal(sched_pdsch->rbStart >= 0, "invalid rbStart %d\n", sched_pdsch->rbStart);
AssertFatal(sched_pdsch->rbSize > 0, "invalid rbSize %d\n", sched_pdsch->rbSize);
AssertFatal(sched_pdsch->mcs >= 0, "invalid mcs %d\n", sched_pdsch->mcs);
AssertFatal(ps->mcsTableIdx >= 0 && ps->mcsTableIdx <= 2, "invalid mcsTableIdx %d\n", ps->mcsTableIdx);
AssertFatal(BWP->mcsTableIdx >= 0 && BWP->mcsTableIdx <= 2, "invalid mcsTableIdx %d\n", BWP->mcsTableIdx);
}
typedef struct {
@@ -835,7 +835,7 @@ int main(int argc, char **argv)
N_RB_DL = gNB->frame_parms.N_RB_DL;
NR_UE_info_t *UE_info = RC.nrmac[0]->UE_info.list[0];
configure_UE_BWP(RC.nrmac[0], &UE_info->current_BWP, scc, &UE_info->UE_sched_ctrl, NULL, UE_info->CellGroup);
configure_UE_BWP(RC.nrmac[0], scc, &UE_info->UE_sched_ctrl, NULL, UE_info);
// stub to configure frame_parms
// nr_phy_config_request_sim(gNB,N_RB_DL,N_RB_DL,mu,Nid_cell,SSB_positions);
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+35 -51
View File
@@ -568,7 +568,7 @@ void nr_initiate_ra_proc(module_id_t module_idP,
ra_rnti = 1 + symbol + (slotP * 14) + (freq_index * 14 * 80) + (ul_carrier_id * 14 * 80 * 8);
// Configure RA BWP
configure_UE_BWP(nr_mac, &ra->BWP, scc, NULL, ra, ra->CellGroup);
configure_UE_BWP(nr_mac, scc, NULL, ra, NULL);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 1);
@@ -606,7 +606,7 @@ void nr_initiate_ra_proc(module_id_t module_idP,
slotP,
&msg2_frame,
&msg2_slot,
ra->BWP.dl_scs,
ra->DL_BWP.scs,
scc,
frame_type,
monitoring_slot_period,
@@ -697,19 +697,19 @@ void nr_generate_Msg3_retransmission(module_id_t module_idP, int CC_id, frame_t
gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id];
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
NR_UE_BWP_t *ra_BWP = &ra->BWP;
NR_UE_UL_BWP_t *UL_BWP = &ra->UL_BWP;
NR_BWP_Uplink_t *ubwp = NULL;
NR_BWP_UplinkDedicated_t *ubwpd = NULL;
NR_PUSCH_TimeDomainResourceAllocationList_t *pusch_TimeDomainAllocationList = NULL;
if(ra->CellGroup) {
ubwp = ra->CellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[ra_BWP->ul_bwp_id-1];
ubwp = ra->CellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[UL_BWP->bwp_id-1];
ubwpd = ra->CellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP;
pusch_TimeDomainAllocationList = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList;
} else
pusch_TimeDomainAllocationList = scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList;
int mu = ra_BWP->ul_scs;
int mu = UL_BWP->scs;
uint8_t K2 = *pusch_TimeDomainAllocationList->list.array[ra->Msg3_tda_id]->k2;
const int sched_frame = frame + (slot + K2 >= nr_slots_per_frame[mu]);
const int sched_slot = (slot + K2) % nr_slots_per_frame[mu];
@@ -846,17 +846,17 @@ void nr_generate_Msg3_retransmission(module_id_t module_idP, int CC_id, frame_t
ra->Msg3_tda_id,
ra->msg3_TPC,
0, // not used in format 0_0
&ra->BWP);
&ra->UL_BWP);
fill_dci_pdu_rel15(scc,
ra->CellGroup,
ra_BWP,
&ra->DL_BWP,
dci_pdu,
&uldci_payload,
NR_UL_DCI_FORMAT_0_0,
NR_RNTI_TC,
pusch_pdu->bwp_size,
ra_BWP->ul_bwp_id,
UL_BWP->bwp_id,
coresetid,
nr_mac->cset0_bwp_size);
@@ -894,9 +894,9 @@ void nr_get_Msg3alloc(module_id_t module_id,
uint16_t msg3_nb_rb = 8; // sdu has 6 or 8 bytes
frame_type_t frame_type = RC.nrmac[module_id]->common_channels->frame_type;
NR_UE_BWP_t *ra_BWP = &ra->BWP;
NR_UE_UL_BWP_t *UL_BWP = &ra->UL_BWP;
int mu = ra_BWP->ul_scs;
int mu = UL_BWP->scs;
int StartSymbolIndex = 0;
int NrOfSymbols = 0;
int startSymbolAndLength = 0;
@@ -969,9 +969,9 @@ void nr_get_Msg3alloc(module_id_t module_id,
int bwpSize = NRRIV2BW(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
int bwpStart = NRRIV2PRBOFFSET(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
if (bwpSize != ra_BWP->ul_BWPSize || bwpStart != ra_BWP->ul_BWPStart) {
int act_bwp_start = ra_BWP->ul_BWPStart;
int act_bwp_size = ra_BWP->ul_BWPSize;
if (bwpSize != UL_BWP->BWPSize || bwpStart != UL_BWP->BWPStart) {
int act_bwp_start = UL_BWP->BWPStart;
int act_bwp_size = UL_BWP->BWPSize;
if (!((bwpStart >= act_bwp_start) && ((bwpStart+bwpSize) <= (act_bwp_start+act_bwp_size))))
bwpStart = act_bwp_start;
}
@@ -1080,7 +1080,7 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t
gNB_MAC_INST *mac = RC.nrmac[module_idP];
NR_COMMON_channels_t *cc = &mac->common_channels[CC_id];
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
NR_UE_BWP_t *ra_BWP = &ra->BWP;
NR_UE_UL_BWP_t *UL_BWP = &ra->UL_BWP;
if (ra->state == RA_IDLE) {
LOG_W(NR_MAC,"RA is not active for RA %X. skipping msg3 scheduling\n", ra->rnti);
@@ -1114,13 +1114,13 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t
memset(pusch_pdu, 0, sizeof(nfapi_nr_pusch_pdu_t));
int ibwp_size = NRRIV2BW(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
int scs = ra_BWP->ul_scs;
int scs = UL_BWP->scs;
int fh = 0;
int startSymbolAndLength = scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[ra->Msg3_tda_id]->startSymbolAndLength;
int mappingtype = scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[ra->Msg3_tda_id]->mappingType;
if (ra->CellGroup) {
NR_BWP_Uplink_t *ubwp = ra->CellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[ra_BWP->ul_bwp_id - 1];
NR_BWP_Uplink_t *ubwp = ra->CellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[UL_BWP->bwp_id - 1];
startSymbolAndLength = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[ra->Msg3_tda_id]->startSymbolAndLength;
mappingtype = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[ra->Msg3_tda_id]->mappingType;
@@ -1154,7 +1154,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id];
NR_UE_BWP_t *ra_BWP = &ra->BWP;
NR_UE_DL_BWP_t *DL_BWP = &ra->DL_BWP;
if ((ra->Msg2_frame == frameP) && (ra->Msg2_slot == slotP)) {
@@ -1165,13 +1165,13 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
NR_SearchSpace_t *ss = ra->ra_ss;
NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_TimeDomainAllocationList = ra_BWP->tdaList;
NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_TimeDomainAllocationList = DL_BWP->tdaList;
long BWPStart = 0;
long BWPSize = 0;
NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config = NULL;
if(*ss->controlResourceSetId!=0) {
BWPStart = ra_BWP->dl_BWPStart;
BWPStart = DL_BWP->BWPStart;
BWPSize = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
} else {
type0_PDCCH_CSS_config = &nr_mac->type0_PDCCH_CSS_config[ra->beam_id];
@@ -1265,16 +1265,8 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
// information to data and is reset every slot.
const int pduindex = nr_mac->pdu_index[CC_id]++;
NR_PDSCH_Config_t *pdsch_Config = ra_BWP->pdsch_Config;
uint8_t mcsTableIdx = 0;
if (pdsch_Config &&
pdsch_Config->mcs_Table) {
if (*pdsch_Config->mcs_Table == 0)
mcsTableIdx = 1;
else
mcsTableIdx = 2;
}
else mcsTableIdx = 0;
NR_PDSCH_Config_t *pdsch_Config = DL_BWP->pdsch_Config;
uint8_t mcsTableIdx = DL_BWP->mcsTableIdx;
int dmrsConfigType=0;
if (pdsch_Config &&
@@ -1288,7 +1280,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
pdsch_pdu_rel15->pduIndex = pduindex;
pdsch_pdu_rel15->BWPSize = BWPSize;
pdsch_pdu_rel15->BWPStart = BWPStart;
pdsch_pdu_rel15->SubcarrierSpacing = ra_BWP->dl_scs;
pdsch_pdu_rel15->SubcarrierSpacing = DL_BWP->scs;
pdsch_pdu_rel15->CyclicPrefix = 0;
pdsch_pdu_rel15->NrOfCodewords = 1;
pdsch_pdu_rel15->mcsTable[0] = mcsTableIdx;
@@ -1401,13 +1393,13 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
fill_dci_pdu_rel15(scc,
ra->CellGroup,
ra_BWP,
DL_BWP,
&pdcch_pdu_rel15->dci_pdu[pdcch_pdu_rel15->numDlDci - 1],
&dci_payload,
NR_DL_DCI_FORMAT_1_0,
NR_RNTI_RA,
BWPSize,
ra_BWP->dl_bwp_id,
DL_BWP->bwp_id,
coresetid,
nr_mac->cset0_bwp_size);
@@ -1416,7 +1408,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
// Program UL processing for Msg3
NR_BWP_Uplink_t *ubwp = ra->CellGroup ?
ra->CellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[ra_BWP->ul_bwp_id-1] :
ra->CellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[ra->UL_BWP.bwp_id-1] :
NULL;
nr_get_Msg3alloc(module_idP, CC_id, scc, ubwp, slotP, frameP, ra, nr_mac->tdd_beam_association);
nr_add_msg3(module_idP, CC_id, frameP, slotP, ra, (uint8_t *) &tx_req->TLVs[0].value.direct[0]);
@@ -1456,7 +1448,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id];
NR_UE_BWP_t *ra_BWP = &ra->BWP;
NR_UE_DL_BWP_t *DL_BWP = &ra->DL_BWP;
if (ra->Msg4_frame == frameP && ra->Msg4_slot == slotP ) {
@@ -1467,7 +1459,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
NR_SearchSpace_t *ss = ra->ra_ss;
NR_ControlResourceSet_t *coreset = ra->coreset;
NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_TimeDomainAllocationList = ra_BWP->tdaList;
NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_TimeDomainAllocationList = DL_BWP->tdaList;
AssertFatal(coreset!=NULL,"Coreset cannot be null for RA-Msg4\n");
@@ -1490,8 +1482,8 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
long BWPSize = 0;
NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config = NULL;
if(*ss->controlResourceSetId!=0) {
BWPStart = ra_BWP->dl_BWPStart;
BWPSize = ra_BWP->dl_BWPSize;
BWPStart = DL_BWP->BWPStart;
BWPSize = DL_BWP->BWPSize;
} else {
type0_PDCCH_CSS_config = &nr_mac->type0_PDCCH_CSS_config[ra->beam_id];
BWPStart = type0_PDCCH_CSS_config->cset_start_rb;
@@ -1601,7 +1593,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
uint16_t N_DMRS_SLOT = get_num_dmrs(dlDmrsSymbPos);
NR_PDSCH_Config_t *pdsch_Config = ra_BWP->pdsch_Config;
NR_PDSCH_Config_t *pdsch_Config = DL_BWP->pdsch_Config;
int dmrsConfigType=0;
if (pdsch_Config &&
pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA &&
@@ -1627,15 +1619,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
N_PRB_DMRS = nr_mac->sched_ctrlCommon->pdsch_semi_static.numDmrsCdmGrpsNoData * 4;
}
uint8_t mcsTableIdx = 0;
if (pdsch_Config &&
pdsch_Config->mcs_Table) {
if (*pdsch_Config->mcs_Table == 0)
mcsTableIdx = 1;
else
mcsTableIdx = 2;
}
else mcsTableIdx = 0;
uint8_t mcsTableIdx = DL_BWP->mcsTableIdx;
int rbStart = 0;
int rbSize = 0;
@@ -1711,7 +1695,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
pdsch_pdu_rel15->pduIndex = pduindex;
pdsch_pdu_rel15->BWPSize = BWPSize;
pdsch_pdu_rel15->BWPStart = BWPStart;
pdsch_pdu_rel15->SubcarrierSpacing = ra_BWP->dl_scs;
pdsch_pdu_rel15->SubcarrierSpacing = DL_BWP->scs;
pdsch_pdu_rel15->CyclicPrefix = 0;
pdsch_pdu_rel15->NrOfCodewords = 1;
int R = nr_get_code_rate_dl(mcsIndex,mcsTableIdx);
@@ -1806,13 +1790,13 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
fill_dci_pdu_rel15(scc,
ra->CellGroup,
ra_BWP,
DL_BWP,
&pdcch_pdu_rel15->dci_pdu[pdcch_pdu_rel15->numDlDci - 1],
&dci_payload,
NR_DL_DCI_FORMAT_1_0,
NR_RNTI_TC,
pdsch_pdu_rel15->BWPSize,
ra_BWP->dl_bwp_id,
DL_BWP->bwp_id,
coresetid,
nr_mac->cset0_bwp_size);
@@ -1908,7 +1892,7 @@ void nr_check_Msg4_Ack(module_id_t module_id, int CC_id, frame_t frame, sub_fram
uint32_t delay_ms = servingCellConfig && servingCellConfig->downlinkBWP_ToAddModList ?
NR_RRC_SETUP_DELAY_MS + NR_RRC_BWP_SWITCHING_DELAY_MS : NR_RRC_SETUP_DELAY_MS;
sched_ctrl->rrc_processing_timer = (delay_ms << ra->BWP.dl_scs);
sched_ctrl->rrc_processing_timer = (delay_ms << ra->DL_BWP.scs);
LOG_I(NR_MAC, "(%d.%d) Activating RRC processing timer for UE %04x with %d ms\n", frame, slot, UE->rnti, delay_ms);
} else {
LOG_I(NR_MAC, "(ue rnti 0x%04x) RA Procedure failed at Msg4!\n", ra->rnti);
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
+6 -6
View File
@@ -352,7 +352,6 @@ uint32_t schedule_control_sib1(module_id_t module_id,
}
gNB_mac->sched_ctrlCommon->pdsch_semi_static.time_domain_allocation = time_domain_allocation;
gNB_mac->sched_ctrlCommon->pdsch_semi_static.mcsTableIdx = 0;
gNB_mac->sched_ctrlCommon->sched_pdsch.mcs = 0; // starting from mcs 0
gNB_mac->sched_ctrlCommon->num_total_bytes = num_total_bytes;
@@ -389,6 +388,7 @@ uint32_t schedule_control_sib1(module_id_t module_id,
uint8_t N_PRB_DMRS = gNB_mac->sched_ctrlCommon->pdsch_semi_static.numDmrsCdmGrpsNoData * 6;
uint16_t dmrs_length = get_num_dmrs(dlDmrsSymbPos);
LOG_D(MAC,"dlDmrsSymbPos %x\n",dlDmrsSymbPos);
int mcsTableIdx = 0;
int rbSize = 0;
uint32_t TBS = 0;
do {
@@ -400,8 +400,8 @@ uint32_t schedule_control_sib1(module_id_t module_id,
else
break;
}
TBS = nr_compute_tbs(nr_get_Qm_dl(gNB_mac->sched_ctrlCommon->sched_pdsch.mcs, gNB_mac->sched_ctrlCommon->pdsch_semi_static.mcsTableIdx),
nr_get_code_rate_dl(gNB_mac->sched_ctrlCommon->sched_pdsch.mcs, gNB_mac->sched_ctrlCommon->pdsch_semi_static.mcsTableIdx),
TBS = nr_compute_tbs(nr_get_Qm_dl(gNB_mac->sched_ctrlCommon->sched_pdsch.mcs, mcsTableIdx),
nr_get_code_rate_dl(gNB_mac->sched_ctrlCommon->sched_pdsch.mcs, mcsTableIdx),
rbSize, nrOfSymbols, N_PRB_DMRS * dmrs_length,0, 0,1) >> 3;
} while (TBS < gNB_mac->sched_ctrlCommon->num_total_bytes);
@@ -443,7 +443,7 @@ void nr_fill_nfapi_dl_sib1_pdu(int Mod_idP,
gNB_MAC_INST *gNB_mac = RC.nrmac[Mod_idP];
NR_COMMON_channels_t *cc = gNB_mac->common_channels;
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
int mcsTableIdx = 0;
nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
memset((void*)dl_tti_pdcch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t));
dl_tti_pdcch_pdu->PDUType = NFAPI_NR_DL_TTI_PDCCH_PDU_TYPE;
@@ -494,9 +494,9 @@ void nr_fill_nfapi_dl_sib1_pdu(int Mod_idP,
pdsch_pdu_rel15->rbSize = gNB_mac->sched_ctrlCommon->sched_pdsch.rbSize;
pdsch_pdu_rel15->VRBtoPRBMapping = 0;
pdsch_pdu_rel15->qamModOrder[0] = nr_get_Qm_dl(gNB_mac->sched_ctrlCommon->sched_pdsch.mcs,
gNB_mac->sched_ctrlCommon->pdsch_semi_static.mcsTableIdx);
mcsTableIdx);
pdsch_pdu_rel15->TBSize[0] = TBS;
pdsch_pdu_rel15->mcsTable[0] = gNB_mac->sched_ctrlCommon->pdsch_semi_static.mcsTableIdx;
pdsch_pdu_rel15->mcsTable[0] = mcsTableIdx;
pdsch_pdu_rel15->StartSymbolIndex = StartSymbolIndex;
pdsch_pdu_rel15->NrOfSymbols = NrOfSymbols;
pdsch_pdu_rel15->dlDmrsSymbPos = dlDmrsSymbPos;
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
+21 -20
View File
@@ -376,7 +376,7 @@ bool allocate_dl_retransmission(module_id_t module_id,
gNB_MAC_INST *nr_mac = RC.nrmac[module_id];
const NR_ServingCellConfigCommon_t *scc = nr_mac->common_channels->ServingCellConfigCommon;
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_BWP_t *BWP = &UE->current_BWP;
NR_UE_DL_BWP_t *BWP = &UE->current_DL_BWP;
NR_sched_pdsch_t *retInfo = &sched_ctrl->harq_processes[current_harq_pid].sched_pdsch;
NR_CellGroupConfig_t *cg = UE->CellGroup;
@@ -388,7 +388,7 @@ bool allocate_dl_retransmission(module_id_t module_id,
cg->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP : NULL;
const int coresetid = sched_ctrl->coreset->controlResourceSetId;
const uint16_t bwpSize = coresetid == 0 ? RC.nrmac[module_id]->cset0_bwp_size : UE->current_BWP.dl_BWPSize;
const uint16_t bwpSize = coresetid == 0 ? RC.nrmac[module_id]->cset0_bwp_size : BWP->BWPSize;
int rbStart = 0; // start wrt BWPstart
NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
@@ -567,6 +567,7 @@ void pf_dl(module_id_t module_id,
continue;
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_DL_BWP_t *BWP = &UE->current_DL_BWP;
if (sched_ctrl->ul_failure==1 && get_softmodem_params()->phy_test==0) continue;
@@ -606,12 +607,12 @@ void pf_dl(module_id_t module_id,
/* Calculate coeff */
const NR_bler_options_t *bo = &mac->dl_bler;
const int max_mcs_table = ps->mcsTableIdx == 1 ? 27 : 28;
const int max_mcs_table = BWP->mcsTableIdx == 1 ? 27 : 28;
const int max_mcs = min(sched_ctrl->dl_max_mcs, max_mcs_table);
sched_pdsch->mcs = get_mcs_from_bler(bo, stats, &sched_ctrl->dl_bler_stats, max_mcs, frame);
UE->layers = set_dl_nrOfLayers(sched_ctrl);
const uint8_t Qm = nr_get_Qm_dl(sched_pdsch->mcs, ps->mcsTableIdx);
const uint16_t R = nr_get_code_rate_dl(sched_pdsch->mcs, ps->mcsTableIdx);
const uint8_t Qm = nr_get_Qm_dl(sched_pdsch->mcs, BWP->mcsTableIdx);
const uint16_t R = nr_get_code_rate_dl(sched_pdsch->mcs, BWP->mcsTableIdx);
uint32_t tbs = nr_compute_tbs(Qm,
R,
1, /* rbSize */
@@ -650,12 +651,12 @@ void pf_dl(module_id_t module_id,
NR_UE_sched_ctrl_t *sched_ctrl = &iterator->UE->UE_sched_ctrl;
const uint16_t rnti = iterator->UE->rnti;
NR_UE_BWP_t *BWP = &iterator->UE->current_BWP;
NR_UE_DL_BWP_t *BWP = &iterator->UE->current_DL_BWP;
const int coresetid = sched_ctrl->coreset->controlResourceSetId;
const uint16_t bwpSize = coresetid == 0 ?
RC.nrmac[module_id]->cset0_bwp_size :
BWP->dl_BWPSize;
BWP->BWPSize;
int rbStart = 0; // start wrt BWPstart
if (sched_ctrl->available_dl_harq.head < 0) {
@@ -744,8 +745,8 @@ void pf_dl(module_id_t module_id,
while (rbStart + max_rbSize < bwpSize && (rballoc_mask[rbStart + max_rbSize] & slbitmap) == slbitmap)
max_rbSize++;
sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, ps->mcsTableIdx);
sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, ps->mcsTableIdx);
sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, BWP->mcsTableIdx);
sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, BWP->mcsTableIdx);
sched_pdsch->pucch_allocation = alloc;
uint32_t TBS = 0;
uint16_t rbSize;
@@ -791,7 +792,7 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
/* This is temporary and it assumes all UEs have the same BWP and TDA*/
NR_UE_info_t *UE=UE_info->list[0];
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_BWP_t *BWP = &UE->current_BWP;
NR_UE_DL_BWP_t *BWP = &UE->current_DL_BWP;
const int tda = get_dl_tda(RC.nrmac[module_id], scc, slot);
int startSymbolIndex, nrOfSymbols;
const struct NR_PDSCH_TimeDomainResourceAllocationList *tdaList = BWP->tdaList;
@@ -801,8 +802,8 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
const int coresetid = sched_ctrl->coreset->controlResourceSetId;
const uint16_t bwpSize = coresetid == 0 ? RC.nrmac[module_id]->cset0_bwp_size : BWP->dl_BWPSize;
const uint16_t BWPStart = coresetid == 0 ? RC.nrmac[module_id]->cset0_bwp_start : BWP->dl_BWPStart;
const uint16_t bwpSize = coresetid == 0 ? RC.nrmac[module_id]->cset0_bwp_size : BWP->BWPSize;
const uint16_t BWPStart = coresetid == 0 ? RC.nrmac[module_id]->cset0_bwp_start : BWP->BWPStart;
const uint16_t slbitmap = SL_to_bitmap(startSymbolIndex, nrOfSymbols);
uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
@@ -879,7 +880,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
UE_iterator(UE_info->list, UE) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_BWP_t *current_BWP = &UE->current_BWP;
NR_UE_DL_BWP_t *current_BWP = &UE->current_DL_BWP;
if (sched_ctrl->ul_failure==1 && get_softmodem_params()->phy_test==0) continue;
@@ -963,7 +964,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
NR_SearchSpace_t *ss = sched_ctrl->search_space;
const int bwp_id = current_BWP->dl_bwp_id;
const int bwp_id = current_BWP->bwp_id;
const int coresetid = sched_ctrl->coreset->controlResourceSetId;
/* look up the PDCCH PDU for this CC, BWP, and CORESET. If it does not exist, create it */
@@ -1001,19 +1002,19 @@ void nr_schedule_ue_spec(module_id_t module_id,
pdsch_pdu->BWPSize = gNB_mac->cset0_bwp_size;
pdsch_pdu->BWPStart = gNB_mac->cset0_bwp_start;
} else {
pdsch_pdu->BWPSize = current_BWP->dl_BWPSize;
pdsch_pdu->BWPStart = current_BWP->dl_BWPStart;
pdsch_pdu->BWPSize = current_BWP->BWPSize;
pdsch_pdu->BWPStart = current_BWP->BWPStart;
}
pdsch_pdu->SubcarrierSpacing = current_BWP->dl_scs;
pdsch_pdu->CyclicPrefix = current_BWP->dl_cyclicprefix ? *current_BWP->dl_cyclicprefix : 0;
pdsch_pdu->SubcarrierSpacing = current_BWP->scs;
pdsch_pdu->CyclicPrefix = current_BWP->cyclicprefix ? *current_BWP->cyclicprefix : 0;
// Codeword information
pdsch_pdu->NrOfCodewords = 1;
//number of information bits per 1024 coded bits expressed in 0.1 bit units
pdsch_pdu->targetCodeRate[0] = R;
pdsch_pdu->qamModOrder[0] = Qm;
pdsch_pdu->mcsIndex[0] = sched_pdsch->mcs;
pdsch_pdu->mcsTable[0] = ps->mcsTableIdx;
pdsch_pdu->mcsTable[0] = current_BWP->mcsTableIdx;
AssertFatal(harq!=NULL,"harq is null\n");
AssertFatal(harq->round<4,"%d",harq->round);
pdsch_pdu->rvIndex[0] = nr_rv_round_map[harq->round];
@@ -1056,7 +1057,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
// Maximum number of PRBs across all configured DL BWPs
int scc_bwpsize = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
int bw_tbslbrm = get_bw_tbslbrm(scc_bwpsize, cg);
pdsch_pdu->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(ps->mcsTableIdx,
pdsch_pdu->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(current_BWP->mcsTableIdx,
bw_tbslbrm,
nl_tbslbrm);
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
+9 -9
View File
@@ -195,7 +195,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
NR_UE_info_t *UE = RC.nrmac[module_id]->UE_info.list[0];
NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[0].ServingCellConfigCommon;
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_BWP_t *BWP = &UE->current_BWP;
NR_UE_DL_BWP_t *BWP = &UE->current_DL_BWP;
const int CC_id = 0;
const int tda = get_dl_tda(RC.nrmac[module_id], scc, slot);
@@ -205,8 +205,8 @@ void nr_preprocessor_phytest(module_id_t module_id,
nr_set_pdsch_semi_static(BWP, scc, UE->CellGroup, tda, target_dl_Nl,sched_ctrl , ps);
/* find largest unallocated chunk */
const int bwpSize = BWP->dl_BWPSize;
const int BWPStart = BWP->dl_BWPStart;
const int bwpSize = BWP->BWPSize;
const int BWPStart = BWP->BWPStart;
int rbStart = 0;
int rbSize = 0;
@@ -311,8 +311,8 @@ void nr_preprocessor_phytest(module_id_t module_id,
sched_pdsch->rbSize = rbSize;
sched_pdsch->mcs = target_dl_mcs;
sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, ps->mcsTableIdx);
sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, ps->mcsTableIdx);
sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, BWP->mcsTableIdx);
sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, BWP->mcsTableIdx);
sched_pdsch->tb_size = nr_compute_tbs(sched_pdsch->Qm,
sched_pdsch->R,
sched_pdsch->rbSize,
@@ -352,8 +352,8 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
const int CC_id = 0;
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_BWP_t *BWP = &UE->current_BWP;
const int mu = BWP->ul_scs;
NR_UE_UL_BWP_t *BWP = &UE->current_UL_BWP;
const int mu = BWP->scs;
const struct NR_PUSCH_TimeDomainResourceAllocationList *tdaList =
sched_ctrl->active_ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList;
@@ -400,8 +400,8 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
uint16_t rbStart = 0;
uint16_t rbSize;
const int bw = BWP->ul_BWPSize;
const int BWPStart = BWP->ul_BWPStart;
const int bw = BWP->BWPSize;
const int BWPStart = BWP->BWPStart;
if (target_ul_bw>bw)
rbSize = bw;
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+94 -83
View File
@@ -528,7 +528,7 @@ bool nr_find_nb_rb(uint16_t Qm,
return *tbs >= bytes && *nb_rb <= nb_rb_max;
}
void nr_set_pdsch_semi_static(const NR_UE_BWP_t *BWP,
void nr_set_pdsch_semi_static(const NR_UE_DL_BWP_t *BWP,
const NR_ServingCellConfigCommon_t *scc,
const NR_CellGroupConfig_t *secondaryCellGroup,
int tda,
@@ -951,12 +951,12 @@ void config_uldci(const NR_SIB1_t *sib1,
int time_domain_assignment,
uint8_t tpc,
int n_ubwp,
NR_UE_BWP_t *BWP) {
NR_UE_UL_BWP_t *UBWP) {
int bwp_id = BWP->ul_bwp_id;
int bwp_id = UBWP->bwp_id;
dci_pdu_rel15->frequency_domain_assignment.val =
PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, pusch_pdu->rb_start, BWP->ul_BWPSize);
PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, pusch_pdu->rb_start, UBWP->BWPSize);
dci_pdu_rel15->time_domain_assignment.val = time_domain_assignment;
dci_pdu_rel15->frequency_hopping_flag.val = pusch_pdu->frequency_hopping;
dci_pdu_rel15->mcs = pusch_pdu->mcs_index;
@@ -1163,12 +1163,12 @@ void nr_configure_pucch(const NR_SIB1_t *sib1,
else
pucch_pdu->hopping_id = *scc->physCellId;
NR_UE_BWP_t *BWP = &UE->current_BWP;
NR_UE_UL_BWP_t *BWP = &UE->current_UL_BWP;
pucch_pdu->bwp_size = BWP->ul_BWPSize;
pucch_pdu->bwp_start = BWP->ul_BWPStart;
pucch_pdu->subcarrier_spacing = BWP->ul_scs;
pucch_pdu->cyclic_prefix = (BWP->ul_cyclicprefix==NULL) ? 0 : *BWP->ul_cyclicprefix;
pucch_pdu->bwp_size = BWP->BWPSize;
pucch_pdu->bwp_start = BWP->BWPStart;
pucch_pdu->subcarrier_spacing = BWP->scs;
pucch_pdu->cyclic_prefix = (BWP->cyclicprefix==NULL) ? 0 : *BWP->cyclicprefix;
if (r_pucch<0 || bwp ){
LOG_D(NR_MAC,"pucch_acknak: Filling dedicated configuration for PUCCH\n");
// we have either a dedicated BWP or Dedicated PUCCH configuration on InitialBWP
@@ -1372,7 +1372,7 @@ void set_r_pucch_parms(int rsetindex,
void prepare_dci(const NR_CellGroupConfig_t *CellGroup,
const NR_UE_BWP_t *BWP,
const NR_UE_DL_BWP_t *BWP,
dci_pdu_rel15_t *dci_pdu_rel15,
nr_dci_format_t format,
int bwp_id) {
@@ -1465,7 +1465,7 @@ void prepare_dci(const NR_CellGroupConfig_t *CellGroup,
void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
const NR_CellGroupConfig_t *CellGroup,
const NR_UE_BWP_t *BWP,
const NR_UE_DL_BWP_t *BWP,
nfapi_nr_dl_dci_pdu_t *pdcch_dci_pdu,
dci_pdu_rel15_t *dci_pdu_rel15,
int dci_format,
@@ -2290,18 +2290,31 @@ void delete_nr_ue_data(NR_UE_info_t *UE, NR_COMMON_channels_t *ccPtr)
}
void configure_UE_BWP(gNB_MAC_INST *nr_mac,
NR_UE_BWP_t *BWP,
NR_ServingCellConfigCommon_t *scc,
NR_UE_sched_ctrl_t *sched_ctrl,
NR_RA_t *ra,
NR_CellGroupConfig_t *CellGroup) {
NR_UE_info_t *UE) {
NR_CellGroupConfig_t *CellGroup;
NR_UE_DL_BWP_t *DL_BWP;
NR_UE_UL_BWP_t *UL_BWP;
if (ra) {
DL_BWP = &ra->DL_BWP;
UL_BWP = &ra->UL_BWP;
CellGroup = ra->CellGroup;
}
else {
DL_BWP = &UE->current_DL_BWP;
UL_BWP = &UE->current_UL_BWP;
CellGroup = UE->CellGroup;
}
NR_BWP_Downlink_t *dl_bwp = NULL;
NR_BWP_Uplink_t *ul_bwp = NULL;
NR_BWP_DownlinkDedicated_t *bwpd = NULL;
NR_BWP_UplinkDedicated_t *ubwpd = NULL;
BWP->n_dl_bwp = 1;
int old_dl_bwp_id = BWP->dl_bwp_id;
DL_BWP->n_dl_bwp = 1;
int old_dl_bwp_id = DL_BWP->bwp_id;
int target_ss;
@@ -2315,33 +2328,31 @@ void configure_UE_BWP(gNB_MAC_INST *nr_mac,
// (re)configuring BWP
// TODO BWP switching not via RRC reconfiguration
// via RRC if firstActiveXlinkBWP_Id is NULL, MAC stays on the same BWP as before
if (servingCellConfig->firstActiveDownlinkBWP_Id) {
BWP->dl_bwp_id = *servingCellConfig->firstActiveDownlinkBWP_Id;
BWP->ul_bwp_id = *servingCellConfig->firstActiveDownlinkBWP_Id;
}
if (servingCellConfig->firstActiveDownlinkBWP_Id)
DL_BWP->bwp_id = *servingCellConfig->firstActiveDownlinkBWP_Id;
if (servingCellConfig->uplinkConfig->firstActiveUplinkBWP_Id)
BWP->ul_bwp_id = *servingCellConfig->uplinkConfig->firstActiveUplinkBWP_Id;
UL_BWP->bwp_id = *servingCellConfig->uplinkConfig->firstActiveUplinkBWP_Id;
const struct NR_ServingCellConfig__downlinkBWP_ToAddModList *bwpList = servingCellConfig->downlinkBWP_ToAddModList;
if(bwpList)
BWP->n_dl_bwp = bwpList->list.count;
if (BWP->dl_bwp_id>0) {
DL_BWP->n_dl_bwp = bwpList->list.count;
if (DL_BWP->bwp_id>0) {
for (int i=0; i<bwpList->list.count; i++) {
dl_bwp = bwpList->list.array[i];
if(dl_bwp->bwp_Id == BWP->dl_bwp_id)
if(dl_bwp->bwp_Id == DL_BWP->bwp_id)
break;
}
AssertFatal(dl_bwp!=NULL,"Couldn't find DLBWP corresponding to BWP ID %ld\n",BWP->dl_bwp_id);
AssertFatal(dl_bwp!=NULL,"Couldn't find DLBWP corresponding to BWP ID %ld\n",DL_BWP->bwp_id);
}
const struct NR_UplinkConfig__uplinkBWP_ToAddModList *ubwpList = servingCellConfig->uplinkConfig->uplinkBWP_ToAddModList;
if (BWP->ul_bwp_id>0) {
if (UL_BWP->bwp_id>0) {
for (int i=0; i<ubwpList->list.count; i++) {
ul_bwp = ubwpList->list.array[i];
if(ul_bwp->bwp_Id == BWP->ul_bwp_id)
if(ul_bwp->bwp_Id == UL_BWP->bwp_id)
break;
}
AssertFatal(ul_bwp!=NULL,"Couldn't find DLBWP corresponding to BWP ID %ld\n",BWP->ul_bwp_id);
AssertFatal(ul_bwp!=NULL,"Couldn't find DLBWP corresponding to BWP ID %ld\n",UL_BWP->bwp_id);
}
// selection of dedicated BWPs
@@ -2354,43 +2365,54 @@ void configure_UE_BWP(gNB_MAC_INST *nr_mac,
else
ubwpd = servingCellConfig->uplinkConfig->initialUplinkBWP;
BWP->pdsch_Config = bwpd->pdsch_Config->choice.setup;
DL_BWP->pdsch_Config = bwpd->pdsch_Config->choice.setup;
}
else {
BWP->dl_bwp_id = 0;
BWP->ul_bwp_id = 0;
DL_BWP->bwp_id = 0;
DL_BWP->bwp_id = 0;
target_ss = NR_SearchSpace__searchSpaceType_PR_common;
BWP->pdsch_Config = NULL;
DL_BWP->pdsch_Config = NULL;
}
if (old_dl_bwp_id != BWP->dl_bwp_id)
LOG_I(NR_MAC, "Switching to DL-BWP %li\n", BWP->dl_bwp_id);
if (old_dl_bwp_id != DL_BWP->bwp_id)
LOG_I(NR_MAC, "Switching to DL-BWP %li\n", DL_BWP->bwp_id);
if (BWP->dl_bwp_id>0)
BWP->tdaList = dl_bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
if (DL_BWP->bwp_id>0)
DL_BWP->tdaList = dl_bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
else
BWP->tdaList = scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
DL_BWP->tdaList = scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
// setting generic parameters
NR_BWP_t dl_genericParameters = (BWP->dl_bwp_id>0 && dl_bwp) ?
NR_BWP_t dl_genericParameters = (DL_BWP->bwp_id>0 && dl_bwp) ?
dl_bwp->bwp_Common->genericParameters:
scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters;
BWP->dl_scs = dl_genericParameters.subcarrierSpacing;
BWP->dl_cyclicprefix = dl_genericParameters.cyclicPrefix;
BWP->dl_BWPSize = NRRIV2BW(dl_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
BWP->dl_BWPStart = NRRIV2PRBOFFSET(dl_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
DL_BWP->scs = dl_genericParameters.subcarrierSpacing;
DL_BWP->cyclicprefix = dl_genericParameters.cyclicPrefix;
DL_BWP->BWPSize = NRRIV2BW(dl_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
DL_BWP->BWPStart = NRRIV2PRBOFFSET(dl_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
NR_BWP_t ul_genericParameters = (BWP->ul_bwp_id>0 && ul_bwp) ?
NR_BWP_t ul_genericParameters = (UL_BWP->bwp_id>0 && ul_bwp) ?
ul_bwp->bwp_Common->genericParameters:
scc->uplinkConfigCommon->initialUplinkBWP->genericParameters;
BWP->ul_scs = ul_genericParameters.subcarrierSpacing;
BWP->ul_cyclicprefix = ul_genericParameters.cyclicPrefix;
BWP->ul_BWPSize = NRRIV2BW(ul_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
BWP->ul_BWPStart = NRRIV2PRBOFFSET(ul_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
UL_BWP->scs = ul_genericParameters.subcarrierSpacing;
UL_BWP->cyclicprefix = ul_genericParameters.cyclicPrefix;
UL_BWP->BWPSize = NRRIV2BW(ul_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
UL_BWP->BWPStart = NRRIV2PRBOFFSET(ul_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
if(sched_ctrl) {
// Set downlink MCS table
if (DL_BWP->pdsch_Config &&
DL_BWP->pdsch_Config->mcs_Table) {
if (*DL_BWP->pdsch_Config->mcs_Table == 0)
DL_BWP->mcsTableIdx = 1;
else
DL_BWP->mcsTableIdx = 2;
} else
DL_BWP->mcsTableIdx = 0;
LOG_D(NR_MAC,"MCS Table Index: %d\n",DL_BWP->mcsTableIdx);
if(UE) {
// setting PDCCH related structures for sched_ctrl
sched_ctrl->search_space = get_searchspace(scc,
bwpd,
@@ -2486,9 +2508,11 @@ NR_UE_info_t *add_new_nr_ue(gNB_MAC_INST *nr_mac, rnti_t rntiP, NR_CellGroupConf
sched_ctrl->sched_srs.srs_scheduled = false;
// initialize UE BWP information
NR_UE_BWP_t *BWP = &UE->current_BWP;
memset(BWP, 0, sizeof(*BWP));
configure_UE_BWP(nr_mac, BWP, scc, sched_ctrl, NULL, CellGroup);
NR_UE_DL_BWP_t *DL_BWP = &UE->current_DL_BWP;
memset(DL_BWP, 0, sizeof(*DL_BWP));
NR_UE_UL_BWP_t *UL_BWP = &UE->current_UL_BWP;
memset(UL_BWP, 0, sizeof(*UL_BWP));
configure_UE_BWP(nr_mac, scc, sched_ctrl, NULL, UE);
/* set illegal time domain allocation to force recomputation of all fields */
sched_ctrl->pdsch_semi_static.time_domain_allocation = -1;
@@ -2504,7 +2528,7 @@ NR_UE_info_t *add_new_nr_ue(gNB_MAC_INST *nr_mac, rnti_t rntiP, NR_CellGroupConf
"uplinkBWP_ToAddModList has %d BWP!\n",
ubwpList->list.count);
sched_ctrl->active_ubwp = ubwpList && BWP->ul_bwp_id > 0 ? ubwpList->list.array[BWP->ul_bwp_id - 1] : NULL;
sched_ctrl->active_ubwp = ubwpList && UL_BWP->bwp_id > 0 ? ubwpList->list.array[UL_BWP->bwp_id - 1] : NULL;
/* get Number of HARQ processes for this UE */
if (servingCellConfig)
@@ -2630,8 +2654,8 @@ void get_pdsch_to_harq_feedback(NR_UE_info_t *UE,
NR_CellGroupConfig_t *CellGroup = UE->CellGroup;
NR_BWP_DownlinkDedicated_t *bwpd=NULL;
NR_BWP_UplinkDedicated_t *ubwpd=NULL;
int dl_bwp_id = UE->current_BWP.dl_bwp_id;
int ul_bwp_id = UE->current_BWP.ul_bwp_id;
int dl_bwp_id = UE->current_DL_BWP.bwp_id;
int ul_bwp_id = UE->current_UL_BWP.bwp_id;
if (ss_type == NR_SearchSpace__searchSpaceType_PR_ue_Specific) {
AssertFatal(CellGroup!=NULL,"Cellgroup is not defined for UE %04x\n",UE->rnti);
@@ -2728,7 +2752,7 @@ void nr_csirs_scheduling(int Mod_idP,
continue;
}
NR_CellGroupConfig_t *CellGroup = UE->CellGroup;
NR_UE_BWP_t *BWP = &UE->current_BWP;
NR_UE_DL_BWP_t *BWP = &UE->current_DL_BWP;
if (!CellGroup || !CellGroup->spCellConfig || !CellGroup->spCellConfig->spCellConfigDedicated ||
!CellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig) continue;
@@ -2759,20 +2783,20 @@ void nr_csirs_scheduling(int Mod_idP,
nfapi_nr_dl_tti_csi_rs_pdu_rel15_t *csirs_pdu_rel15 = &dl_tti_csirs_pdu->csi_rs_pdu.csi_rs_pdu_rel15;
csirs_pdu_rel15->subcarrier_spacing = BWP->dl_scs;
if (BWP->dl_cyclicprefix)
csirs_pdu_rel15->cyclic_prefix = *BWP->dl_cyclicprefix;
csirs_pdu_rel15->subcarrier_spacing = BWP->scs;
if (BWP->cyclicprefix)
csirs_pdu_rel15->cyclic_prefix = *BWP->cyclicprefix;
else
csirs_pdu_rel15->cyclic_prefix = 0;
// According to last paragraph of TS 38.214 5.2.2.3.1
if (resourceMapping.freqBand.startingRB < BWP->dl_BWPStart) {
csirs_pdu_rel15->start_rb = BWP->dl_BWPStart;
if (resourceMapping.freqBand.startingRB < BWP->BWPStart) {
csirs_pdu_rel15->start_rb = BWP->BWPStart;
} else {
csirs_pdu_rel15->start_rb = resourceMapping.freqBand.startingRB;
}
if (resourceMapping.freqBand.nrofRBs > (BWP->dl_BWPStart + BWP->dl_BWPSize - csirs_pdu_rel15->start_rb)) {
csirs_pdu_rel15->nr_of_rbs = BWP->dl_BWPStart + BWP->dl_BWPSize - csirs_pdu_rel15->start_rb;
if (resourceMapping.freqBand.nrofRBs > (BWP->BWPStart + BWP->BWPSize - csirs_pdu_rel15->start_rb)) {
csirs_pdu_rel15->nr_of_rbs = BWP->BWPStart + BWP->BWPSize - csirs_pdu_rel15->start_rb;
} else {
csirs_pdu_rel15->nr_of_rbs = resourceMapping.freqBand.nrofRBs;
}
@@ -2956,8 +2980,7 @@ void nr_mac_update_timers(module_id_t module_id,
LOG_I(NR_MAC,"Modified rnti %04x with CellGroup\n", UE->rnti);
process_CellGroup(cg,&UE->UE_sched_ctrl);
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
// re-configure BWP information
NR_UE_BWP_t *BWP = &UE->current_BWP;
const NR_PDSCH_ServingCellConfig_t *pdsch = spCellConfigDedicated ? spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup : NULL;
if (get_softmodem_params()->sa) {
@@ -2969,12 +2992,12 @@ void nr_mac_update_timers(module_id_t module_id,
if (spCellConfigDedicated->uplinkConfig &&
spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList) {
sched_ctrl->active_ubwp = spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[*spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id - 1];
if (*spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id != BWP->ul_bwp_id) {
if (*spCellConfigDedicated->uplinkConfig->firstActiveUplinkBWP_Id != UE->current_UL_BWP.bwp_id) {
LOG_I(NR_MAC, "Changing to UL-BWP %li\n", sched_ctrl->active_ubwp->bwp_Id);
}
}
configure_UE_BWP(RC.nrmac[module_id], BWP, scc, sched_ctrl, NULL, UE->CellGroup);
configure_UE_BWP(RC.nrmac[module_id], scc, sched_ctrl, NULL, UE);
// Update coreset/searchspace
@@ -2991,20 +3014,7 @@ void nr_mac_update_timers(module_id_t module_id,
const uint8_t layers = set_dl_nrOfLayers(sched_ctrl);
const int tda = get_dl_tda(RC.nrmac[module_id], scc, slot);
// Update downlink MCS table
if (BWP->pdsch_Config &&
BWP->pdsch_Config->mcs_Table) {
if (*BWP->pdsch_Config->mcs_Table == 0) {
ps->mcsTableIdx = 1;
} else {
ps->mcsTableIdx = 2;
}
} else {
ps->mcsTableIdx = 0;
}
LOG_D(NR_MAC,"MCS Table Index: %d\n",ps->mcsTableIdx);
nr_set_pdsch_semi_static(BWP,
nr_set_pdsch_semi_static(&UE->current_DL_BWP,
scc,
cg,
tda,
@@ -3055,14 +3065,15 @@ void schedule_nr_bwp_switch(module_id_t module_id,
UE_iterator(UE_info->list, UE) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_BWP_t *BWP = &UE->current_BWP;
NR_UE_DL_BWP_t *DLBWP = &UE->current_DL_BWP;
NR_UE_UL_BWP_t *ULBWP = &UE->current_UL_BWP;
if (sched_ctrl->rrc_processing_timer == 0 &&
UE->Msg4_ACKed &&
((sched_ctrl->next_dl_bwp_id >= 0 && BWP->dl_bwp_id != sched_ctrl->next_dl_bwp_id) ||
(sched_ctrl->next_ul_bwp_id >= 0 && BWP->ul_bwp_id != sched_ctrl->next_ul_bwp_id))) {
((sched_ctrl->next_dl_bwp_id >= 0 && DLBWP->bwp_id != sched_ctrl->next_dl_bwp_id) ||
(sched_ctrl->next_ul_bwp_id >= 0 && ULBWP->bwp_id != sched_ctrl->next_ul_bwp_id))) {
LOG_W(NR_MAC,"%4d.%2d UE %04x Schedule BWP switch from dl_bwp_id %ld to %ld and from ul_bwp_id %ld to %ld\n",
frame, slot, UE->rnti, BWP->dl_bwp_id, sched_ctrl->next_dl_bwp_id, BWP->ul_bwp_id, sched_ctrl->next_ul_bwp_id);
frame, slot, UE->rnti, DLBWP->bwp_id, sched_ctrl->next_dl_bwp_id, ULBWP->bwp_id, sched_ctrl->next_ul_bwp_id);
nr_mac_rrc_bwp_switch_req(module_id, frame, slot, UE->rnti, sched_ctrl->next_dl_bwp_id, sched_ctrl->next_ul_bwp_id);
}
}
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_srs.c
+6 -6
View File
@@ -36,13 +36,13 @@ extern RAN_CONTEXT_t RC;
void nr_configure_srs(nfapi_nr_srs_pdu_t *srs_pdu, int module_id, int CC_id,NR_UE_info_t* UE, NR_SRS_Resource_t *srs_resource) {
NR_UE_BWP_t *current_BWP = &UE->current_BWP;
NR_UE_UL_BWP_t *current_BWP = &UE->current_UL_BWP;
srs_pdu->rnti = UE->rnti;
srs_pdu->handle = 0;
srs_pdu->bwp_size = current_BWP->ul_BWPSize;
srs_pdu->bwp_start = current_BWP->ul_BWPStart;
srs_pdu->subcarrier_spacing = current_BWP->ul_scs;
srs_pdu->bwp_size = current_BWP->BWPSize;
srs_pdu->bwp_start = current_BWP->BWPStart;
srs_pdu->subcarrier_spacing = current_BWP->scs;
srs_pdu->cyclic_prefix = 0;
srs_pdu->num_ant_ports = srs_resource->nrofSRS_Ports;
srs_pdu->num_symbols = srs_resource->resourceMapping.nrofSymbols;
@@ -110,7 +110,7 @@ void nr_schedule_srs(int module_id, frame_t frame) {
const int CC_id = 0;
NR_CellGroupConfig_t *cg = UE->CellGroup;
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_BWP_t *current_BWP = &UE->current_BWP;
NR_UE_UL_BWP_t *current_BWP = &UE->current_UL_BWP;
sched_ctrl->sched_srs.frame = -1;
sched_ctrl->sched_srs.slot = -1;
@@ -160,7 +160,7 @@ void nr_schedule_srs(int module_id, frame_t frame) {
uint16_t period = srs_period[srs_resource->resourceType.choice.periodic->periodicityAndOffset_p.present];
uint16_t offset = get_nr_srs_offset(srs_resource->resourceType.choice.periodic->periodicityAndOffset_p);
int n_slots_frame = nr_slots_per_frame[current_BWP->ul_scs];
int n_slots_frame = nr_slots_per_frame[current_BWP->scs];
// Check if UE will transmit the SRS in this frame
if ( ((frame - offset/n_slots_frame)*n_slots_frame)%period == 0) {
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c
+23 -20
View File
@@ -698,8 +698,8 @@ void nr_csi_meas_reporting(int Mod_idP,
UE_iterator(RC.nrmac[Mod_idP]->UE_info.list, UE ) {
const NR_CellGroupConfig_t *CellGroup = UE->CellGroup;
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_BWP_t *BWP = &UE->current_BWP;
const int n_slots_frame = nr_slots_per_frame[BWP->ul_scs];
NR_UE_UL_BWP_t *UL_BWP = &UE->current_UL_BWP;
const int n_slots_frame = nr_slots_per_frame[UL_BWP->scs];
if ((sched_ctrl->rrc_processing_timer > 0) || (sched_ctrl->ul_failure==1 && get_softmodem_params()->phy_test==0)) {
continue;
}
@@ -758,7 +758,7 @@ void nr_csi_meas_reporting(int Mod_idP,
curr_pucch->resource_indicator = res_index;
curr_pucch->csi_bits += nr_get_csi_bitlen(UE,csi_report_id);
int bwp_start = BWP->ul_BWPStart;
int bwp_start = UL_BWP->BWPStart;
// going through the list of PUCCH resources to find the one indexed by resource_id
uint16_t *vrb_map_UL = &RC.nrmac[Mod_idP]->common_channels[0].vrb_map_UL[sched_slot * MAX_BWP_SIZE];
@@ -834,7 +834,7 @@ static void handle_dl_harq(NR_UE_info_t * UE,
int checkTargetSSBInFirst64TCIStates_pdschConfig(int ssb_index_t, NR_UE_info_t * UE) {
const NR_PDSCH_Config_t *pdsch_Config = UE->current_BWP.pdsch_Config;
const NR_PDSCH_Config_t *pdsch_Config = UE->current_DL_BWP.pdsch_Config;
int nb_tci_states = pdsch_Config ? pdsch_Config->tci_StatesToAddModList->list.count : 0;
NR_TCI_State_t *tci =NULL;
@@ -866,7 +866,7 @@ int checkTargetSSBInTCIStates_pdcchConfig(int ssb_index_t, NR_UE_info_t *UE) {
NR_ControlResourceSet_t *coreset = sched_ctrl->coreset;
int flag = 0;
int tci_stateID = -1;
const NR_PDSCH_Config_t *pdsch_Config = UE->current_BWP.pdsch_Config;
const NR_PDSCH_Config_t *pdsch_Config = UE->current_DL_BWP.pdsch_Config;
int nb_tci_states = pdsch_Config ? pdsch_Config->tci_StatesToAddModList->list.count : 0;
for(int i=0; i<nb_tci_states && i<128; i++) {
tci = (NR_TCI_State_t *)pdsch_Config->tci_StatesToAddModList->list.array[i];
@@ -929,7 +929,7 @@ void tci_handling(NR_UE_info_t *UE, frame_t frame, slot_t slot) {
int ssb_index[MAX_NUM_SSB] = {0};
int ssb_rsrp[MAX_NUM_SSB] = {0};
uint8_t idx = 0;
NR_UE_BWP_t *BWP = &UE->current_BWP;
NR_UE_DL_BWP_t *BWP = &UE->current_DL_BWP;
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
uint8_t nr_ssbri_cri = 0;
@@ -940,7 +940,7 @@ void tci_handling(NR_UE_info_t *UE, frame_t frame, slot_t slot) {
//bwp indicator
int n_dl_bwp = BWP->n_dl_bwp;
const int bwp_id = BWP->dl_bwp_id;
const int bwp_id = BWP->bwp_id;
if (n_dl_bwp < 4)
pdsch_bwp_id = bwp_id;
else
@@ -1203,9 +1203,12 @@ void evaluate_cqi_report(uint8_t *payload,
nr_csi_report_t *csi_report,
int cumul_bits,
uint8_t ri,
NR_UE_sched_ctrl_t *sched_ctrl,
NR_UE_info_t *UE,
long *cqi_Table){
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_DL_BWP_t *BWP = &UE->current_DL_BWP;
//TODO sub-band CQI report not yet implemented
int cqi_bitlen = csi_report->csi_meas_bitlen.cqi_bitlen[ri];
@@ -1228,7 +1231,7 @@ void evaluate_cqi_report(uint8_t *payload,
// TODO for wideband case and multiple TB
const int cqi_idx = sched_ctrl->CSI_report.cri_ri_li_pmi_cqi_report.wb_cqi_1tb;
const int mcs_table = sched_ctrl->pdsch_semi_static.mcsTableIdx;
const int mcs_table = BWP->mcsTableIdx;
const int cqi_table = sched_ctrl->CSI_report.cri_ri_li_pmi_cqi_report.cqi_table;
sched_ctrl->dl_max_mcs = get_mcs_from_cqi(mcs_table, cqi_table, cqi_idx);
}
@@ -1307,8 +1310,8 @@ void extract_pucch_csi_report(NR_CSI_MeasConfig_t *csi_MeasConfig,
uint16_t bitlen = uci_pdu->csi_part1.csi_part1_bit_len;
NR_CSI_ReportConfig__reportQuantity_PR reportQuantity_type = NR_CSI_ReportConfig__reportQuantity_PR_NOTHING;
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_BWP_t *BWP = &UE->current_BWP;
const int n_slots_frame = nr_slots_per_frame[BWP->ul_scs];
NR_UE_UL_BWP_t *BWP = &UE->current_UL_BWP;
const int n_slots_frame = nr_slots_per_frame[BWP->scs];
int cumul_bits = 0;
int r_index = -1;
for (int csi_report_id = 0; csi_report_id < csi_MeasConfig->csi_ReportConfigToAddModList->list.count; csi_report_id++ ) {
@@ -1343,7 +1346,7 @@ void extract_pucch_csi_report(NR_CSI_MeasConfig_t *csi_MeasConfig,
cumul_bits += ri_bitlen;
if (r_index != -1)
skip_zero_padding(&cumul_bits,csi_report,r_index,bitlen);
evaluate_cqi_report(payload,csi_report,cumul_bits,r_index,sched_ctrl,csirep->cqi_Table);
evaluate_cqi_report(payload,csi_report,cumul_bits,r_index,UE,csirep->cqi_Table);
break;
case NR_CSI_ReportConfig__reportQuantity_PR_cri_RI_PMI_CQI:
cri_bitlen = csi_report->csi_meas_bitlen.cri_bitlen;
@@ -1359,7 +1362,7 @@ void extract_pucch_csi_report(NR_CSI_MeasConfig_t *csi_MeasConfig,
pmi_bitlen = evaluate_pmi_report(payload,csi_report,cumul_bits,r_index,sched_ctrl);
sched_ctrl->CSI_report.cri_ri_li_pmi_cqi_report.csi_report_id = csi_report_id;
cumul_bits += pmi_bitlen;
evaluate_cqi_report(payload,csi_report,cumul_bits,r_index,sched_ctrl,csirep->cqi_Table);
evaluate_cqi_report(payload,csi_report,cumul_bits,r_index,UE,csirep->cqi_Table);
break;
case NR_CSI_ReportConfig__reportQuantity_PR_cri_RI_LI_PMI_CQI:
cri_bitlen = csi_report->csi_meas_bitlen.cri_bitlen;
@@ -1377,7 +1380,7 @@ void extract_pucch_csi_report(NR_CSI_MeasConfig_t *csi_MeasConfig,
pmi_bitlen = evaluate_pmi_report(payload,csi_report,cumul_bits,r_index,sched_ctrl);
sched_ctrl->CSI_report.cri_ri_li_pmi_cqi_report.csi_report_id = csi_report_id;
cumul_bits += pmi_bitlen;
evaluate_cqi_report(payload,csi_report,cumul_bits,r_index,sched_ctrl,csirep->cqi_Table);
evaluate_cqi_report(payload,csi_report,cumul_bits,r_index,UE,csirep->cqi_Table);
break;
default:
AssertFatal(1==0, "Invalid or not supported CSI measurement report\n");
@@ -1598,8 +1601,8 @@ int nr_acknack_scheduling(int mod_id,
const int CC_id = 0;
const int minfbtime = RC.nrmac[mod_id]->minRXTXTIMEpdsch;
const NR_ServingCellConfigCommon_t *scc = RC.nrmac[mod_id]->common_channels[CC_id].ServingCellConfigCommon;
NR_UE_BWP_t *BWP = &UE->current_BWP;
const int n_slots_frame = nr_slots_per_frame[BWP->ul_scs];
NR_UE_UL_BWP_t *BWP = &UE->current_UL_BWP;
const int n_slots_frame = nr_slots_per_frame[BWP->scs];
const NR_TDD_UL_DL_Pattern_t *tdd = scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL;
AssertFatal(tdd || RC.nrmac[mod_id]->common_channels[CC_id].frame_type == FDD, "Dynamic TDD not handled yet\n");
const int nr_slots_period = tdd ? n_slots_frame / get_nb_periods_per_frame(tdd->dl_UL_TransmissionPeriodicity) : n_slots_frame;
@@ -1627,8 +1630,8 @@ int nr_acknack_scheduling(int mod_id,
pucch_Config = cg->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP->pucch_Config->choice.setup;
}
int bwp_start = BWP->ul_BWPStart;
int bwp_size = BWP->ul_BWPSize;
int bwp_start = BWP->BWPStart;
int bwp_size = BWP->BWPSize;
NR_sched_pucch_t *pucch = &sched_ctrl->sched_pucch[0];
LOG_D(NR_MAC, "In %s: %4d.%2d Trying to allocate pucch, current DAI %d\n", __FUNCTION__, frame, slot, pucch->dai_c);
@@ -1875,8 +1878,8 @@ void nr_sr_reporting(gNB_MAC_INST *nrmac, frame_t SFN, sub_frame_t slot)
UE_iterator(nrmac->UE_info.list, UE) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_BWP_t *BWP = &UE->current_BWP;
const int n_slots_frame = nr_slots_per_frame[BWP->ul_scs];
NR_UE_UL_BWP_t *BWP = &UE->current_UL_BWP;
const int n_slots_frame = nr_slots_per_frame[BWP->scs];
if (sched_ctrl->ul_failure==1) continue;
NR_PUCCH_Config_t *pucch_Config = NULL;
if (sched_ctrl->active_ubwp) {
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
+16 -16
View File
@@ -847,7 +847,7 @@ static bool allocate_ul_retransmission(gNB_MAC_INST *nrmac,
cg->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP : NULL;
int rbStart = 0; // wrt BWP start
const uint16_t bwpSize = UE->current_BWP.ul_BWPSize;
const uint16_t bwpSize = UE->current_UL_BWP.BWPSize;
const uint8_t nrOfLayers = 1;
const uint8_t num_dmrs_cdm_grps_no_data = (sched_ctrl->active_ubwp || ubwpd) ? 1 : 2;
LOG_D(NR_MAC,"retInfo->time_domain_allocation = %d, tda = %d\n", retInfo->time_domain_allocation, tda);
@@ -1037,7 +1037,7 @@ void pf_ul(module_id_t module_id,
LOG_D(NR_MAC,"pf_ul: preparing UL scheduling for UE %04x\n",UE->rnti);
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_BWP_t *BWP = &UE->current_BWP;
NR_UE_UL_BWP_t *BWP = &UE->current_UL_BWP;
int rbStart = 0; // wrt BWP start
NR_CellGroupConfig_t *cg = UE->CellGroup;
@@ -1045,7 +1045,7 @@ void pf_ul(module_id_t module_id,
cg->spCellConfig->spCellConfigDedicated->uplinkConfig ?
cg->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP : NULL;
const uint16_t bwpSize = BWP->ul_BWPSize;
const uint16_t bwpSize = BWP->BWPSize;
NR_sched_pusch_t *sched_pusch = &sched_ctrl->sched_pusch;
NR_pusch_semi_static_t *ps = &sched_ctrl->pusch_semi_static;
const NR_mac_dir_stats_t *stats = &UE->mac_stats.ul;
@@ -1235,15 +1235,15 @@ void pf_ul(module_id_t module_id,
}
else LOG_D(NR_MAC, "%4d.%2d free CCE for UL DCI UE %04x\n",frame,slot, iterator->UE->rnti);
NR_UE_BWP_t *BWP = &iterator->UE->current_BWP;
NR_UE_UL_BWP_t *BWP = &iterator->UE->current_UL_BWP;
NR_CellGroupConfig_t *cg = iterator->UE->CellGroup;
NR_BWP_UplinkDedicated_t *ubwpd = cg && cg->spCellConfig && cg->spCellConfig->spCellConfigDedicated
&& cg->spCellConfig->spCellConfigDedicated->uplinkConfig ?
cg->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP : NULL;
int rbStart = sched_ctrl->active_ubwp ? BWP->ul_BWPStart : 0;
const uint16_t bwpSize = BWP->ul_BWPSize;
int rbStart = sched_ctrl->active_ubwp ? BWP->BWPStart : 0;
const uint16_t bwpSize = BWP->BWPSize;
NR_sched_pusch_t *sched_pusch = &sched_ctrl->sched_pusch;
NR_pusch_semi_static_t *ps = &sched_ctrl->pusch_semi_static;
@@ -1347,8 +1347,8 @@ bool nr_fr1_ulsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
* TDAs yet). If the TDA is negative, it means that there is no UL slot to
* schedule now (slot + k2 is not UL slot) */
NR_UE_sched_ctrl_t *sched_ctrl = &nr_mac->UE_info.list[0]->UE_sched_ctrl;
NR_UE_BWP_t *BWP = &nr_mac->UE_info.list[0]->current_BWP;
int mu = BWP->ul_scs;
NR_UE_UL_BWP_t *BWP = &nr_mac->UE_info.list[0]->current_UL_BWP;
int mu = BWP->scs;
const int temp_tda = get_ul_tda(nr_mac, scc, slot);
int K2 = get_K2(scc, scc_sib1, sched_ctrl->active_ubwp, temp_tda, mu);
const int sched_frame = (frame + (slot + K2 >= nr_slots_per_frame[mu])) & 1023;
@@ -1398,8 +1398,8 @@ bool nr_fr1_ulsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
uint16_t *vrb_map_UL =
&RC.nrmac[module_id]->common_channels[CC_id].vrb_map_UL[sched_slot * MAX_BWP_SIZE];
const uint16_t bwpSize = BWP->ul_BWPSize;
const uint16_t bwpStart = BWP->ul_BWPStart;
const uint16_t bwpSize = BWP->BWPSize;
const uint16_t bwpStart = BWP->BWPStart;
NR_PUSCH_TimeDomainResourceAllocationList_t *tdaList = NULL;
if (sched_ctrl->active_ubwp) {
@@ -1511,7 +1511,7 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
if (sched_ctrl->ul_failure == 1 && get_softmodem_params()->phy_test==0) continue;
NR_CellGroupConfig_t *cg = UE->CellGroup;
NR_UE_BWP_t *current_BWP = &UE->current_BWP;
NR_UE_UL_BWP_t *current_BWP = &UE->current_UL_BWP;
NR_BWP_UplinkDedicated_t *ubwpd = cg && cg->spCellConfig && cg->spCellConfig->spCellConfigDedicated &&
cg->spCellConfig->spCellConfigDedicated->uplinkConfig ?
@@ -1642,9 +1642,9 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
/* FAPI: BWP */
pusch_pdu->bwp_size = current_BWP->ul_BWPSize;
pusch_pdu->bwp_start = current_BWP->ul_BWPStart;
pusch_pdu->subcarrier_spacing = current_BWP->ul_scs;
pusch_pdu->bwp_size = current_BWP->BWPSize;
pusch_pdu->bwp_start = current_BWP->BWPStart;
pusch_pdu->subcarrier_spacing = current_BWP->scs;
pusch_pdu->cyclic_prefix = 0;
/* FAPI: PUSCH information always included */
@@ -1806,13 +1806,13 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot)
current_BWP);
fill_dci_pdu_rel15(scc,
cg,
current_BWP,
&UE->current_DL_BWP,
dci_pdu,
&uldci_payload,
ps->dci_format,
rnti_types[0],
pusch_pdu->bwp_size,
current_BWP->ul_bwp_id,
current_BWP->bwp_id,
coresetid,
nr_mac->cset0_bwp_size);
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+5 -6
View File
@@ -201,7 +201,7 @@ void config_uldci(const NR_SIB1_t *sib1,
int time_domain_assignment,
uint8_t tpc,
int n_ubwp,
NR_UE_BWP_t *BWP);
NR_UE_UL_BWP_t *BWP);
void nr_schedule_pucch(gNB_MAC_INST* nrmac,
frame_t frameP,
@@ -297,7 +297,7 @@ void fill_pdcch_vrb_map(gNB_MAC_INST *mac,
void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
const NR_CellGroupConfig_t *CellGroup,
const NR_UE_BWP_t *BWP,
const NR_UE_DL_BWP_t *BWP,
nfapi_nr_dl_dci_pdu_t *pdcch_dci_pdu,
dci_pdu_rel15_t *dci_pdu_rel15,
int dci_formats,
@@ -308,7 +308,7 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
uint16_t cset0_bwp_size);
void prepare_dci(const NR_CellGroupConfig_t *CellGroup,
const NR_UE_BWP_t *BWP,
const NR_UE_DL_BWP_t *BWP,
dci_pdu_rel15_t *dci_pdu_rel15,
nr_dci_format_t format,
int bwp_id);
@@ -339,7 +339,7 @@ long get_K2(NR_ServingCellConfigCommon_t *scc,
int time_domain_assignment,
int mu);
void nr_set_pdsch_semi_static(const NR_UE_BWP_t *BWP,
void nr_set_pdsch_semi_static(const NR_UE_DL_BWP_t *BWP,
const NR_ServingCellConfigCommon_t *scc,
const NR_CellGroupConfig_t *secondaryCellGroup,
int tda,
@@ -391,11 +391,10 @@ NR_UE_info_t * find_nr_UE(NR_UEs_t* UEs, rnti_t rntiP);
int find_nr_RA_id(module_id_t mod_idP, int CC_idP, rnti_t rntiP);
void configure_UE_BWP(gNB_MAC_INST *nr_mac,
NR_UE_BWP_t *BWP,
NR_ServingCellConfigCommon_t *scc,
NR_UE_sched_ctrl_t *sched_ctrl,
NR_RA_t *ra,
NR_CellGroupConfig_t *CellGroup);
NR_UE_info_t *UE);
NR_UE_info_t* add_new_nr_ue(gNB_MAC_INST *nr_mac, rnti_t rntiP, NR_CellGroupConfig_t *CellGroup);
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+20 -15
View File
@@ -91,21 +91,25 @@ typedef struct {
int len;
} NR_list_t;
typedef struct NR_UE_BWP {
NR_BWP_Id_t dl_bwp_id;
NR_BWP_Id_t ul_bwp_id;
typedef struct NR_UE_DL_BWP {
NR_BWP_Id_t bwp_id;
int n_dl_bwp;
int dl_scs;
int ul_scs;
long *dl_cyclicprefix;
long *ul_cyclicprefix;
uint16_t dl_BWPSize;
uint16_t dl_BWPStart;
uint16_t ul_BWPSize;
uint16_t ul_BWPStart;
int scs;
long *cyclicprefix;
uint16_t BWPSize;
uint16_t BWPStart;
NR_PDSCH_TimeDomainResourceAllocationList_t *tdaList;
NR_PDSCH_Config_t *pdsch_Config;
} NR_UE_BWP_t;
uint8_t mcsTableIdx;
} NR_UE_DL_BWP_t;
typedef struct NR_UE_UL_BWP {
NR_BWP_Id_t bwp_id;
int scs;
long *cyclicprefix;
uint16_t BWPSize;
uint16_t BWPStart;
} NR_UE_UL_BWP_t;
typedef enum {
RA_IDLE = 0,
@@ -211,7 +215,8 @@ typedef struct {
/// CFRA flag
bool cfra;
// BWP for RA
NR_UE_BWP_t BWP;
NR_UE_DL_BWP_t DL_BWP;
NR_UE_UL_BWP_t UL_BWP;
} NR_RA_t;
/*! \brief gNB common channels */
@@ -422,7 +427,6 @@ typedef struct NR_pdsch_semi_static {
int startSymbolIndex;
int nrOfSymbols;
uint8_t nrOfLayers;
uint8_t mcsTableIdx;
uint8_t dmrs_ports_id;
uint8_t N_PRB_DMRS;
uint8_t N_DMRS_SLOT;
@@ -719,7 +723,8 @@ typedef struct {
/// scheduling control info
nr_csi_report_t csi_report_template[MAX_CSI_REPORTCONFIG];
NR_UE_sched_ctrl_t UE_sched_ctrl;
NR_UE_BWP_t current_BWP;
NR_UE_DL_BWP_t current_DL_BWP;
NR_UE_UL_BWP_t current_UL_BWP;
NR_mac_stats_t mac_stats;
NR_CellGroupConfig_t *CellGroup;
char cg_buf[32768]; /* arbitrary size */