fix tx_resume_ind_fifo messages sending bugs, rename associated function send_slot_ind() to what it actually does send_dl_done_to_tx_thread()
This commit is contained in:
+64
-29
@@ -494,7 +494,7 @@ static void UE_synch(void *arg) {
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static void RU_write(nr_rxtx_thread_data_t *rxtxD) {
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PHY_VARS_NR_UE *UE = rxtxD->UE;
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UE_nr_rxtx_proc_t *proc = &rxtxD->proc;
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const UE_nr_rxtx_proc_t *proc = &rxtxD->proc;
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void *txp[NB_ANTENNAS_TX];
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int slot = proc->nr_slot_tx;
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@@ -541,19 +541,48 @@ static void RU_write(nr_rxtx_thread_data_t *rxtxD) {
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void processSlotTX(void *arg) {
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nr_rxtx_thread_data_t *rxtxD = (nr_rxtx_thread_data_t *) arg;
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UE_nr_rxtx_proc_t *proc = &rxtxD->proc;
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const UE_nr_rxtx_proc_t *proc = &rxtxD->proc;
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PHY_VARS_NR_UE *UE = rxtxD->UE;
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nr_phy_data_tx_t phy_data = {0};
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LOG_D(PHY,"%d.%d => slot type %d\n", proc->frame_tx, proc->nr_slot_tx, proc->tx_slot_type);
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if (proc->tx_slot_type == NR_UPLINK_SLOT || proc->tx_slot_type == NR_MIXED_SLOT){
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if (rxtxD->tx_wait_for_dlsch)
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LOG_D(PHY, "enter wait for tx, slot %d, nb events to wait %d; ", proc->nr_slot_tx, rxtxD->tx_wait_for_dlsch);
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// wait for rx slots to send indication (if any) that DLSCH decoding is finished
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for(int i=0; i < rxtxD->tx_wait_for_dlsch; i++) {
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notifiedFIFO_elt_t *res = pullNotifiedFIFO(UE->tx_resume_ind_fifo[proc->nr_slot_tx]);
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notifiedFIFO_elt_t *res = pullNotifiedFIFO(UE->tx_resume_ind_fifo + proc->nr_slot_tx);
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delNotifiedFIFO_elt(res);
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}
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LOG_D(PHY, "completed wait for tx, slot %d\n", proc->nr_slot_tx);
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/*
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This herafter code is costing some perfomance for a check that should be useless
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But, we face today several bugs arround the matching between events in UE->tx_resume_ind_fifo[slot]
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and the corresponding tx_wait_for_dlsch[slot]
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The algorithm is we accumlate the actions that should end before processing a tx slot in tx_wait_for_dlsch[slot]
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later, other threads push events in UE->tx_resume_ind_fifo[slot]
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so, the tx encoding starts only when related actions are done (mainly DLSCH ACK/NACK to encode PUCCH)
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if there is a bug that misses to send a event in UE->tx_resume_ind_fifo[slot], the process hangs, we detect the issue
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if there is a bug that makes a extra event in UE->tx_resume_ind_fifo[slot], and if we drop the hereafter check
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the system runs with random race conditions, very hard to debug
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Likely we should later remove completly UE->tx_resume_ind_fifo with notifications,
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instead,
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we may run in place the processSlotTX() when the conditions are met (when a decreasing tx_wait_for_dlsch[slot] will become 0)
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It will remove the condition signals (for a thread safe semaphore or counter) and make the system simpler
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This require also other modifications to
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remove txFifo that is also a big issue
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add out of order RF board sending, because,
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if we encode and send tx slot as soon as we can,
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it will be thrown out of order, especially in TDD mode
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*/
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notifiedFIFO_elt_t *res = pollNotifiedFIFO(UE->tx_resume_ind_fifo + proc->nr_slot_tx);
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if (res)
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LOG_E(NR_PHY,
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"Internal error: extra event on Tx waiting queue for slot %d, event comes from rx slot %d\n",
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proc->nr_slot_tx,
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*(int *)NotifiedFifoData(res));
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// trigger L2 to run ue_scheduler thru IF module
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// [TODO] mapping right after NR initial sync
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if(UE->if_inst != NULL && UE->if_inst->ul_indication != NULL) {
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@@ -580,10 +609,8 @@ void processSlotTX(void *arg) {
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RU_write(rxtxD);
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}
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nr_phy_data_t UE_dl_preprocessing(PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc)
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static void UE_dl_preprocessing(PHY_VARS_NR_UE *UE, const UE_nr_rxtx_proc_t *proc, int *tx_wait_for_dlsch, nr_phy_data_t *phy_data)
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{
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nr_phy_data_t phy_data = {0};
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if (IS_SOFTMODEM_NOS1 || get_softmodem_params()->sa) {
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// Start synchronization with a target gNB
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@@ -607,23 +634,24 @@ nr_phy_data_t UE_dl_preprocessing(PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc)
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if(UE->if_inst != NULL && UE->if_inst->dl_indication != NULL) {
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nr_downlink_indication_t dl_indication;
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nr_fill_dl_indication(&dl_indication, NULL, NULL, proc, UE, &phy_data);
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nr_fill_dl_indication(&dl_indication, NULL, NULL, proc, UE, phy_data);
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UE->if_inst->dl_indication(&dl_indication);
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}
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uint64_t a=rdtsc_oai();
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pbch_pdcch_processing(UE, proc, &phy_data);
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if (phy_data.dlsch[0].active && phy_data.dlsch[0].rnti_type == TYPE_C_RNTI_) {
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pbch_pdcch_processing(UE, proc, phy_data);
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if (phy_data->dlsch[0].active && phy_data->dlsch[0].rnti_type == TYPE_C_RNTI_) {
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// indicate to tx thread to wait for DLSCH decoding
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const int ack_nack_slot = (proc->nr_slot_rx + phy_data.dlsch[0].dlsch_config.k1_feedback) % UE->frame_parms.slots_per_frame;
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UE->tx_wait_for_dlsch[ack_nack_slot]++;
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const int ack_nack_slot = (proc->nr_slot_rx + phy_data->dlsch[0].dlsch_config.k1_feedback) % UE->frame_parms.slots_per_frame;
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LOG_D(NR_PHY, "Adding one event to wait after decoding slot %d, for futre tx slot %d\n", proc->nr_slot_rx, ack_nack_slot);
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tx_wait_for_dlsch[ack_nack_slot]++;
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}
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LOG_D(PHY, "In %s: slot %d, time %llu\n", __FUNCTION__, proc->nr_slot_rx, (rdtsc_oai()-a)/3500);
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}
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ue_ta_procedures(UE, proc->nr_slot_tx, proc->frame_tx);
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return phy_data;
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return;
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}
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void UE_dl_processing(void *arg) {
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@@ -764,12 +792,11 @@ void *UE_thread(void *arg)
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const int nb_slot_frame = UE->frame_parms.slots_per_frame;
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int absolute_slot=0, decoded_frame_rx=INT_MAX, trashed_frames=0;
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initNotifiedFIFO(&UE->phy_config_ind);
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int tx_wait_for_dlsch[NR_MAX_SLOTS_PER_FRAME];
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int num_ind_fifo = nb_slot_frame;
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for(int i=0; i < num_ind_fifo; i++) {
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UE->tx_wait_for_dlsch[num_ind_fifo] = 0;
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UE->tx_resume_ind_fifo[i] = malloc(sizeof(*UE->tx_resume_ind_fifo[i]));
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initNotifiedFIFO(UE->tx_resume_ind_fifo[i]);
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initNotifiedFIFO(UE->tx_resume_ind_fifo + i);
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}
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while (!oai_exit) {
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@@ -836,6 +863,13 @@ void *UE_thread(void *arg)
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decoded_frame_rx++;
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// we do ++ first in the regular processing, so it will be begin of frame;
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absolute_slot = decoded_frame_rx * nb_slot_frame - 1;
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// We have resynchronized, maybe after RF loss so we need to purge any existing context
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memset(tx_wait_for_dlsch, 0, sizeof(tx_wait_for_dlsch));
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for (int i = 0; i < num_ind_fifo; i++) {
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notifiedFIFO_elt_t *res;
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while ((res = pollNotifiedFIFO(UE->tx_resume_ind_fifo + i)))
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delNotifiedFIFO_elt(res);
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}
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continue;
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}
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@@ -913,26 +947,27 @@ void *UE_thread(void *arg)
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if (curMsg.proc.nr_slot_tx == 0)
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nr_ue_rrc_timer_trigger(UE->Mod_id, curMsg.proc.frame_tx, curMsg.proc.gNB_id);
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// RX slot processing. We launch and forget.
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notifiedFIFO_elt_t *newRx = newNotifiedFIFO_elt(sizeof(nr_rxtx_thread_data_t), curMsg.proc.nr_slot_rx, NULL, UE_dl_processing);
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nr_rxtx_thread_data_t *curMsgRx = (nr_rxtx_thread_data_t *)NotifiedFifoData(newRx);
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*curMsgRx = (nr_rxtx_thread_data_t){.proc = curMsg.proc, .UE = UE};
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UE_dl_preprocessing(UE, &curMsgRx->proc, tx_wait_for_dlsch, &curMsgRx->phy_data);
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pushTpool(&(get_nrUE_params()->Tpool), newRx);
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// Start TX slot processing here. It runs in parallel with RX slot processing
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notifiedFIFO_elt_t *newElt = newNotifiedFIFO_elt(sizeof(nr_rxtx_thread_data_t), curMsg.proc.nr_slot_tx, &txFifo, processSlotTX);
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nr_rxtx_thread_data_t *curMsgTx = (nr_rxtx_thread_data_t *) NotifiedFifoData(newElt);
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// in current code, DURATION_RX_TO_TX constant is the limit to get UL data to encode from a RX slot
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notifiedFIFO_elt_t *newTx = newNotifiedFIFO_elt(sizeof(nr_rxtx_thread_data_t), curMsg.proc.nr_slot_tx, &txFifo, processSlotTX);
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nr_rxtx_thread_data_t *curMsgTx = (nr_rxtx_thread_data_t *)NotifiedFifoData(newTx);
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curMsgTx->proc = curMsg.proc;
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curMsgTx->writeBlockSize = writeBlockSize;
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curMsgTx->proc.timestamp_tx = writeTimestamp;
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curMsgTx->UE = UE;
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curMsgTx->tx_wait_for_dlsch = UE->tx_wait_for_dlsch[curMsgTx->proc.nr_slot_tx];
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UE->tx_wait_for_dlsch[curMsgTx->proc.nr_slot_tx] = 0;
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pushTpool(&(get_nrUE_params()->Tpool), newElt);
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// RX slot processing. We launch and forget.
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newElt = newNotifiedFIFO_elt(sizeof(nr_rxtx_thread_data_t), curMsg.proc.nr_slot_rx, NULL, UE_dl_processing);
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nr_rxtx_thread_data_t *curMsgRx = (nr_rxtx_thread_data_t *) NotifiedFifoData(newElt);
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curMsgRx->proc = curMsg.proc;
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curMsgRx->UE = UE;
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curMsgRx->phy_data = UE_dl_preprocessing(UE, &curMsg.proc);
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pushTpool(&(get_nrUE_params()->Tpool), newElt);
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curMsgTx->tx_wait_for_dlsch = tx_wait_for_dlsch[curMsgTx->proc.nr_slot_tx];
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tx_wait_for_dlsch[curMsgTx->proc.nr_slot_tx] = 0;
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pushTpool(&(get_nrUE_params()->Tpool), newTx);
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// Wait for TX slot processing to finish
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// Should be removed when bugs, race conditions, will be fixed
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notifiedFIFO_elt_t *res;
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res = pullTpool(&txFifo, &(get_nrUE_params()->Tpool));
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if (res == NULL)
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@@ -426,7 +426,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
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rdata->offset = offset;
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rdata->dlsch = dlsch;
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rdata->dlsch_id = 0;
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rdata->proc = proc;
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rdata->proc = *proc;
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reset_meas(&rdata->ts_deinterleave);
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reset_meas(&rdata->ts_rate_unmatch);
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reset_meas(&rdata->ts_ldpc_decode);
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@@ -613,8 +613,7 @@ typedef struct {
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void *phy_sim_pdsch_dl_ch_estimates_ext;
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uint8_t *phy_sim_dlsch_b;
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notifiedFIFO_t phy_config_ind;
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notifiedFIFO_t *tx_resume_ind_fifo[NR_MAX_SLOTS_PER_FRAME];
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int tx_wait_for_dlsch[NR_MAX_SLOTS_PER_FRAME];
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notifiedFIFO_t tx_resume_ind_fifo[NR_MAX_SLOTS_PER_FRAME];
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} PHY_VARS_NR_UE;
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typedef struct {
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@@ -649,7 +648,6 @@ typedef struct nr_rxtx_thread_data_s {
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UE_nr_rxtx_proc_t proc;
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PHY_VARS_NR_UE *UE;
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int writeBlockSize;
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notifiedFIFO_t txFifo;
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nr_phy_data_t phy_data;
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int tx_wait_for_dlsch;
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} nr_rxtx_thread_data_t;
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@@ -677,7 +675,7 @@ typedef struct LDPCDecode_ue_s {
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time_stats_t ts_deinterleave;
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time_stats_t ts_rate_unmatch;
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time_stats_t ts_ldpc_decode;
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UE_nr_rxtx_proc_t *proc;
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UE_nr_rxtx_proc_t proc;
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} ldpcDecode_ue_t;
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#include "SIMULATION/ETH_TRANSPORT/defs.h"
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@@ -488,20 +488,17 @@ int nr_ue_pdcch_procedures(PHY_VARS_NR_UE *ue,
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return(dci_cnt);
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}
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int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue,
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UE_nr_rxtx_proc_t *proc,
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NR_UE_DLSCH_t dlsch[2],
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int16_t *llr[2],
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c16_t rxdataF[][ue->frame_parms.samples_per_slot_wCP])
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static int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue,
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const UE_nr_rxtx_proc_t *proc,
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NR_UE_DLSCH_t dlsch[2],
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int16_t *llr[2],
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c16_t rxdataF[][ue->frame_parms.samples_per_slot_wCP])
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{
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int frame_rx = proc->frame_rx;
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int nr_slot_rx = proc->nr_slot_rx;
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int m;
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int first_symbol_flag=0;
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if (!dlsch[0].active)
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return 0;
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// We handle only one CW now
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if (!(NR_MAX_NB_LAYERS>4)) {
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NR_UE_DLSCH_t *dlsch0 = &dlsch[0];
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@@ -637,23 +634,23 @@ int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue,
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return 0;
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}
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void send_slot_ind(notifiedFIFO_t *nf, int slot) {
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// This function release the Tx working thread for one pending information, like dlsch ACK/NACK
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static void send_dl_done_to_tx_thread(notifiedFIFO_t *nf, int rx_slot)
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{
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if (nf) {
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notifiedFIFO_elt_t *newElt = newNotifiedFIFO_elt(sizeof(int), 0, NULL, NULL);
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// We put rx slot only for tracing purpose
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int *msgData = (int *) NotifiedFifoData(newElt);
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*msgData = slot;
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*msgData = rx_slot;
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pushNotifiedFIFO(nf, newElt);
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}
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}
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bool nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
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UE_nr_rxtx_proc_t *proc,
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NR_UE_DLSCH_t dlsch[2],
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int16_t* llr[2]) {
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static bool nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue, const UE_nr_rxtx_proc_t *proc, NR_UE_DLSCH_t dlsch[2], int16_t *llr[2])
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{
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if (dlsch[0].active == false) {
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LOG_E(PHY, "DLSCH should be active when calling this function\n");
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return 1;
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return true;
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}
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int gNB_id = proc->gNB_id;
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@@ -688,8 +685,9 @@ bool nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
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// exit dlsch procedures as there are no active dlsch
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if (is_cw0_active != ACTIVE && is_cw1_active != ACTIVE) {
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// don't wait anymore
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LOG_E(NR_PHY, "Internal error nr_ue_dlsch_procedure() called but no active cw on slot %d, harq %d\n", nr_slot_rx, harq_pid);
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const int ack_nack_slot = (proc->nr_slot_rx + dlsch[0].dlsch_config.k1_feedback) % ue->frame_parms.slots_per_frame;
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send_slot_ind(ue->tx_resume_ind_fifo[ack_nack_slot], proc->nr_slot_rx);
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send_dl_done_to_tx_thread(ue->tx_resume_ind_fifo + ack_nack_slot, proc->nr_slot_rx);
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return false;
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}
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@@ -821,7 +819,7 @@ bool nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
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LOG_D(PHY, "AbsSubframe %d.%d --> ldpc Decoding for CW1 %5.3f\n",
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frame_rx%1024, nr_slot_rx,(ue->dlsch_decoding_stats.p_time)/(cpuf*1000.0));
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}
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LOG_D(PHY, "harq_pid: %d, TBS expected dlsch1: %d \n", harq_pid, dlsch[1].dlsch_config.TBS);
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LOG_D(PHY, "harq_pid: %d, TBS expected dlsch1: %d \n", harq_pid, dlsch[1].dlsch_config.TBS);
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}
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// send to mac
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@@ -829,8 +827,11 @@ bool nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
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ue->if_inst->dl_indication(&dl_indication);
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}
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const int ack_nack_slot = (proc->nr_slot_rx + dlsch[0].dlsch_config.k1_feedback) % ue->frame_parms.slots_per_frame;
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send_slot_ind(ue->tx_resume_ind_fifo[ack_nack_slot], proc->nr_slot_rx);
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// DLSCH decoding finished! don't wait anymore in Tx process, we know if we should answer ACK/NACK PUCCH
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if (dlsch[0].rnti_type == TYPE_C_RNTI_) {
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const int ack_nack_slot = (proc->nr_slot_rx + dlsch[0].dlsch_config.k1_feedback) % ue->frame_parms.slots_per_frame;
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send_dl_done_to_tx_thread(ue->tx_resume_ind_fifo + ack_nack_slot, proc->nr_slot_rx);
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}
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if (ue->phy_sim_dlsch_b)
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memcpy(ue->phy_sim_dlsch_b, p_b, dlsch_bytes);
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@@ -1097,9 +1098,12 @@ void pdsch_processing(PHY_VARS_NR_UE *ue, const UE_nr_rxtx_proc_t *proc, nr_phy_
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if (ret_pdsch >= 0)
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nr_ue_dlsch_procedures(ue, proc, dlsch, llr);
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else
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// don't wait anymore
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send_slot_ind(ue->tx_resume_ind_fifo[(proc->nr_slot_rx + dlsch_config->k1_feedback) % ue->frame_parms.slots_per_frame], proc->nr_slot_rx);
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else {
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LOG_E(NR_PHY, "Demodulation impossible, internal error\n");
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send_dl_done_to_tx_thread(
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ue->tx_resume_ind_fifo + (proc->nr_slot_rx + dlsch_config->k1_feedback) % ue->frame_parms.slots_per_frame,
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proc->nr_slot_rx);
|
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}
|
||||
|
||||
stop_meas(&ue->dlsch_procedures_stat);
|
||||
if (cpumeas(CPUMEAS_GETSTATE)) {
|
||||
|
||||
Reference in New Issue
Block a user