static bitmap to schedule dl slots (also to test phone)
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@@ -377,7 +377,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0)
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nr_ulmix_slots++;
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if ((slot_txP == 0) && (UE_list->fiveG_connected[UE_id] || get_softmodem_params()->phy_test)) {
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if (slot_txP== 0 && (UE_list->fiveG_connected[UE_id] || get_softmodem_params()->phy_test)) {
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for (int k=0; k<nr_ulmix_slots; k++) {
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memset((void *) &UE_list->UE_sched_ctrl[UE_id].sched_pucch[k],
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0,
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@@ -394,25 +394,23 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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RC.nrmac[module_idP]->frame = frame_rxP;
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RC.nrmac[module_idP]->slot = slot_rxP;
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if (get_softmodem_params()->phy_test) {
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dlsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch
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ulsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].ulsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains ulsch
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dlsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch
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ulsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].ulsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains ulsch
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// hardcoding dlsch to be in slot 1
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if (!(slot_txP%num_slots_per_tdd)) {
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if(slot_txP==0)
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*dlsch_in_slot_bitmap = 0x02;
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else
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*dlsch_in_slot_bitmap = 0x00;
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}
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// hardcoding dlsch to be in slot 1
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if (!(slot_txP%num_slots_per_tdd)) {
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if(slot_txP==0)
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*dlsch_in_slot_bitmap = 0x7e;
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else
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*dlsch_in_slot_bitmap = 0x00;
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}
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// hardcoding ulsch to be in slot 8
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if (!(slot_rxP%num_slots_per_tdd)) {
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if(slot_rxP==0)
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*ulsch_in_slot_bitmap = 0x100;
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else
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*ulsch_in_slot_bitmap = 0x00;
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}
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// hardcoding ulsch to be in slot 8
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if (!(slot_rxP%num_slots_per_tdd)) {
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if(slot_rxP==0)
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*ulsch_in_slot_bitmap = 0x100;
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else
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*ulsch_in_slot_bitmap = 0x00;
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}
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// Check if there are downlink symbols in the slot,
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@@ -464,9 +462,11 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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if (get_softmodem_params()->phy_test == 0)
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nr_schedule_RA(module_idP, frame_txP, slot_txP);
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else
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UE_list->fiveG_connected[UE_id] = true;
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// Phytest scheduling
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if (get_softmodem_params()->phy_test && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot_txP%num_slots_per_tdd))) {
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if (UE_list->fiveG_connected[UE_id] && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot_txP%num_slots_per_tdd))) {
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ue_sched_ctl->current_harq_pid = slot_txP % num_slots_per_tdd;
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nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,&pucch_sched);
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nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched], NULL);
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@@ -474,16 +474,6 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
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gNB->ta_len = 0;
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}
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// Test DL scheduling
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if (get_softmodem_params()->phy_test == 0 && slot_txP>0 && slot_txP<7 && UE_list->fiveG_connected[UE_id]) {
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ue_sched_ctl->current_harq_pid = slot_txP % num_slots_per_tdd;
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nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,&pucch_sched);
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nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched], NULL);
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// resetting ta flag
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gNB->ta_len = 0;
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}
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/*
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// Allocate CCEs for good after scheduling is done
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for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++)
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