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Fix: smooth ULSCH AMC and TPC control.

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(cherry picked from commit 56720c68864f6b04409deb00676e59a41c8f050b)
This commit is contained in:
Haruki NAOI
2020-11-27 10:07:56 +09:00
committed by shono.takafumi
parent b573fd4dbd
commit 52dfba49cd
9 changed files with 39 additions and 50 deletions
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openair1/SCHED/phy_procedures_lte_eNb.c
+4
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@@ -1606,6 +1606,10 @@ void fill_rx_indication(PHY_VARS_eNB *eNB,
pdu->rx_indication_rel8.timing_advance = timing_advance_update;
// estimate UL_CQI for MAC (from antenna port 0 only)
int SNRtimes10 = dB_fixed_times10(eNB->pusch_vars[UE_id]->ulsch_power[0]) - dB_fixed_times10(eNB->pusch_vars[UE_id]->ulsch_interference_power[0]);
if(dB_fixed_times10(eNB->pusch_vars[UE_id]->ulsch_power[0]) > 500) {
SNRtimes10 = 300;
}
if (SNRtimes10 < -640)
pdu->rx_indication_rel8.ul_cqi = 0;
openair2/LAYER2/MAC/defs.h
+1 -1
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@@ -834,9 +834,9 @@ typedef struct {
uint8_t pucch2_snr[NFAPI_CC_MAX];
uint8_t pucch3_cqi_update[NFAPI_CC_MAX];
uint8_t pucch3_snr[NFAPI_CC_MAX];
uint8_t pusch_cqi[NFAPI_CC_MAX];
uint8_t pusch_snr[NFAPI_CC_MAX];
uint8_t pusch_snr_avg[NFAPI_CC_MAX];
uint8_t pusch_snr_amc[NFAPI_CC_MAX];
uint64_t pusch_rx_num[NFAPI_CC_MAX];
uint64_t pusch_rx_num_old[NFAPI_CC_MAX];
uint64_t pusch_rx_error_num[NFAPI_CC_MAX];
openair2/LAYER2/MAC/eNB_scheduler.c
+2 -2
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@@ -601,8 +601,8 @@ eNB_dlsch_ulsch_scheduler(module_id_t module_idP,
UE_scheduling_control->ul_out_of_sync == 0 ? "in synch" : "out of sync",
UE_info->UE_template[CC_id][UE_id].phr_info,
UE_scheduling_control->dl_cqi[CC_id],
(5 * UE_scheduling_control->pusch_snr_avg[CC_id] - 640) / 10,
(5 * UE_scheduling_control->pucch1_snr[CC_id] - 640) / 10);
UE_scheduling_control->pusch_snr_avg[CC_id],
UE_scheduling_control->pucch1_snr[CC_id]);
}
RC.eNB[module_idP][CC_id]->pusch_stats_bsr[UE_id][(frameP * 10) + subframeP] = -63;
openair2/LAYER2/MAC/eNB_scheduler_dlsch.c
+2 -2
View File
@@ -1050,7 +1050,7 @@ schedule_ue_spec(module_id_t module_idP,
// this is the snr
// unit is not dBm, it's special from nfapi
// converting to dBm
int snr = (5 * ue_sched_ctrl->pucch1_snr[CC_id] - 640) / 10;
int snr = ue_sched_ctrl->pucch1_snr[CC_id];
int target_snr = eNB->puCch10xSnr / 10;
// this assumes accumulated tpc
// make sure that we are only sending a tpc update once a frame, otherwise the control loop will freak out
@@ -1684,7 +1684,7 @@ schedule_ue_spec_br(module_id_t module_idP,
/* Do PUCCH power control */
/* This is the snr */
/* unit is not dBm, it's special from nfapi, convert to dBm */
snr = (5 * ue_sched_ctl->pucch1_snr[CC_id] - 640) / 10;
snr = ue_sched_ctl->pucch1_snr[CC_id];
target_snr = mac->puCch10xSnr / 10;
/* This assumes accumulated tpc */
/* Make sure that we are only sending a tpc update once a frame, otherwise the control loop will freak out */
openair2/LAYER2/MAC/eNB_scheduler_fairRR.c
+14 -24
View File
@@ -1998,8 +1998,8 @@ schedule_ue_spec_fairRR(module_id_t module_idP,
// this is the snr
eNB_UE_stats = &UE_info->eNB_UE_stats[CC_id][UE_id];
/* Unit is not dBm, it's special from nfapi */
snr = (5 * ue_sched_ctl->pucch1_snr[CC_id] - 640) / 10;
target_snr = eNB->puCch10xSnr / 10;
snr = ue_sched_ctl->pucch1_snr[CC_id];
target_snr = eNB->puCch10xSnr/10;
// this assumes accumulated tpc
// make sure that we are only sending a tpc update once a frame, otherwise the control loop will freak out
int32_t framex10psubframe = UE_info->UE_template[CC_id][UE_id].pucch_tpc_tx_frame*10+UE_info->UE_template[CC_id][UE_id].pucch_tpc_tx_subframe;
@@ -2669,7 +2669,7 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP,
UE_template = &UE_info->UE_template[CC_id][UE_id];
int32_t framex10psubframe = UE_template->pusch_bler_calc_frame*10+UE_template->pusch_bler_calc_subframe;
int pusch_bler_interval=100;
int pusch_bler_interval=50;
double total_bler;
if(UE_info->UE_sched_ctrl[UE_id].pusch_rx_num[CC_id] == 0 && UE_info->UE_sched_ctrl[UE_id].pusch_rx_error_num[CC_id] == 0) {
@@ -2711,21 +2711,11 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP,
}
}
if ( UE_info->UE_sched_ctrl[UE_id].phr_received == 1 ) {
snr = (5 * UE_info->UE_sched_ctrl[UE_id].pusch_snr_amc[CC_id] - 640) / 10;
mcs = snr - snr2mcs_offset;
if(mcs > 20) {
mcs = 20;
}
if(mcs - UE_info->UE_sched_ctrl[UE_id].mcs_offset[CC_id] < 6) {
mcs = 6;
}
else {
mcs = mcs - UE_list->UE_sched_ctrl[UE_id].mcs_offset[CC_id];
}
} else {
mcs = 10;
snr = UE_info->UE_sched_ctrl[UE_id].pusch_snr_avg[CC_id];
mcs = 20 - UE_info->UE_sched_ctrl[UE_id].mcs_offset[CC_id];
if(mcs < 6) {
mcs = 6;
}
if ( ulsch_ue_select[CC_id].list[ulsch_ue_num].ue_priority == SCH_UL_FIRST ) {
@@ -2773,9 +2763,9 @@ void ulsch_scheduler_pre_processor_fairRR(module_id_t module_idP,
UE_info->UE_template[CC_id][UE_id].pre_assigned_mcs_ul = mcs;
}
LOG_D(MAC,"[eNB %d] frame %d subframe %d, UE %d/%x CC %d snr %d mcs %d mcs_offset %d bler %lf total_bler %lf ( %d %d ) rb_num %d phr_info %d tx_power %d bsr %d\n",
module_idP,frameP,subframeP,UE_id,UE_RNTI(CC_id,UE_id),CC_id, snr, mcs, UE_list->UE_sched_ctrl[UE_id].mcs_offset[CC_id], UE_list->UE_sched_ctrl[UE_id].pusch_bler[CC_id],
total_bler, UE_list->UE_sched_ctrl[UE_id].pusch_rx_num[CC_id], UE_list->UE_sched_ctrl[UE_id].pusch_rx_error_num[CC_id], rb_table[rb_table_index-1], UE_template->phr_info, tx_power, bytes_to_schedule);
LOG_D(MAC,"[eNB %d] frame %d subframe %d, UE %d/%x CC %d snr %d snr_inst %d mcs %d mcs_offset %d bler %lf total_bler %lf ( %d %d ) rb_num %d phr_info %d tx_power %d bsr %d estimated_ul_buffer %d scheduled_ul_bytes %d\n",
module_idP,frameP,subframeP,UE_id,UE_RNTI(CC_id,UE_id),CC_id, snr, UE_list->UE_sched_ctrl[UE_id].pusch_snr[CC_id], mcs, UE_list->UE_sched_ctrl[UE_id].mcs_offset[CC_id], UE_list->UE_sched_ctrl[UE_id].pusch_bler[CC_id],
total_bler, UE_list->UE_sched_ctrl[UE_id].pusch_rx_num[CC_id], UE_list->UE_sched_ctrl[UE_id].pusch_rx_error_num[CC_id], rb_table[rb_table_index-1], UE_template->phr_info, tx_power, bytes_to_schedule, UE_template->estimated_ul_buffer, UE_template->scheduled_ul_bytes);
} else {
if (mac_eNB_get_rrc_status(module_idP,UE_RNTI(module_idP, UE_id)) < RRC_CONNECTED) {
@@ -3140,7 +3130,7 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP,
//power control
//compute the expected ULSCH RX power (for the stats)
// this is the normalized RX power and this should be constant (regardless of mcs
snr = (5 * UE_sched_ctrl->pusch_snr_avg[CC_id] - 640) / 10;
snr = UE_sched_ctrl->pusch_snr_avg[CC_id];
target_snr = eNB->puSch10xSnr / 10;
// this assumes accumulated tpc
// make sure that we are only sending a tpc update once a frame, otherwise the control loop will freak out
@@ -3265,7 +3255,7 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP,
nfapi_hi_dci0_req->sfn_sf = frameP<<4|subframeP; // sfnsf_add_subframe(sched_frame, sched_subframeP, 0); // sunday!
nfapi_hi_dci0_req->header.message_id = NFAPI_HI_DCI0_REQUEST;
LOG_D(MAC,"[PUSCH %d] Frame %d, Subframe %d: Adding UL CONFIG.Request for UE %d/%x, ulsch_frame %d, ulsch_subframe %d mcs %d first_rb %d num_rb %d round %d mcs %d sinr %d bler %lf\n",
harq_pid,frameP,subframeP,UE_id,rnti,sched_frame,sched_subframeP,UE_template->mcs_UL[harq_pid],first_rb[CC_id],rb_table[rb_table_index],0,UE_template->mcs_UL[harq_pid],(5 * UE_sched_ctrl->pusch_snr_amc[CC_id] - 640) / 10,UE_sched_ctrl->pusch_bler[CC_id]);
harq_pid,frameP,subframeP,UE_id,rnti,sched_frame,sched_subframeP,UE_template->mcs_UL[harq_pid],first_rb[CC_id],rb_table[rb_table_index],0,UE_template->mcs_UL[harq_pid],UE_sched_ctrl->pusch_snr_avg[CC_id],UE_sched_ctrl->pusch_bler[CC_id]);
ul_req_index = 0;
dlsch_flag = 0;
@@ -3415,7 +3405,7 @@ void schedule_ulsch_rnti_fairRR(module_id_t module_idP,
hi_dci0_req->number_of_dci++;
// Add UL_config PDUs
LOG_D(MAC,"[PUSCH %d] Frame %d, Subframe %d: Adding UL CONFIG.Request for UE %d/%x, ulsch_frame %d, ulsch_subframe %d mcs %d first_rb %d num_rb %d round %d mcs %d sinr %d bler %lf\n",
harq_pid,frameP,subframeP,UE_id,rnti,sched_frame,sched_subframeP,mcs_rv,ulsch_ue_select[CC_id].list[ulsch_ue_num].start_rb,ulsch_ue_select[CC_id].list[ulsch_ue_num].nb_rb,UE_sched_ctrl->round_UL[CC_id][harq_pid],UE_template->mcs_UL[harq_pid],(5 * UE_sched_ctrl->pusch_snr_amc[CC_id] - 640) / 10,UE_sched_ctrl->pusch_bler[CC_id]);
harq_pid,frameP,subframeP,UE_id,rnti,sched_frame,sched_subframeP,mcs_rv,ulsch_ue_select[CC_id].list[ulsch_ue_num].start_rb,ulsch_ue_select[CC_id].list[ulsch_ue_num].nb_rb,UE_sched_ctrl->round_UL[CC_id][harq_pid],UE_template->mcs_UL[harq_pid],UE_sched_ctrl->pusch_snr_avg[CC_id],UE_sched_ctrl->pusch_bler[CC_id]);
ul_req_index = 0;
dlsch_flag = 0;
openair2/LAYER2/MAC/eNB_scheduler_phytest.c
+2 -1
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@@ -238,7 +238,8 @@ void schedule_ulsch_phy_test(module_id_t module_idP,frame_t frameP,sub_frame_t s
//power control
//compute the expected ULSCH RX power (for the stats)
// this is the snr and this should be constant (regardless of mcs)
snr = (5 * UE_sched_ctrl->pusch_snr[CC_id] - 640) / 10;
snr = UE_sched_ctrl->pusch_snr[CC_id];
// new transmission
ndi = 1-UE_template->oldNDI_UL[harq_pid];
UE_template->oldNDI_UL[harq_pid]=ndi;
openair2/LAYER2/MAC/eNB_scheduler_primitives.c
+3 -3
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@@ -2217,8 +2217,8 @@ add_new_ue(module_id_t mod_idP,
UE_info->UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer = 0;
UE_info->UE_sched_ctrl[UE_id].ta_update = 31;
UE_info->UE_sched_ctrl[UE_id].pusch_snr[cc_idP] = 0;
UE_info->UE_sched_ctrl[UE_id].pusch_snr_avg[cc_idP] = 0;
UE_info->UE_sched_ctrl[UE_id].pusch_snr_amc[cc_idP] = 0;
UE_info->UE_sched_ctrl[UE_id].pusch_cqi[cc_idP] = (eNB->puSch10xSnr+640)/5;
UE_info->UE_sched_ctrl[UE_id].pusch_snr_avg[cc_idP] = eNB->puSch10xSnr/10;
UE_info->UE_sched_ctrl[UE_id].pusch_rx_num[cc_idP] = 0;
UE_info->UE_sched_ctrl[UE_id].pusch_rx_num_old[cc_idP] = 0;
UE_info->UE_sched_ctrl[UE_id].pusch_rx_error_num[cc_idP] = 0;
@@ -5173,7 +5173,7 @@ harq_indication(module_id_t mod_idP,
/* don't care about cqi reporting if NACK/DTX is there */
if (channel == 0 && !nack_or_dtx_reported(cc,
harq_pdu)) {
sched_ctl->pucch1_snr[CC_idP] = ul_cqi;
sched_ctl->pucch1_snr[CC_idP] = (5 * ul_cqi - 640) / 10;
sched_ctl->pucch1_cqi_update[CC_idP] = 1;
}
openair2/LAYER2/MAC/eNB_scheduler_ulsch.c
+10 -16
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@@ -168,22 +168,16 @@ rx_sdu(const module_id_t enb_mod_idP,
* maybe it's even not correct at all?
*/
UE_scheduling_control->ta_update = (UE_scheduling_control->ta_update * 3 + timing_advance) / 4;
UE_scheduling_control->pusch_snr[CC_idP] = ul_cqi;
UE_scheduling_control->pusch_snr[CC_idP] = (5 * ul_cqi - 640) / 10;
double snr_filter_tpc=0.75;
if(UE_scheduling_control->pusch_snr_avg[CC_idP] == 0) {
UE_scheduling_control->pusch_snr_avg[CC_idP] = ul_cqi;
}
else {
UE_scheduling_control->pusch_snr_avg[CC_idP] = (int)((double)UE_scheduling_control->pusch_snr_avg[CC_idP] * snr_filter_tpc + (double)ul_cqi * (1-snr_filter_tpc));
}
double snr_filter_amc=0.5;
if(UE_scheduling_control->pusch_snr_amc[CC_idP] == 0) {
UE_scheduling_control->pusch_snr_amc[CC_idP] = ul_cqi;
}
else {
UE_scheduling_control->pusch_snr_amc[CC_idP] = (int)((double)UE_scheduling_control->pusch_snr_amc[CC_idP] * snr_filter_amc + (double)ul_cqi * (1-snr_filter_amc));
if(UE_scheduling_control->pusch_snr[CC_idP] > 0 || UE_scheduling_control->pusch_snr[CC_idP] < 63) {
double snr_filter_tpc=0.9;
int snr_thres_tpc=30;
int diff = UE_scheduling_control->pusch_snr_avg[CC_idP] - UE_scheduling_control->pusch_snr[CC_idP];
if(abs(diff) < snr_thres_tpc) {
UE_scheduling_control->pusch_cqi[CC_idP] = (int)((double)UE_scheduling_control->pusch_cqi[CC_idP] * snr_filter_tpc + (double)ul_cqi * (1-snr_filter_tpc));
UE_scheduling_control->pusch_snr_avg[CC_idP] = (5 * UE_scheduling_control->pusch_cqi[CC_idP] - 640) / 10;
}
}
UE_scheduling_control->ul_consecutive_errors = 0;
@@ -2013,7 +2007,7 @@ void schedule_ulsch_rnti_emtc(module_id_t module_idP,
cqi_req = 0;
/* Power control: compute the expected ULSCH RX snr (for the stats) */
/* This is the normalized snr and this should be constant (regardless of mcs) */
snr = (5 * UE_sched_ctrl->pusch_snr_avg[CC_id] - 640) / 10;
snr = UE_sched_ctrl->pusch_snr_avg[CC_id];
target_snr = eNB->puSch10xSnr / 10; /* TODO: target_rx_power was 178, what to put? */
/* This assumes accumulated tpc */
/* Make sure that we are only sending a tpc update once a frame, otherwise the control loop will freak out */
openair2/LAYER2/MAC/mac.h
+1 -1
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@@ -965,9 +965,9 @@ typedef struct {
uint8_t pucch2_snr[NFAPI_CC_MAX];
uint8_t pucch3_cqi_update[NFAPI_CC_MAX];
uint8_t pucch3_snr[NFAPI_CC_MAX];
uint8_t pusch_cqi[NFAPI_CC_MAX];
uint8_t pusch_snr[NFAPI_CC_MAX];
uint8_t pusch_snr_avg[NFAPI_CC_MAX];
uint8_t pusch_snr_amc[NFAPI_CC_MAX];
uint64_t pusch_rx_num[NFAPI_CC_MAX];
uint64_t pusch_rx_num_old[NFAPI_CC_MAX];
uint64_t pusch_rx_error_num[NFAPI_CC_MAX];