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scheduling of PUCCH on MAC, passing PUCCH FAPI down to PHY (to be finished), filling DCI structures according to PUCCH (to be finished)

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This commit is contained in:
Francesco Mani
2020-02-05 18:05:18 +01:00
parent b1d259663e
commit 5320469402
7 changed files with 176 additions and 39 deletions
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openair1/SCHED_NR/phy_procedures_nr_gNB.c
+8 -7
View File
@@ -347,15 +347,13 @@ void phy_procedures_gNB_common_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx)
void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx) {
nfapi_nr_ul_tti_request_t *UL_tti_req = &gNB->UL_tti_req;
int num_pusch_pdu = UL_tti_req->n_pdus;
int num_pdus = UL_tti_req->n_pdus;
LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d, num_pusch_pdu %d\n",frame_rx,slot_rx,num_pusch_pdu);
LOG_D(PHY,"phy_procedures_gNB_uespec_RX frame %d, slot %d, num_pdus %d\n",frame_rx,slot_rx,num_pdus);
for (int i = 0; i < num_pusch_pdu; i++) {
for (int i = 0; i < num_pdus; i++) {
switch (UL_tti_req->pdus_list[i].pdu_type) {
case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE:
{
case NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE:
LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE\n",frame_rx,slot_rx);
nfapi_nr_pusch_pdu_t *pusch_pdu = &UL_tti_req->pdus_list[0].pusch_pdu;
@@ -373,7 +371,10 @@ void phy_procedures_gNB_uespec_RX(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx)
//LOG_M("rxdataF_ext.m","rxF_ext",gNB->pusch_vars[0]->rxdataF_ext[0],6900,1,1);
nr_ulsch_procedures(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid);
nr_fill_rx_indication(gNB, frame_rx, slot_rx, ULSCH_id, harq_pid); // indicate SDU to MAC
}
break;
case NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE:
LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE\n",frame_rx,slot_rx);
break;
}
}
}
openair2/LAYER2/NR_MAC_gNB/config.c
-3
View File
@@ -50,7 +50,6 @@ extern RAN_CONTEXT_t RC;
//extern int l2_init_gNB(void);
extern void mac_top_init_gNB(void);
extern uint8_t nfapi_mode;
uint8_t nr_slots_per_frame[5] = {10, 20, 40, 80, 160};
void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigCommon_t *scc) {
@@ -281,8 +280,6 @@ void config_common(int Mod_idP, int pdsch_AntennaPorts, NR_ServingCellConfigComm
else LOG_I(PHY,"TDD has been properly configurated\n");
}
RC.nrmac[Mod_idP]->common_channels[0].num_slots_per_tdd = (nr_slots_per_frame[*scc->ssbSubcarrierSpacing])>>(7-cfg->tdd_table.tdd_period.value);
/*
// PDCCH-ConfigCommon
cfg->pdcch_config.controlResourceSetZero.value = scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->controlResourceSetZero;
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
+73 -9
View File
@@ -70,6 +70,8 @@ extern uint8_t nfapi_mode;
uint16_t nr_pdcch_order_table[6] = { 31, 31, 511, 2047, 2047, 8191 };
uint8_t nr_slots_per_frame[5] = {10, 20, 40, 80, 160};
void clear_nr_nfapi_information(gNB_MAC_INST * gNB,
int CC_idP,
frame_t frameP,
@@ -308,6 +310,61 @@ void copy_nr_ulreq(module_id_t module_idP, frame_t frameP, sub_frame_t slotP)
}
*/
void nr_schedule_pucch(int Mod_idP,
int UE_id,
frame_t frameP,
sub_frame_t slotP) {
uint16_t O_uci;
uint16_t O_ack;
uint8_t SR_flag = 0; // no SR in PUCCH implemented for now
uint8_t pucch_resource = 0; // in PHY test only one UE -> only one PUCCH resource used
NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels->ServingCellConfigCommon;
NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list;
AssertFatal(UE_list->active[UE_id] >=0,"Cannot find UE_id %d is not active\n",UE_id);
NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id];
int bwp_id=1;
NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1];
nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0];
NR_sched_pucch *curr_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch;
NR_sched_pucch *temp_pucch;
int release_pucch = 0;
if (curr_pucch != NULL) {
if ((frameP == curr_pucch->frame) && (slotP == curr_pucch->ul_slot)) {
UL_tti_req->SFN = frameP;
UL_tti_req->Slot = slotP;
UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE;
UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pucch_pdu_t);
nfapi_nr_pucch_pdu_t *pucch_pdu = &UL_tti_req->pdus_list[UL_tti_req->n_pdus].pucch_pdu;
memset(pucch_pdu,0,sizeof(nfapi_nr_pucch_pdu_t));
UL_tti_req->n_pdus+=1;
O_ack = curr_pucch->dai_c;
O_uci = O_ack; // for now we are just sending acknacks in pucch
nr_configure_pucch(pucch_pdu,
scc,
ubwp,
pucch_resource,
O_uci,
O_ack,
SR_flag);
release_pucch = 1;
}
}
if (release_pucch) {
temp_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch;
UE_list->UE_sched_ctrl[UE_id].sched_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch->next_sched_pucch;
free(temp_pucch);
}
}
bool is_xlsch_in_slot(uint64_t bitmap, sub_frame_t slot){
if((bitmap>>slot)&0x01)
@@ -329,10 +386,13 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
int UE_id;
uint64_t *dlsch_in_slot_bitmap=NULL;
uint64_t *ulsch_in_slot_bitmap=NULL;
NR_sched_pucch *pucch_sched = (NR_sched_pucch*) malloc(sizeof(NR_sched_pucch));
if (phy_test) UE_id=0;
NR_COMMON_channels_t *cc = RC.nrmac[module_idP]->common_channels;
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
int num_slots_per_tdd = (nr_slots_per_frame[*scc->ssbSubcarrierSpacing])>>(7-scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity);
//nfapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config = NULL;
@@ -346,11 +406,11 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
RC.nrmac[module_idP]->slot = slot_rxP;
if (phy_test) {
dlsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.dlsch_in_slot_bitmap[UE_id]; // static bitmap signaling which slot in a tdd period contains dlsch
ulsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.ulsch_in_slot_bitmap[UE_id]; // static bitmap signaling which slot in a tdd period contains ulsch
dlsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch
ulsch_in_slot_bitmap = &RC.nrmac[module_idP]->UE_list.UE_sched_ctrl[UE_id].ulsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains ulsch
// hardcoding dlsch to be in slot 1
if (!(slot_txP%cc->num_slots_per_tdd)) {
if (!(slot_txP%num_slots_per_tdd)) {
if(slot_txP==0)
*dlsch_in_slot_bitmap = 0x02;
else
@@ -358,7 +418,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
}
// hardcoding ulsch to be in slot 8
if (!(slot_rxP%cc->num_slots_per_tdd)) {
if (!(slot_rxP%num_slots_per_tdd)) {
if(slot_rxP==0)
*ulsch_in_slot_bitmap = 0x100;
else
@@ -403,8 +463,9 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
}
// Phytest scheduling
if (phy_test && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot_txP%cc->num_slots_per_tdd))) {
nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP,NULL);
if (phy_test && (is_xlsch_in_slot(*dlsch_in_slot_bitmap,slot_txP%num_slots_per_tdd))) {
nr_update_pucch_scheduling(module_idP, UE_id, frame_txP, slot_txP, num_slots_per_tdd,pucch_sched);
nr_schedule_uss_dlsch_phytest(module_idP, frame_txP, slot_txP, pucch_sched, NULL);
}
/*
@@ -416,8 +477,11 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
} //is_nr_DL_slot
if (is_nr_UL_slot(cc->ServingCellConfigCommon,slot_rxP)) {
if (phy_test && (is_xlsch_in_slot(*ulsch_in_slot_bitmap,slot_rxP%cc->num_slots_per_tdd))){
nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP);
if (phy_test) {
nr_schedule_pucch(module_idP, UE_id, frame_rxP, slot_rxP);
if (is_xlsch_in_slot(*ulsch_in_slot_bitmap,slot_rxP%num_slots_per_tdd)){
nr_schedule_uss_ulsch_phytest(module_idP, frame_rxP, slot_rxP);
}
}
}
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
+12 -10
View File
@@ -247,9 +247,11 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
}
int configure_fapi_dl_Tx(int Mod_idP,
sub_frame_t slotP,
int *CCEIndex,
nfapi_nr_dl_tti_request_body_t *dl_req,
nfapi_nr_pdu_t *TX_req,
NR_sched_pucch *pucch_sched,
uint8_t *mcsIndex,
uint16_t *rbSize,
uint16_t *rbStart) {
@@ -350,10 +352,10 @@ int configure_fapi_dl_Tx(int Mod_idP,
dci_pdu_rel15[0].ndi = 1;
dci_pdu_rel15[0].rv = 0;
dci_pdu_rel15[0].harq_pid = 0;
dci_pdu_rel15[0].dai = 2;
dci_pdu_rel15[0].dai = (pucch_sched->dai_c)&3;
dci_pdu_rel15[0].tpc = 2;
dci_pdu_rel15[0].pucch_resource_indicator = 7;
dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator = 7;
dci_pdu_rel15[0].pucch_resource_indicator = 7; //FIXME
dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator = pucch_sched->ul_slot - slotP; //FIXME put check on validity of indicator depending on type of DCI
LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n",
dci_pdu_rel15[0].frequency_domain_assignment,
@@ -373,9 +375,6 @@ int configure_fapi_dl_Tx(int Mod_idP,
scc,
bwp);
pdcch_pdu_rel15->numDlDci = 1;
pdcch_pdu_rel15->AggregationLevel[0] = 4;
pdcch_pdu_rel15->RNTI[0]=UE_list->rnti[0];
@@ -466,15 +465,16 @@ void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr
void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
frame_t frameP,
sub_frame_t slotP,
NR_sched_pucch *pucch_sched,
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *dlsch_config)
{
LOG_D(MAC, "In nr_schedule_uss_dlsch_phytest \n");
gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
//NR_COMMON_channels_t *cc = nr_mac->common_channels;
//NR_ServingCellConfigCommon_t *scc=cc->ServingCellConfigCommon;
nfapi_nr_dl_tti_request_body_t *dl_req;
nfapi_nr_pdu_t *TX_req;
nfapi_nr_pdu_t *TX_req;
int TBS;
int TBS_bytes;
@@ -630,9 +630,11 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
CCEIndices[0] = CCEIndex;
TBS_bytes = configure_fapi_dl_Tx(module_idP,
slotP,
CCEIndices,
dl_req,
TX_req,
pucch_sched,
dlsch_config!=NULL ? dlsch_config->mcsIndex : NULL,
dlsch_config!=NULL ? &dlsch_config->rbSize : NULL,
dlsch_config!=NULL ? &dlsch_config->rbStart : NULL);
@@ -670,7 +672,7 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
int CCEIndices[2];
CCEIndices[0] = CCEIndex;
LOG_D(MAC,"Configuring DL_TX in %d.%d\n",frameP,slotP);
TBS_bytes = configure_fapi_dl_Tx(module_idP,CCEIndices,dl_req, TX_req,
TBS_bytes = configure_fapi_dl_Tx(module_idP,slotP,CCEIndices,dl_req, TX_req, pucch_sched,
dlsch_config!=NULL ? dlsch_config->mcsIndex : NULL,
dlsch_config!=NULL ? &dlsch_config->rbSize : NULL,
dlsch_config!=NULL ? &dlsch_config->rbStart : NULL);
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+60 -2
View File
@@ -655,6 +655,8 @@ void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu,
if (pucchres->pucch_ResourceId == *resource_id) {
res_found = 1;
pucch_pdu->prb_start = pucchres->startingPRB;
// FIXME why there is only one frequency hopping flag
// what about inter slot frequency hopping?
pucch_pdu->freq_hop_flag = pucchres->intraSlotFrequencyHopping!= NULL ? 1 : 0;
pucch_pdu->second_hop_prb = pucchres->secondHopPRB!= NULL ? *pucchres->secondHopPRB : 0;
switch(pucchres->format.present) {
@@ -732,8 +734,7 @@ void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu,
void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
dci_pdu_rel15_t *dci_pdu_rel15,
int *dci_formats,
int *rnti_types
) {
int *rnti_types) {
uint16_t N_RB = pdcch_pdu_rel15->BWPSize;
uint8_t fsize=0, pos=0;
@@ -1245,6 +1246,63 @@ int add_new_nr_ue(module_id_t mod_idP,
return -1;
}
// function to update pucch scheduling parameters in UE list when a USS DL is scheduled
void nr_update_pucch_scheduling(int Mod_idP,
int UE_id,
frame_t frameP,
sub_frame_t slotP,
int slots_per_tdd,
NR_sched_pucch *sched_pucch) {
NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels->ServingCellConfigCommon;
NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list;
int first_ul_slot_tdd,next_slot;
NR_sched_pucch *curr_pucch;
// if the list of pucch to be scheduled is empty
if (UE_list->UE_sched_ctrl[UE_id].sched_pucch == NULL) {
sched_pucch->frame = frameP;
sched_pucch->next_sched_pucch = NULL;
sched_pucch->dai_c = 1;
if ( (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots!=0) || (scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols!=0)) {
// first pucch occasion in first UL or MIXED slot
first_ul_slot_tdd = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots;
// computing slot in which pucch is scheduled
sched_pucch->ul_slot = first_ul_slot_tdd + slotP - (slotP % slots_per_tdd);
}
else
AssertFatal(1==0,"No Uplink Slots in this Frame\n");
UE_list->UE_sched_ctrl[UE_id].sched_pucch = sched_pucch;
}
else {
curr_pucch = UE_list->UE_sched_ctrl[UE_id].sched_pucch;
while (curr_pucch->next_sched_pucch != NULL)
curr_pucch = curr_pucch->next_sched_pucch;
// we are scheduling at most 11 ack nacks in the same pucch
if (curr_pucch->dai_c==11) {
next_slot = curr_pucch->ul_slot + 1;
if (next_slot == slots_per_tdd)
AssertFatal(1==0,"No more slots in this TDD period\n");
else {
// generating a new item in the list
sched_pucch->frame = frameP;
sched_pucch->next_sched_pucch = NULL;
sched_pucch->dai_c = 1;
sched_pucch->ul_slot = next_slot;
curr_pucch->next_sched_pucch = (NR_sched_pucch*) malloc(sizeof(NR_sched_pucch));
curr_pucch->next_sched_pucch = sched_pucch;
}
}
else {
sched_pucch = curr_pucch;
sched_pucch->dai_c = 1 + sched_pucch->dai_c;
}
}
}
/*void fill_nfapi_coresets_and_searchspaces(NR_CellGroupConfig_t *cg,
nfapi_nr_coreset_t *coreset,
nfapi_nr_search_space_t *search_space) {
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+11 -2
View File
@@ -68,9 +68,11 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
sub_frame_t subframeP);
int configure_fapi_dl_Tx(int Mod_id,
sub_frame_t slotP,
int *CCEIndeces,
nfapi_nr_dl_tti_request_body_t *dl_req,
nfapi_nr_pdu_t *TX_req,
NR_sched_pucch *pucch_sched,
uint8_t *mcsIndex,
uint16_t *rbSize,
uint16_t *rbStart);
@@ -79,11 +81,19 @@ void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr
void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
frame_t frameP,
sub_frame_t slotP,
NR_sched_pucch *pucch_sched,
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_config);
void nr_schedule_uss_ulsch_phytest(int Mod_idP,
frame_t frameP,
sub_frame_t slotP);
void nr_update_pucch_scheduling(int Mod_idP,
int UE_id,
frame_t frameP,
sub_frame_t slotP,
int slots_per_tdd,
NR_sched_pucch *sched_pucch);
void nr_configure_css_dci_initial(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
nr_scs_e scs_common,
@@ -117,8 +127,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
dci_pdu_rel15_t *dci_pdu_rel15,
int *dci_formats,
int *rnti_types
);
int *rnti_types);
int get_spf(nfapi_nr_config_request_scf_t *cfg);
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+12 -6
View File
@@ -98,13 +98,21 @@ typedef struct {
uint8_t vrb_map_UL[100];
/// number of subframe allocation pattern available for MBSFN sync area
uint8_t num_sf_allocation_pattern;
/// number of slots per TDD period
uint8_t num_slots_per_tdd;
} NR_COMMON_channels_t;
/*! \brief scheduling control information set through an API (not used)*/
typedef struct NR_sched_pucch {
int frame;
int ul_slot;
uint8_t dai_c;
uint8_t dai_t;
struct NR_sched_pucch *next_sched_pucch;
} NR_sched_pucch;
/*! \brief scheduling control information set through an API */
typedef struct {
int dummy;
uint64_t dlsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains dlsch
uint64_t ulsch_in_slot_bitmap; // static bitmap signaling which slot in a tdd period contains ulsch
NR_sched_pucch *sched_pucch;
} NR_UE_sched_ctrl_t;
/*! \brief UE list used by eNB to order UEs/CC for scheduling*/
@@ -122,8 +130,6 @@ typedef struct {
boolean_t active[MAX_MOBILES_PER_GNB];
rnti_t rnti[MAX_MOBILES_PER_GNB];
NR_CellGroupConfig_t *secondaryCellGroup[MAX_MOBILES_PER_GNB];
uint64_t dlsch_in_slot_bitmap[MAX_MOBILES_PER_GNB]; // static bitmap signaling which slot in a tdd period contains dlsch
uint64_t ulsch_in_slot_bitmap[MAX_MOBILES_PER_GNB]; // static bitmap signaling which slot in a tdd period contains ulsch
} NR_UE_list_t;
/*! \brief top level gNB MAC structure */