New design UE scheduler
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+12
-20
@@ -431,32 +431,24 @@ void processSlotTX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
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void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
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nr_dcireq_t dcireq;
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nr_scheduled_response_t scheduled_response;
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fapi_nr_config_request_t *cfg = &UE->nrUE_config;
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int rx_slot_type = nr_ue_slot_select(cfg, proc->frame_rx, proc->nr_tti_rx);
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uint8_t ssb_period = UE->nrUE_config.ssb_table.ssb_period;
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uint8_t gNB_id = 0;
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nr_downlink_indication_t dl_indication;
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memset((void*)&dl_indication, 0, sizeof(dl_indication));
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//program DCI for slot 1
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//TODO: all of this has to be moved to the MAC!!!
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if (rx_slot_type == NR_DOWNLINK_SLOT || rx_slot_type == NR_MIXED_SLOT){
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dcireq.module_id = UE->Mod_id;
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dcireq.gNB_index = 0;
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dcireq.cc_id = 0;
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dcireq.frame = proc->frame_rx;
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dcireq.slot = proc->nr_tti_rx;
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nr_ue_dcireq(&dcireq); //to be replaced with function pointer later
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// we should have received a DL DCI here, so configure DL accordingly
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scheduled_response.dl_config = &dcireq.dl_config_req;
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scheduled_response.ul_config = NULL;
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scheduled_response.tx_request = NULL;
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scheduled_response.module_id = UE->Mod_id;
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scheduled_response.CC_id = 0;
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scheduled_response.frame = proc->frame_rx;
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scheduled_response.slot = proc->nr_tti_rx;
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if(UE->if_inst != NULL && UE->if_inst->dl_indication != NULL) {
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dl_indication.module_id = UE->Mod_id;
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dl_indication.gNB_index = gNB_id;
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dl_indication.cc_id = UE->CC_id;
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dl_indication.frame = proc->frame_rx;
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dl_indication.slot = proc->nr_tti_rx;
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}
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nr_ue_scheduled_response(&scheduled_response);
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nr_ue_scheduler(&dl_indication, NULL);
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// Process Rx data for one sub-frame
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#ifdef UE_SLOT_PARALLELISATION
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