Refactor inactivity-based PUSCH allocation
Write a single NR_sched_pusch_t structure in a single statement (where possible). Assign to sched_ctrl->sched_pusch in one place, where the post-processing functionality will be called in a follow-up commit.
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@@ -1879,7 +1879,6 @@ static void pf_ul(module_id_t module_id,
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LOG_D(NR_MAC,"pf_ul: preparing UL scheduling for UE %04x\n",UE->rnti);
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NR_UE_UL_BWP_t *current_BWP = &UE->current_UL_BWP;
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NR_sched_pusch_t *sched_pusch = &sched_ctrl->sched_pusch;
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const NR_mac_dir_stats_t *stats = &UE->mac_stats.ul;
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/* Calculate throughput */
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@@ -1995,29 +1994,21 @@ static void pf_ul(module_id_t module_id,
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continue;
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}
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sched_pusch->nrOfLayers = get_ul_nrOfLayers(sched_ctrl, current_BWP->dci_format);
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sched_pusch->time_domain_allocation = get_ul_tda(nrmac, sched_frame, sched_slot);
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sched_pusch->tda_info = get_ul_tda_info(current_BWP,
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int tda = get_ul_tda(nrmac, sched_frame, sched_slot);
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NR_tda_info_t tda_info = get_ul_tda_info(current_BWP,
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sched_ctrl->coreset->controlResourceSetId,
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sched_ctrl->search_space->searchSpaceType->present,
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TYPE_C_RNTI_,
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sched_pusch->time_domain_allocation);
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AssertFatal(sched_pusch->tda_info.valid_tda, "Invalid TDA from get_ul_tda_info\n");
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sched_pusch->dmrs_info = get_ul_dmrs_params(scc, current_BWP, &sched_pusch->tda_info, sched_pusch->nrOfLayers);
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tda);
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AssertFatal(tda_info.valid_tda, "Invalid TDA from get_ul_tda_info\n");
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int rbStart = 0; // wrt BWP start
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LOG_D(NR_MAC,
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"Looking for min_rb %d RBs, starting at %d num_dmrs_cdm_grps_no_data %d\n",
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min_rb,
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rbStart,
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sched_pusch->dmrs_info.num_dmrs_cdm_grps_no_data);
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bwp_info_t bwp_info = get_pusch_bwp_start_size(UE);
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const uint32_t bwpStart = bwp_info.bwpStart;
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const uint32_t bwpSize = bwp_info.bwpSize;
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const uint16_t slbitmap = SL_to_bitmap(sched_pusch->tda_info.startSymbolIndex, sched_pusch->tda_info.nrOfSymbols);
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while (rbStart < bwpSize && (rballoc_mask[rbStart + bwpStart] & slbitmap))
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LOG_D(NR_MAC, "Looking for min_rb %d RBs, starting at %d\n", min_rb, rbStart);
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bwp_info_t bi = get_pusch_bwp_start_size(UE);
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const uint16_t slbitmap = SL_to_bitmap(tda_info.startSymbolIndex, tda_info.nrOfSymbols);
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while (rbStart < bi.bwpSize && (rballoc_mask[rbStart + bi.bwpStart] & slbitmap))
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rbStart++;
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if (rbStart + min_rb > bwpSize) {
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if (rbStart + min_rb > bi.bwpSize) {
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LOG_D(NR_MAC,
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"[UE %04x][%4d.%2d] could not allocate continuous UL data: no resources (rbStart %d, min_rb %d, bwpSize %d)\n",
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UE->rnti,
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@@ -2025,7 +2016,7 @@ static void pf_ul(module_id_t module_id,
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slot,
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rbStart,
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min_rb,
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bwpSize);
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bi.bwpSize);
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reset_beam_status(&nrmac->beam_info, sched_frame, sched_slot, UE->UE_beam_index, slots_per_frame, beam.new_beam);
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reset_beam_status(&nrmac->beam_info, frame, slot, UE->UE_beam_index, slots_per_frame, dci_beam.new_beam);
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continue;
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@@ -2034,47 +2025,58 @@ static void pf_ul(module_id_t module_id,
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sched_ctrl->cce_index = CCEIndex;
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fill_pdcch_vrb_map(nrmac, CC_id, &sched_ctrl->sched_pdcch, CCEIndex, sched_ctrl->aggregation_level, dci_beam.idx);
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NR_sched_pusch_t *sched_pusch = &sched_ctrl->sched_pusch;
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sched_pusch->mcs = selected_mcs;
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update_ul_ue_R_Qm(sched_pusch->mcs, current_BWP->mcs_table, current_BWP->pusch_Config, &sched_pusch->R, &sched_pusch->Qm);
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sched_pusch->rbStart = rbStart;
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sched_pusch->rbSize = min_rb;
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sched_pusch->bwp_info = bwp_info;
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sched_pusch->frame = sched_frame;
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sched_pusch->slot = sched_slot;
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sched_pusch->ul_harq_pid = -1; // new transmission
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sched_pusch->tb_size = nr_compute_tbs(sched_pusch->Qm,
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sched_pusch->R,
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sched_pusch->rbSize,
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sched_pusch->tda_info.nrOfSymbols,
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sched_pusch->dmrs_info.N_PRB_DMRS * sched_pusch->dmrs_info.num_dmrs_symb,
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0, // nb_rb_oh
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0,
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sched_pusch->nrOfLayers) >> 3;
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int nrOfLayers = get_ul_nrOfLayers(sched_ctrl, current_BWP->dci_format);
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NR_sched_pusch_t sched = {
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.frame = sched_frame,
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.slot = sched_slot,
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.rbSize = min_rb,
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.rbStart = rbStart,
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.mcs = selected_mcs,
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// R, Qm, tb_size below
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.ul_harq_pid = -1, // new transmission
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.nrOfLayers = nrOfLayers,
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// tpmi in post-process
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.time_domain_allocation = tda,
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.tda_info = tda_info,
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.dmrs_info = get_ul_dmrs_params(scc, current_BWP, &tda_info, nrOfLayers),
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.bwp_info = bi,
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// phr_txpower_calc below
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};
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update_ul_ue_R_Qm(sched.mcs, current_BWP->mcs_table, current_BWP->pusch_Config, &sched.R, &sched.Qm);
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sched.tb_size = nr_compute_tbs(sched.Qm,
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sched.R,
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sched.rbSize,
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sched.tda_info.nrOfSymbols,
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sched.dmrs_info.N_PRB_DMRS * sched.dmrs_info.num_dmrs_symb,
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0, // nb_rb_oh
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0,
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sched.nrOfLayers)
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>> 3;
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long *deltaMCS = current_BWP->pusch_Config ? current_BWP->pusch_Config->pusch_PowerControl->deltaMCS : NULL;
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sched_pusch->phr_txpower_calc = compute_ph_factor(current_BWP->scs,
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sched_pusch->tb_size << 3,
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sched_pusch->rbSize,
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sched_pusch->nrOfLayers,
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sched_pusch->tda_info.nrOfSymbols,
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sched_pusch->dmrs_info.N_PRB_DMRS * sched_pusch->dmrs_info.num_dmrs_symb,
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deltaMCS,
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false);
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sched.phr_txpower_calc = compute_ph_factor(current_BWP->scs,
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sched.tb_size << 3,
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sched.rbSize,
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sched.nrOfLayers,
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sched.tda_info.nrOfSymbols,
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sched.dmrs_info.N_PRB_DMRS * sched.dmrs_info.num_dmrs_symb,
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deltaMCS,
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false);
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sched_ctrl->sched_pusch = sched;
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LOG_D(NR_MAC,
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"pf_ul %d.%d UE %x Scheduling PUSCH (no data) nrb %d mcs %d tbs %d bits phr_txpower %d\n",
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frame,
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slot,
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UE->rnti,
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sched_pusch->rbSize,
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sched_pusch->mcs,
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sched_pusch->tb_size << 3,
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sched_pusch->phr_txpower_calc);
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sched.rbSize,
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sched.mcs,
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sched.tb_size << 3,
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sched.phr_txpower_calc);
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/* Mark the corresponding RBs as used */
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n_rb_sched[beam.idx] -= sched_pusch->rbSize;
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for (int rb = bwpStart; rb < sched_ctrl->sched_pusch.rbSize; rb++)
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rballoc_mask[rb + sched_ctrl->sched_pusch.rbStart] |= slbitmap;
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n_rb_sched[beam.idx] -= sched.rbSize;
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for (int rb = bi.bwpStart; rb < sched.rbSize; rb++)
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rballoc_mask[rb + sched.rbStart] |= slbitmap;
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remainUEs[beam.idx]--;
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continue;
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