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Add statistics for CQI and MCS distribution

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This commit is contained in:
fatich
2026-03-24 10:51:59 +01:00
committed by Teodora
parent 0ba31c0f89
commit 5e379e41db
4 changed files with 35 additions and 0 deletions
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openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
+6
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@@ -1389,6 +1389,12 @@ void post_process_dlsch(gNB_MAC_INST *nr_mac, post_process_pdsch_t *pdsch, NR_UE
T(T_GNB_MAC_DL, T_INT(rnti), T_INT(frame), T_INT(slot), T_INT(sched_pdsch->mcs), T_INT(TBS));
}
DevAssert(nrOfLayers >= 1 && nrOfLayers <= 8);
DevAssert(current_BWP->mcsTableIdx >= 0 && current_BWP->mcsTableIdx <= 1);
DevAssert(sched_pdsch->mcs >= 0 && sched_pdsch->mcs <= 31);
NR_du_stats_t *stats = &nr_mac->du_stats;
stats->pdsch_mcs_dist[nrOfLayers - 1][current_BWP->mcsTableIdx][sched_pdsch->mcs] += sched_pdsch->rbSize;
const int ntx_req = pdsch->TX_req->Number_of_PDUs;
nfapi_nr_pdu_t *tx_req = &pdsch->TX_req->pdu_list[ntx_req];
tx_req->PDU_index = pduindex;
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c
+6
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@@ -637,6 +637,12 @@ static void evaluate_cqi_report(uint8_t *payload,
uint8_t temp_cqi = pickandreverse_bits(payload, 4, cumul_bits);
DevAssert(temp_cqi >= 0 && temp_cqi <= 15); // binX: value is 0-indexed, so it uses temp_cqi below
DevAssert(ri >= 0 && ri <= 7); // binY: value is 0-indexed, so it used ri below
DevAssert(cqi_Table >= 0 && cqi_Table <= 2); // binZ: value is 0-indexed, so it uses cqi_Table below
NR_du_stats_t *stats = &RC.nrmac[0]->du_stats;
stats->wb_cqi_dist[temp_cqi][ri][cqi_Table] += 1;
// NR_CSI_ReportConfig__cqi_Table_table1 = 0
// NR_CSI_ReportConfig__cqi_Table_table2 = 1
// NR_CSI_ReportConfig__cqi_Table_table3 = 2
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
+6
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@@ -2504,6 +2504,12 @@ void post_process_ulsch(gNB_MAC_INST *nr_mac, post_process_pusch_t *pusch, NR_UE
T(T_GNB_MAC_UL, T_INT(UE->rnti), T_INT(frame), T_INT(slot), T_INT(sched_pusch->mcs), T_INT(sched_pusch->tb_size));
DevAssert(sched_pusch->nrOfLayers >= 1 && sched_pusch->nrOfLayers <= 8);
DevAssert(current_BWP->mcs_table == 0 || current_BWP->mcs_table == 1 || current_BWP->mcs_table == 3);
DevAssert(sched_pusch->mcs >= 0 && sched_pusch->mcs <= 31);
NR_du_stats_t *stats = &nr_mac->du_stats;
stats->pusch_mcs_dist[sched_pusch->nrOfLayers - 1][current_BWP->mcs_table][sched_pusch->mcs] += sched_pusch->rbSize;
/* PUSCH in a later slot, but corresponding DCI now! */
const int index = ul_buffer_index(sched_pusch->frame,
sched_pusch->slot,
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+17
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@@ -889,6 +889,20 @@ typedef struct fsn {
slot_t s;
} fsn_t;
typedef struct NR_du_stats {
/// cell-wide wide-band CQI distribution, see 28.552 5.1.1.11.1;
/// 0-15 CQI, 1-8 RI, 1-3 CQI table
uint32_t wb_cqi_dist[16][8][3];
/// cell-wide MCS distribution in PDSCH, see 28.552 5.1.1.12.1
/// 1-8 RI, 1-3 MCS table, 0-31 MCS value
uint32_t pdsch_mcs_dist[8][3][32];
/// cell-wide MCS distribution in PUSCH, see 28.552 5.1.1.12.1
/// 1-8 RI, 1-2 MCS table, 0-31 MCS value
uint32_t pusch_mcs_dist[8][2][32];
} NR_du_stats_t;
/*! \brief top level eNB MAC structure */
typedef struct gNB_MAC_INST_s {
/// Ethernet parameters for northbound midhaul interface
@@ -1010,6 +1024,9 @@ typedef struct gNB_MAC_INST_s {
dlul_mac_stats_t mac_stats;
uint64_t num_scheduled_prach_rx;
NR_du_stats_t du_stats;
} gNB_MAC_INST;
#endif /*__LAYER2_NR_MAC_GNB_H__ */