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clang formatting and review

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This commit is contained in:
francescomani
2023-12-17 17:28:28 +01:00
parent b0dd591932
commit 60f5b9622c
17 changed files with 722 additions and 1290 deletions
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nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
+2 -1
View File
@@ -662,7 +662,8 @@ typedef struct
typedef struct
{
uint8_t prach_sequence_length;//RACH sequence length. Only short sequence length is supported for FR2. [38.211, sec 6.3.3.1] Value: 0 = Long sequence 1 = Short sequence
uint8_t prach_sub_c_spacing;//Subcarrier spacing of PRACH. [38.211 sec 4.2] Value: 0: 15 kHz 1: 30 kHz 2: 60 kHz 3: 120 kHz 4: 1.25 kHz 5: 5 kHz
uint8_t prach_sub_c_spacing; // Subcarrier spacing of PRACH. [38.211 sec 4.2] Value: 0: 15 kHz 1: 30 kHz 2: 60 kHz 3: 120 kHz
// 4: 1.25 kHz 5: 5 kHz
uint8_t restricted_set_config;//PRACH restricted set config Value: 0: unrestricted 1: restricted set type A 2: restricted set type B
uint8_t num_prach_fd_occasions;//Corresponds to the parameter 𝑀 in [38.211, sec 6.3.3.2] which equals the higher layer parameter msg1FDM Value: 1,2,4,8
fapi_nr_num_prach_fd_occasions_t* num_prach_fd_occasions_list;
openair1/SIMULATION/NR_PHY/dlsim.c
+5 -5
View File
@@ -1403,7 +1403,7 @@ void update_dmrs_config(NR_CellGroupConfig_t *scg, int8_t* dmrs_arg)
}
/* Additional DMRS positions 0 ,1 ,2 and 3 */
if(dmrs_arg[1] >= 0 && dmrs_arg[1] < 4) {
if (dmrs_arg[1] >= 0 && dmrs_arg[1] < 4) {
add_pos = dmrs_arg[1];
} else {
AssertFatal(1==0,"Incorrect Additional Position, valid options 0-pos1, 1-pos1, 2-pos2, 3-pos3\n");
@@ -1463,16 +1463,16 @@ void update_dmrs_config(NR_CellGroupConfig_t *scg, int8_t* dmrs_arg)
dmrs_config->dmrs_AdditionalPosition = calloc(1,sizeof(*dmrs_MappingtypeA->choice.setup->dmrs_AdditionalPosition));
}
switch (add_pos) {
case 0 :
case 0:
*dmrs_config->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0;
break;
case 1 :
case 1:
*dmrs_config->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1;
break;
case 3 :
case 3:
*dmrs_config->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos3;
break;
default :
default:
AssertFatal(false, "DMRS additional position %d not valid\n", add_pos);
}
} else { // if NULL, Value pos2
openair2/GNB_APP/gnb_config.c
+2 -1
View File
@@ -278,7 +278,8 @@ void fill_scc_sim(NR_ServingCellConfigCommon_t *scc,uint64_t *ssb_bitmap,int N_R
scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->offsetToCarrier=0;
scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing=mu_dl;
scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth=N_RB_DL;
scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth = PRBalloc_to_locationandbandwidth(N_RB_DL, 0);
scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth =
PRBalloc_to_locationandbandwidth(N_RB_DL, 0);
scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.subcarrierSpacing=mu_dl;//NR_SubcarrierSpacing_kHz30;
*scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->controlResourceSetZero=12;
*scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->searchSpaceZero=0;
openair2/LAYER2/NR_MAC_COMMON/nr_mac.h
+1 -1
View File
@@ -590,7 +590,7 @@ typedef struct NR_UE_UL_BWP {
int max_fb_time;
} NR_UE_UL_BWP_t;
// non-BWP seving cell configuration
// non-BWP serving cell configuration
typedef struct {
NR_CrossCarrierSchedulingConfig_t *crossCarrierSchedulingConfig;
NR_SRS_CarrierSwitching_t *carrierSwitching;
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
+3 -2
View File
@@ -3385,7 +3385,8 @@ uint16_t nr_dci_size(const NR_UE_DL_BWP_t *DL_BWP,
size += dci_pdu->dai[1].nbits;
}
// SRS resource indicator
dci_pdu->srs_resource_indicator.nbits = compute_srs_resource_indicator(sc_info->maxMIMO_Layers_PUSCH, pusch_Config, srs_config, NULL, NULL);
dci_pdu->srs_resource_indicator.nbits =
compute_srs_resource_indicator(sc_info->maxMIMO_Layers_PUSCH, pusch_Config, srs_config, NULL, NULL);
size += dci_pdu->srs_resource_indicator.nbits;
LOG_D(NR_MAC, "dci_pdu->srs_resource_indicator.nbits %d\n", dci_pdu->srs_resource_indicator.nbits);
// Precoding info and number of layers
@@ -3555,7 +3556,7 @@ uint16_t nr_dci_size(const NR_UE_DL_BWP_t *DL_BWP,
// PUCCH resource indicator
size += 3;
// PDSCH to HARQ timing indicator
uint8_t I = pucch_Config->dl_DataToUL_ACK ? pucch_Config->dl_DataToUL_ACK->list.count : 8;
uint8_t I = (pucch_Config && pucch_Config->dl_DataToUL_ACK) ? pucch_Config->dl_DataToUL_ACK->list.count : 8;
dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits = (int)ceil(log2(I));
size += dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits;
LOG_D(NR_MAC,"dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits %d\n",dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits);
openair2/LAYER2/NR_MAC_UE/config_ue.c
+522 -1127
View File
File diff suppressed because it is too large Load Diff
openair2/LAYER2/NR_MAC_UE/mac_proto.h
+82 -29
View File
@@ -39,37 +39,90 @@
#define NR_DL_MAX_DAI (4) /* TS 38.213 table 9.1.3-1 Value of counter DAI for DCI format 1_0 and 1_1 */
#define NR_DL_MAX_NB_CW (2) /* number of downlink code word */
#define updateMACie(destination, origin, type) { \
type *tmp = origin; \
origin = destination; \
destination = tmp; \
} \
#define UPDATE_MAC_IE(DESTINATION, ORIGIN, TYPE) \
do { \
TYPE *tmp = ORIGIN; \
ORIGIN = DESTINATION; \
DESTINATION = tmp; \
} while(0); \
#define handleMACsetuprelease(destination, origin, type, asn_DEF) { \
if (origin->present == 1) { \
ASN_STRUCT_FREE(asn_DEF, destination); \
destination = NULL; \
} \
if (origin->present == 2) \
updateMACie(destination, \
origin->choice.setup, \
type); \
} \
#define HANDLE_SETUPRELEASE_DIRECT(DESTINATION, ORIGIN, TYPE, ASN_DEF) \
do { \
if (ORIGIN->present == 1) { \
ASN_STRUCT_FREE(ASN_DEF, DESTINATION); \
DESTINATION = NULL; \
} \
if (ORIGIN->present == 2) \
UPDATE_MAC_IE(DESTINATION, ORIGIN->choice.setup, TYPE); \
} while(0); \
#define HANDLE_SETUPRELEASE_IE(DESTINATION, ORIGIN, TYPE, ASN_DEF) \
do { \
if (ORIGIN->present == 1) { \
ASN_STRUCT_FREE(ASN_DEF, DESTINATION); \
DESTINATION = NULL; \
} \
if (ORIGIN->present == 2) { \
if (!DESTINATION) \
DESTINATION = calloc(1, sizeof(*DESTINATION)); \
DESTINATION->present = ORIGIN->present; \
UPDATE_MAC_IE(DESTINATION->choice.setup, ORIGIN->choice.setup, TYPE); \
} \
} while(0); \
#define RELEASE_IE_FROMLIST(SOURCE, TARGET, FIELD) \
do { \
for (int iI = 0; iI < SOURCE->list.count; iI++) { \
long eL = *SOURCE->list.array[iI]; \
int iJ; \
for (iJ = 0; iJ < TARGET->list.count; iJ++) { \
if (eL == TARGET->list.array[iJ]->FIELD) \
break; \
} \
if (iJ == TARGET->list.count) \
asn_sequence_del(&TARGET->list, iJ, 1); \
else \
LOG_E(NR_MAC, "Element not present in the list, impossible to release\n"); \
} \
} while (0) \
#define ADDMOD_IE_FROMLIST(SOURCE, TARGET, FIELD, TYPE) \
do { \
for (int iI = 0; iI < SOURCE->list.count; iI++) { \
long eL = SOURCE->list.array[iI]->FIELD; \
int iJ; \
for (iJ = 0; iJ < TARGET->list.count; iJ++) { \
if (eL == TARGET->list.array[iJ]->FIELD) \
break; \
} \
if (iJ == TARGET->list.count) { \
TYPE *nEW = calloc(1, sizeof(*nEW)); \
ASN_SEQUENCE_ADD(&TARGET->list, nEW); \
} \
UPDATE_MAC_IE(TARGET->list.array[iJ], \
SOURCE->list.array[iI], \
TYPE); \
} \
} while (0) \
#define ADDMOD_IE_FROMLIST_WFUNCTION(SOURCE, TARGET, FIELD, TYPE, FUNC) \
do { \
for (int iI = 0; iI < SOURCE->list.count; iI++) { \
long eL = SOURCE->list.array[iI]->FIELD; \
int iJ; \
for (iJ = 0; iJ < TARGET->list.count; iJ++) { \
if (eL == TARGET->list.array[iJ]->FIELD) \
break; \
} \
if (iJ == TARGET->list.count) { \
TYPE *nEW = calloc(1, sizeof(*nEW)); \
ASN_SEQUENCE_ADD(&TARGET->list, nEW); \
} \
FUNC(TARGET->list.array[iJ], \
SOURCE->list.array[iI]); \
} \
} while (0)
#define handleMACsetupreleaseElement(destination, origin, type, asn_DEF) { \
if (origin->present == 1) { \
ASN_STRUCT_FREE(asn_DEF, destination); \
destination = NULL; \
} \
if (origin->present == 2) { \
if (!destination) \
destination = calloc(1, sizeof(*destination)); \
destination->present = origin->present; \
updateMACie(destination->choice.setup, \
origin->choice.setup, \
type); \
} \
} \
/**\brief initialize the field in nr_mac instance
\param module_id module id */
openair2/LAYER2/NR_MAC_UE/nr_ra_procedures.c
+1 -1
View File
@@ -77,7 +77,7 @@ void init_RA(module_id_t mod_id,
prach_resources->RA_PREAMBLE_BACKOFF = 0;
NR_SubcarrierSpacing_t prach_scs = *nr_rach_ConfigCommon->msg1_SubcarrierSpacing;
int n_prbs = get_N_RA_RB (prach_scs, mac->current_UL_BWP->scs);
int n_prbs = get_N_RA_RB(prach_scs, mac->current_UL_BWP->scs);
int start_prb = rach_ConfigGeneric->msg1_FrequencyStart + mac->current_UL_BWP->BWPStart;
// PRACH shall be as specified for QPSK modulated DFT-s-OFDM of equivalent RB allocation (38.101-1)
prach_resources->RA_PCMAX = nr_get_Pcmax(mac, 2, false, prach_scs, cfg->carrier_config.dl_grid_size[prach_scs], true, n_prbs, start_prb);
openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c
+29 -33
View File
@@ -88,8 +88,7 @@ void fill_dci_search_candidates(const NR_SearchSpace_t *ss,
NR_ControlResourceSet_t *ue_get_coreset(const NR_BWP_PDCCH_t *config, const int coreset_id)
{
if (config->commonControlResourceSet &&
coreset_id == config->commonControlResourceSet->controlResourceSetId)
if (config->commonControlResourceSet && coreset_id == config->commonControlResourceSet->controlResourceSetId)
return config->commonControlResourceSet;
NR_ControlResourceSet_t *coreset = NULL;
for (int i = 0; i < config->list_Coreset.count; i++) {
@@ -109,7 +108,6 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac,
const int slot,
const NR_SearchSpace_t *ss)
{
const NR_UE_DL_BWP_t *current_DL_BWP = mac->current_DL_BWP;
const NR_UE_UL_BWP_t *current_UL_BWP = mac->current_UL_BWP;
NR_BWP_Id_t dl_bwp_id = current_DL_BWP ? current_DL_BWP->bwp_id : 0;
@@ -188,33 +186,31 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac,
// computing alternative size for padding
dci_pdu_rel15_t temp_pdu;
if(dci_format == NR_DL_DCI_FORMAT_1_0)
alt_size =
nr_dci_size(current_DL_BWP,
current_UL_BWP,
sc_info,
mac->pdsch_HARQ_ACK_Codebook,
&temp_pdu,
NR_UL_DCI_FORMAT_0_0,
rnti_type,
coreset,
dl_bwp_id,
ss->searchSpaceType->present,
mac->type0_PDCCH_CSS_config.num_rbs,
0);
alt_size = nr_dci_size(current_DL_BWP,
current_UL_BWP,
sc_info,
mac->pdsch_HARQ_ACK_Codebook,
&temp_pdu,
NR_UL_DCI_FORMAT_0_0,
rnti_type,
coreset,
dl_bwp_id,
ss->searchSpaceType->present,
mac->type0_PDCCH_CSS_config.num_rbs,
0);
if(dci_format == NR_UL_DCI_FORMAT_0_0)
alt_size =
nr_dci_size(current_DL_BWP,
current_UL_BWP,
sc_info,
mac->pdsch_HARQ_ACK_Codebook,
&temp_pdu,
NR_DL_DCI_FORMAT_1_0,
rnti_type,
coreset,
dl_bwp_id,
ss->searchSpaceType->present,
mac->type0_PDCCH_CSS_config.num_rbs,
0);
alt_size = nr_dci_size(current_DL_BWP,
current_UL_BWP,
sc_info,
mac->pdsch_HARQ_ACK_Codebook,
&temp_pdu,
NR_DL_DCI_FORMAT_1_0,
rnti_type,
coreset,
dl_bwp_id,
ss->searchSpaceType->present,
mac->type0_PDCCH_CSS_config.num_rbs,
0);
}
rel15->dci_length_options[i] = nr_dci_size(current_DL_BWP,
@@ -488,10 +484,10 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl
mac->mib_ssb,
1, // If the UE is not configured with a periodicity, the UE assumes a periodicity of a half frame
ssb_offset_point_a);
if(pdcch_config->search_space_zero == NULL)
pdcch_config->search_space_zero = calloc(1,sizeof(*pdcch_config->search_space_zero));
if(pdcch_config->coreset0 == NULL)
pdcch_config->coreset0 = calloc(1,sizeof(*pdcch_config->coreset0));
if (pdcch_config->search_space_zero == NULL)
pdcch_config->search_space_zero = calloc(1, sizeof(*pdcch_config->search_space_zero));
if (pdcch_config->coreset0 == NULL)
pdcch_config->coreset0 = calloc(1, sizeof(*pdcch_config->coreset0));
fill_coresetZero(pdcch_config->coreset0, &mac->type0_PDCCH_CSS_config);
fill_searchSpaceZero(pdcch_config->search_space_zero, slots_per_frame, &mac->type0_PDCCH_CSS_config);
if (is_ss_monitor_occasion(frame, slot, slots_per_frame, pdcch_config->search_space_zero)) {
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
+2 -4
View File
@@ -736,9 +736,7 @@ static int nr_ue_process_dci_dl_10(module_id_t module_id,
dlsch_pdu->TBS = current_harq->TBS;
}
int bw_tbslbrm = current_DL_BWP?
mac->sc_info.dl_bw_tbslbrm :
dlsch_pdu->BWPSize;
int bw_tbslbrm = current_DL_BWP ? mac->sc_info.dl_bw_tbslbrm : dlsch_pdu->BWPSize;
dlsch_pdu->tbslbrm = nr_compute_tbslbrm(dlsch_pdu->mcs_table, bw_tbslbrm, 1);
/* NDI (only if CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI)*/
@@ -765,7 +763,7 @@ static int nr_ue_process_dci_dl_10(module_id_t module_id,
dlsch_pdu->accumulated_delta_PUCCH = tcp[dci->tpc];
// Sanity check for pucch_resource_indicator value received to check for false DCI.
bool valid = false;
NR_PUCCH_Config_t *pucch_Config = mac->current_UL_BWP? mac->current_UL_BWP->pucch_Config : NULL;
NR_PUCCH_Config_t *pucch_Config = mac->current_UL_BWP ? mac->current_UL_BWP->pucch_Config : NULL;
if (pucch_Config && pucch_Config->resourceSetToAddModList) {
int pucch_res_set_cnt = pucch_Config->resourceSetToAddModList->list.count;
openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c
+3 -6
View File
@@ -116,7 +116,7 @@ fapi_nr_ul_config_request_t *get_ul_config_request(NR_UE_MAC_INST_t *mac, int sl
//Check if requested on the right slot
AssertFatal(is_nr_UL_slot(tdd_config, slot, mac->frame_type) != 0, "UL config_request called at wrong slot %d\n", slot);
int mu = mac->current_UL_BWP ? mac->current_UL_BWP->scs : get_softmodem_params()->numerology;
int mu = mac->current_UL_BWP ? mac->current_UL_BWP->scs : get_softmodem_params()->numerology;
const int n = nr_slots_per_frame[mu];
AssertFatal(fb_time < n, "Cannot schedule to a slot more than 1 frame away, ul_config_request is not big enough\n");
AssertFatal(mac->ul_config_request != NULL, "mac->ul_config_request not initialized, logic bug\n");
@@ -668,9 +668,7 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac,
if (!maxMIMO_Layers)
maxMIMO_Layers = pusch_Config ? pusch_Config->maxRank : NULL;
AssertFatal (maxMIMO_Layers != NULL,"Option with max MIMO layers not configured is not supported\n");
pusch_config_pdu->tbslbrm = nr_compute_tbslbrm(pusch_config_pdu->mcs_table,
sc_info->ul_bw_tbslbrm,
*maxMIMO_Layers);
pusch_config_pdu->tbslbrm = nr_compute_tbslbrm(pusch_config_pdu->mcs_table, sc_info->ul_bw_tbslbrm, *maxMIMO_Layers);
} else
pusch_config_pdu->tbslbrm = 0;
@@ -2002,7 +2000,7 @@ static int get_nr_prach_info_from_ssb_index(uint8_t ssb_idx,
// - exact slot number
// - frame offset
ssb_info_p = &ssb_list->tx_ssb[ssb_idx];
LOG_D(NR_MAC,"checking for prach : ssb_info_p->nb_mapped_ro %d\n", ssb_info_p->nb_mapped_ro);
LOG_D(NR_MAC, "checking for prach : ssb_info_p->nb_mapped_ro %d\n", ssb_info_p->nb_mapped_ro);
for (uint8_t n_mapped_ro=0; n_mapped_ro<ssb_info_p->nb_mapped_ro; n_mapped_ro++) {
LOG_D(NR_MAC,"%d.%d: mapped_ro[%d]->frame.slot %d.%d, prach_assoc_pattern.nb_of_frame %d\n",
frame,slot,n_mapped_ro,ssb_info_p->mapped_ro[n_mapped_ro]->frame,ssb_info_p->mapped_ro[n_mapped_ro]->slot,prach_assoc_pattern.nb_of_frame);
@@ -2441,7 +2439,6 @@ void nr_schedule_csirs_reception(NR_UE_MAC_INST_t *mac, int frame, int slot)
}
}
// This function schedules the PRACH according to prach_ConfigurationIndex and TS 38.211, tables 6.3.3.2.x
// PRACH formats 9, 10, 11 are corresponding to dual PRACH format configurations A1/B1, A2/B2, A3/B3.
// - todo:
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+18 -21
View File
@@ -1178,7 +1178,7 @@ static void nr_generate_Msg2(module_id_t module_idP,
NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config = NULL;
if(*ss->controlResourceSetId != 0) {
BWPStart = dl_bwp->BWPStart;
BWPSize = sc_info->initial_dl_BWPSize;
BWPSize = sc_info->initial_dl_BWPSize;
} else {
type0_PDCCH_CSS_config = &nr_mac->type0_PDCCH_CSS_config[ra->beam_id];
BWPStart = type0_PDCCH_CSS_config->cset_start_rb;
@@ -1314,9 +1314,7 @@ static void nr_generate_Msg2(module_id_t module_idP,
pdsch_pdu_rel15->TBSize[0] = TBS;
}
pdsch_pdu_rel15->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(mcsTableIdx,
sc_info->dl_bw_tbslbrm,
1);
pdsch_pdu_rel15->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(mcsTableIdx, sc_info->dl_bw_tbslbrm, 1);
pdsch_pdu_rel15->maintenance_parms_v3.ldpcBaseGraph = get_BG(TBS<<3,R);
// Fill PDCCH DL DCI PDU
@@ -1523,9 +1521,7 @@ static void prepare_dl_pdus(gNB_MAC_INST *nr_mac,
int x_Overhead = 0;
nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead, pdsch_pdu_rel15->numDmrsCdmGrpsNoData, tb_scaling);
pdsch_pdu_rel15->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(mcsTableIdx,
ra->sc_info.dl_bw_tbslbrm,
1);
pdsch_pdu_rel15->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(mcsTableIdx, ra->sc_info.dl_bw_tbslbrm, 1);
pdsch_pdu_rel15->maintenance_parms_v3.ldpcBaseGraph = get_BG(tb_size<<3,R);
pdsch_pdu_rel15->precodingAndBeamforming.num_prgs=1;
@@ -1599,20 +1595,21 @@ static void prepare_dl_pdus(gNB_MAC_INST *nr_mac,
0, // parameter not needed for DCI 1_0
nr_mac->cset0_bwp_size);
LOG_D(NR_MAC,"BWPSize: %i\n", pdcch_pdu_rel15->BWPSize);
LOG_D(NR_MAC,"BWPStart: %i\n", pdcch_pdu_rel15->BWPStart);
LOG_D(NR_MAC,"SubcarrierSpacing: %i\n", pdcch_pdu_rel15->SubcarrierSpacing);
LOG_D(NR_MAC,"CyclicPrefix: %i\n", pdcch_pdu_rel15->CyclicPrefix);
LOG_D(NR_MAC,"StartSymbolIndex: %i\n", pdcch_pdu_rel15->StartSymbolIndex);
LOG_D(NR_MAC,"DurationSymbols: %i\n", pdcch_pdu_rel15->DurationSymbols);
for(int n=0;n<6;n++) LOG_D(NR_MAC,"FreqDomainResource[%i]: %x\n",n, pdcch_pdu_rel15->FreqDomainResource[n]);
LOG_D(NR_MAC,"CceRegMappingType: %i\n", pdcch_pdu_rel15->CceRegMappingType);
LOG_D(NR_MAC,"RegBundleSize: %i\n", pdcch_pdu_rel15->RegBundleSize);
LOG_D(NR_MAC,"InterleaverSize: %i\n", pdcch_pdu_rel15->InterleaverSize);
LOG_D(NR_MAC,"CoreSetType: %i\n", pdcch_pdu_rel15->CoreSetType);
LOG_D(NR_MAC,"ShiftIndex: %i\n", pdcch_pdu_rel15->ShiftIndex);
LOG_D(NR_MAC,"precoderGranularity: %i\n", pdcch_pdu_rel15->precoderGranularity);
LOG_D(NR_MAC,"numDlDci: %i\n", pdcch_pdu_rel15->numDlDci);
LOG_D(NR_MAC, "BWPSize: %i\n", pdcch_pdu_rel15->BWPSize);
LOG_D(NR_MAC, "BWPStart: %i\n", pdcch_pdu_rel15->BWPStart);
LOG_D(NR_MAC, "SubcarrierSpacing: %i\n", pdcch_pdu_rel15->SubcarrierSpacing);
LOG_D(NR_MAC, "CyclicPrefix: %i\n", pdcch_pdu_rel15->CyclicPrefix);
LOG_D(NR_MAC, "StartSymbolIndex: %i\n", pdcch_pdu_rel15->StartSymbolIndex);
LOG_D(NR_MAC, "DurationSymbols: %i\n", pdcch_pdu_rel15->DurationSymbols);
for (int n = 0; n < 6; n++)
LOG_D(NR_MAC, "FreqDomainResource[%i]: %x\n", n, pdcch_pdu_rel15->FreqDomainResource[n]);
LOG_D(NR_MAC, "CceRegMappingType: %i\n", pdcch_pdu_rel15->CceRegMappingType);
LOG_D(NR_MAC, "RegBundleSize: %i\n", pdcch_pdu_rel15->RegBundleSize);
LOG_D(NR_MAC, "InterleaverSize: %i\n", pdcch_pdu_rel15->InterleaverSize);
LOG_D(NR_MAC, "CoreSetType: %i\n", pdcch_pdu_rel15->CoreSetType);
LOG_D(NR_MAC, "ShiftIndex: %i\n", pdcch_pdu_rel15->ShiftIndex);
LOG_D(NR_MAC, "precoderGranularity: %i\n", pdcch_pdu_rel15->precoderGranularity);
LOG_D(NR_MAC, "numDlDci: %i\n", pdcch_pdu_rel15->numDlDci);
}
static void nr_generate_Msg4(module_id_t module_idP,
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
+2 -3
View File
@@ -1085,9 +1085,8 @@ void nr_schedule_ue_spec(module_id_t module_id,
long maxMIMO_Layers = UE->sc_info.maxMIMO_Layers_PDSCH ? *UE->sc_info.maxMIMO_Layers_PDSCH : 1;
const int nl_tbslbrm = min(maxMIMO_Layers, 4);
// Maximum number of PRBs across all configured DL BWPs
pdsch_pdu->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(current_BWP->mcsTableIdx,
UE->sc_info.dl_bw_tbslbrm,
nl_tbslbrm);
pdsch_pdu->maintenance_parms_v3.tbSizeLbrmBytes =
nr_compute_tbslbrm(current_BWP->mcsTableIdx, UE->sc_info.dl_bw_tbslbrm, nl_tbslbrm);
pdsch_pdu->maintenance_parms_v3.ldpcBaseGraph = get_BG(TBS<<3,R);
NR_PDSCH_Config_t *pdsch_Config = current_BWP->pdsch_Config;
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+42 -42
View File
@@ -716,7 +716,11 @@ void config_uldci(const NR_UE_ServingCell_Info_t *sc_info,
pusch_Config->txConfig != NULL) {
AssertFatal(*pusch_Config->txConfig == NR_PUSCH_Config__txConfig_codebook,
"Non Codebook configuration non supported\n");
compute_srs_resource_indicator(sc_info->maxMIMO_Layers_PUSCH, pusch_Config, ul_bwp->srs_Config, srs_feedback, &dci_pdu_rel15->srs_resource_indicator.val);
compute_srs_resource_indicator(sc_info->maxMIMO_Layers_PUSCH,
pusch_Config,
ul_bwp->srs_Config,
srs_feedback,
&dci_pdu_rel15->srs_resource_indicator.val);
}
compute_precoding_information(pusch_Config,
ul_bwp->srs_Config,
@@ -1099,8 +1103,8 @@ void prepare_dci(const NR_UE_ServingCell_Info_t *servingCellInfo,
AssertFatal(1==0,"TCI in DCI currently not supported\n");
//srs resource set
if (servingCellInfo->carrierSwitching) {
if (servingCellInfo->carrierSwitching->srs_TPC_PDCCH_Group){
switch(servingCellInfo->carrierSwitching->srs_TPC_PDCCH_Group->present) {
if (servingCellInfo->carrierSwitching->srs_TPC_PDCCH_Group) {
switch (servingCellInfo->carrierSwitching->srs_TPC_PDCCH_Group->present) {
case NR_SRS_CarrierSwitching__srs_TPC_PDCCH_Group_PR_NOTHING:
dci_pdu_rel15->srs_request.val = 0;
break;
@@ -1111,16 +1115,14 @@ void prepare_dci(const NR_UE_ServingCell_Info_t *servingCellInfo,
AssertFatal(1==0,"SRS TPC PRCCH group type B currently not supported\n");
break;
}
}
else
} else
dci_pdu_rel15->srs_request.val = 0;
}
else
} else
dci_pdu_rel15->srs_request.val = 0;
// CBGTI and CBGFI
if (servingCellInfo->pdsch_CGB_Transmission)
AssertFatal(1==0,"CBG transmission currently not supported\n");
break;
if (servingCellInfo->pdsch_CGB_Transmission)
AssertFatal(1 == 0, "CBG transmission currently not supported\n");
break;
default :
AssertFatal(1==0,"Prepare dci currently only implemented for 1_1 and 0_1 \n");
}
@@ -2018,14 +2020,13 @@ void reset_sched_ctrl(NR_UE_sched_ctrl_t *sched_ctrl)
sched_ctrl->srs_feedback.sri = 0;
}
int get_dlbw_tbslbrm(int scc_bwpsize,
const NR_ServingCellConfig_t *servingCellConfig)
int get_dlbw_tbslbrm(int scc_bwpsize, const NR_ServingCellConfig_t *servingCellConfig)
{
int bw = scc_bwpsize;
if (servingCellConfig) {
if(servingCellConfig->downlinkBWP_ToAddModList) {
if (servingCellConfig->downlinkBWP_ToAddModList) {
const struct NR_ServingCellConfig__downlinkBWP_ToAddModList *BWP_list = servingCellConfig->downlinkBWP_ToAddModList;
for (int i=0; i<BWP_list->list.count; i++) {
for (int i = 0; i < BWP_list->list.count; i++) {
NR_BWP_t genericParameters = BWP_list->list.array[i]->bwp_Common->genericParameters;
int curr_bw = NRRIV2BW(genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
if (curr_bw > bw)
@@ -2036,15 +2037,13 @@ int get_dlbw_tbslbrm(int scc_bwpsize,
return bw;
}
int get_ulbw_tbslbrm(int scc_bwpsize,
const NR_ServingCellConfig_t *servingCellConfig)
int get_ulbw_tbslbrm(int scc_bwpsize, const NR_ServingCellConfig_t *servingCellConfig)
{
int bw = scc_bwpsize;
if (servingCellConfig) {
if (servingCellConfig->uplinkConfig &&
servingCellConfig->uplinkConfig->uplinkBWP_ToAddModList) {
if (servingCellConfig->uplinkConfig && servingCellConfig->uplinkConfig->uplinkBWP_ToAddModList) {
const struct NR_UplinkConfig__uplinkBWP_ToAddModList *BWP_list = servingCellConfig->uplinkConfig->uplinkBWP_ToAddModList;
for (int i=0; i<BWP_list->list.count; i++) {
for (int i = 0; i < BWP_list->list.count; i++) {
NR_BWP_t genericParameters = BWP_list->list.array[i]->bwp_Common->genericParameters;
int curr_bw = NRRIV2BW(genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
if (curr_bw > bw)
@@ -2193,8 +2192,10 @@ void configure_UE_BWP(gNB_MAC_INST *nr_mac,
DL_BWP->cyclicprefix = dl_genericParameters.cyclicPrefix;
DL_BWP->BWPSize = NRRIV2BW(dl_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
DL_BWP->BWPStart = NRRIV2PRBOFFSET(dl_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
sc_info->initial_dl_BWPSize = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
sc_info->initial_dl_BWPStart = NRRIV2PRBOFFSET(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
sc_info->initial_dl_BWPSize =
NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
sc_info->initial_dl_BWPStart =
NRRIV2PRBOFFSET(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
NR_BWP_t ul_genericParameters = (UL_BWP->bwp_id > 0 && ul_bwp) ?
ul_bwp->bwp_Common->genericParameters:
@@ -2204,8 +2205,10 @@ void configure_UE_BWP(gNB_MAC_INST *nr_mac,
UL_BWP->cyclicprefix = ul_genericParameters.cyclicPrefix;
UL_BWP->BWPSize = NRRIV2BW(ul_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
UL_BWP->BWPStart = NRRIV2PRBOFFSET(ul_genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
sc_info->initial_ul_BWPSize = NRRIV2BW(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
sc_info->initial_ul_BWPStart = NRRIV2PRBOFFSET(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
sc_info->initial_ul_BWPSize =
NRRIV2BW(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
sc_info->initial_ul_BWPStart =
NRRIV2PRBOFFSET(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
sc_info->dl_bw_tbslbrm = get_dlbw_tbslbrm(sc_info->initial_dl_BWPSize, servingCellConfig);
sc_info->dl_bw_tbslbrm = get_ulbw_tbslbrm(sc_info->initial_ul_BWPSize, servingCellConfig);
@@ -2220,18 +2223,17 @@ void configure_UE_BWP(gNB_MAC_INST *nr_mac,
if(UE) {
if (servingCellConfig) {
if(servingCellConfig->csi_MeasConfig) {
if (servingCellConfig->csi_MeasConfig) {
sc_info->csi_MeasConfig = servingCellConfig->csi_MeasConfig->choice.setup;
compute_csi_bitlen (sc_info->csi_MeasConfig, UE->csi_report_template);
compute_csi_bitlen(sc_info->csi_MeasConfig, UE->csi_report_template);
}
if (servingCellConfig->pdsch_ServingCellConfig &&
servingCellConfig->pdsch_ServingCellConfig->choice.setup) {
if (servingCellConfig->pdsch_ServingCellConfig && servingCellConfig->pdsch_ServingCellConfig->choice.setup) {
NR_PDSCH_ServingCellConfig_t *pdsch_servingcellconfig = servingCellConfig->pdsch_ServingCellConfig->choice.setup;
sc_info->nrofHARQ_ProcessesForPDSCH = pdsch_servingcellconfig->nrofHARQ_ProcessesForPDSCH;
if (pdsch_servingcellconfig->ext1)
sc_info->maxMIMO_Layers_PDSCH = pdsch_servingcellconfig->ext1->maxMIMO_Layers;
if (pdsch_servingcellconfig->codeBlockGroupTransmission &&
pdsch_servingcellconfig->codeBlockGroupTransmission->choice.setup)
if (pdsch_servingcellconfig->codeBlockGroupTransmission
&& pdsch_servingcellconfig->codeBlockGroupTransmission->choice.setup)
sc_info->pdsch_CGB_Transmission = pdsch_servingcellconfig->codeBlockGroupTransmission->choice.setup;
}
sc_info->crossCarrierSchedulingConfig = servingCellConfig->crossCarrierSchedulingConfig;
@@ -2239,14 +2241,15 @@ void configure_UE_BWP(gNB_MAC_INST *nr_mac,
if (servingCellConfig->uplinkConfig) {
if (servingCellConfig->uplinkConfig->carrierSwitching)
sc_info->carrierSwitching = servingCellConfig->uplinkConfig->carrierSwitching->choice.setup;
if (servingCellConfig->uplinkConfig->pusch_ServingCellConfig &&
servingCellConfig->uplinkConfig->pusch_ServingCellConfig->choice.setup) {
NR_PUSCH_ServingCellConfig_t *pusch_servingcellconfig = servingCellConfig->uplinkConfig->pusch_ServingCellConfig->choice.setup;
if (servingCellConfig->uplinkConfig->pusch_ServingCellConfig
&& servingCellConfig->uplinkConfig->pusch_ServingCellConfig->choice.setup) {
NR_PUSCH_ServingCellConfig_t *pusch_servingcellconfig =
servingCellConfig->uplinkConfig->pusch_ServingCellConfig->choice.setup;
if (pusch_servingcellconfig->ext1)
sc_info->maxMIMO_Layers_PUSCH = pusch_servingcellconfig->ext1->maxMIMO_Layers;
sc_info->rateMatching_PUSCH = pusch_servingcellconfig->rateMatching;
if (pusch_servingcellconfig->codeBlockGroupTransmission &&
pusch_servingcellconfig->codeBlockGroupTransmission->choice.setup)
if (pusch_servingcellconfig->codeBlockGroupTransmission
&& pusch_servingcellconfig->codeBlockGroupTransmission->choice.setup)
sc_info->pusch_CGB_Transmission = pusch_servingcellconfig->codeBlockGroupTransmission->choice.setup;
}
}
@@ -2362,7 +2365,7 @@ NR_UE_info_t *add_new_nr_ue(gNB_MAC_INST *nr_mac, rnti_t rntiP, NR_CellGroupConf
// We will attach at the end, to mitigate race conditions
// This is not good, but we will fix it progressively
NR_UE_info_t *UE = calloc(1,sizeof(NR_UE_info_t));
NR_UE_info_t *UE = calloc(1, sizeof(NR_UE_info_t));
if(!UE) {
LOG_E(NR_MAC,"want to add UE %04x but the fixed allocated size is full\n",rntiP);
return NULL;
@@ -2396,9 +2399,7 @@ NR_UE_info_t *add_new_nr_ue(gNB_MAC_INST *nr_mac, rnti_t rntiP, NR_CellGroupConf
sched_ctrl->sched_pusch.time_domain_allocation = -1;
/* Set default BWPs */
AssertFatal(UE->sc_info.n_ul_bwp <= NR_MAX_NUM_BWP,
"uplinkBWP_ToAddModList has %d BWP!\n",
UE->sc_info.n_ul_bwp);
AssertFatal(UE->sc_info.n_ul_bwp <= NR_MAX_NUM_BWP, "uplinkBWP_ToAddModList has %d BWP!\n", UE->sc_info.n_ul_bwp);
if (get_softmodem_params()->phy_test == 0) {
UE->ra_timer = 12000 << UE->current_DL_BWP.scs; // 12000 ms is arbitrary and found to be a good timeout from experiments
@@ -2468,11 +2469,10 @@ void free_sched_pucch_list(NR_UE_sched_ctrl_t *sched_ctrl)
free(sched_ctrl->sched_pucch);
}
void create_dl_harq_list(NR_UE_sched_ctrl_t *sched_ctrl,
const NR_UE_ServingCell_Info_t *sc_info)
void create_dl_harq_list(NR_UE_sched_ctrl_t *sched_ctrl, const NR_UE_ServingCell_Info_t *sc_info)
{
const int nrofHARQ = sc_info && sc_info->nrofHARQ_ProcessesForPDSCH ?
get_nrofHARQ_ProcessesForPDSCH(*sc_info->nrofHARQ_ProcessesForPDSCH) : 8;
const int nrofHARQ =
sc_info && sc_info->nrofHARQ_ProcessesForPDSCH ? get_nrofHARQ_ProcessesForPDSCH(*sc_info->nrofHARQ_ProcessesForPDSCH) : 8;
// add all available DL HARQ processes for this UE
AssertFatal(sched_ctrl->available_dl_harq.len == sched_ctrl->feedback_dl_harq.len
&& sched_ctrl->available_dl_harq.len == sched_ctrl->retrans_dl_harq.len,
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
+5 -7
View File
@@ -2281,18 +2281,16 @@ void nr_schedule_ulsch(module_id_t module_id, frame_t frame, sub_frame_t slot, n
pusch_pdu->maintenance_parms_v3.ldpcBaseGraph = get_BG(sched_pusch->tb_size<<3,sched_pusch->R);
NR_UE_ServingCell_Info_t *sc_info = &UE->sc_info;
if(sc_info->rateMatching_PUSCH) {
if (sc_info->rateMatching_PUSCH) {
// TBS_LBRM according to section 5.4.2.1 of 38.212
long *maxMIMO_Layers = sc_info->maxMIMO_Layers_PUSCH;
if (!maxMIMO_Layers)
maxMIMO_Layers = current_BWP->pusch_Config->maxRank;
AssertFatal (maxMIMO_Layers != NULL,"Option with max MIMO layers not configured is not supported\n");
pusch_pdu->maintenance_parms_v3.tbSizeLbrmBytes = nr_compute_tbslbrm(current_BWP->mcs_table,
sc_info->ul_bw_tbslbrm,
*maxMIMO_Layers);
}
else
pusch_pdu->maintenance_parms_v3.tbSizeLbrmBytes = 0;
pusch_pdu->maintenance_parms_v3.tbSizeLbrmBytes =
nr_compute_tbslbrm(current_BWP->mcs_table, sc_info->ul_bw_tbslbrm, *maxMIMO_Layers);
} else
pusch_pdu->maintenance_parms_v3.tbSizeLbrmBytes = 0;
LOG_D(NR_MAC,"PUSCH PDU : data_scrambling_identity %x, dmrs_scrambling_id %x\n",pusch_pdu->data_scrambling_id,pusch_pdu->ul_dmrs_scrambling_id);
/* TRANSFORM PRECODING --------------------------------------------------------*/
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+1 -3
View File
@@ -142,7 +142,6 @@ void handle_nr_uci_pucch_2_3_4(module_id_t mod_id,
sub_frame_t slot,
const nfapi_nr_uci_pucch_pdu_format_2_3_4_t *uci_234);
void config_uldci(const NR_UE_ServingCell_Info_t *sc_info,
const nfapi_nr_pusch_pdu_t *pusch_pdu,
dci_pdu_rel15_t *dci_pdu_rel15,
@@ -355,8 +354,7 @@ void nr_rx_sdu(const module_id_t gnb_mod_idP,
const uint8_t ul_cqi,
const uint16_t rssi);
void create_dl_harq_list(NR_UE_sched_ctrl_t *sched_ctrl,
const NR_UE_ServingCell_Info_t *sc_info);
void create_dl_harq_list(NR_UE_sched_ctrl_t *sched_ctrl, const NR_UE_ServingCell_Info_t *sc_info);
void reset_dl_harq_list(NR_UE_sched_ctrl_t *sched_ctrl);
openair2/RRC/NR/nr_rrc_config.c
+2 -4
View File
@@ -175,13 +175,11 @@ NR_SearchSpace_t *rrc_searchspace_config(bool is_common, int searchspaceid, int
ss->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0;
ss->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n1;
ss->nrofCandidates->aggregationLevel8 = NR_SearchSpace__nrofCandidates__aggregationLevel8_n1;
}
else {
} else {
if (is_common) {
ss->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n0;
ss->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n1;
}
else {
} else {
ss->nrofCandidates->aggregationLevel2 = NR_SearchSpace__nrofCandidates__aggregationLevel2_n2;
ss->nrofCandidates->aggregationLevel4 = NR_SearchSpace__nrofCandidates__aggregationLevel4_n0;
}