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Fix DCI allocation for coreset0

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This commit is contained in:
rmagueta
2021-08-31 20:14:07 +01:00
parent e621c3533c
commit 6746fd4077
2 changed files with 3 additions and 2 deletions
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openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+1 -1
View File
@@ -1000,7 +1000,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2 + sizeof(nfapi_nr_dl_tti_pdcch_pdu));
dl_req->nPDUs += 1;
pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
nr_configure_pdcch(pdcch_pdu_rel15, ss, coreset, scc, genericParameters, NULL);
nr_configure_pdcch(pdcch_pdu_rel15, ss, coreset, scc, genericParameters, &nr_mac->type0_PDCCH_CSS_config[ra->beam_id]);
nr_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid] = pdcch_pdu_rel15;
}
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+2 -1
View File
@@ -692,7 +692,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu,
NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config) {
int sps;
if (bwp) { // This is not for SIB1
if (bwp && *ss->controlResourceSetId!=0) { // This is not for coreset0
pdcch_pdu->BWPSize = NRRIV2BW(bwp->locationAndBandwidth, MAX_BWP_SIZE);
pdcch_pdu->BWPStart = NRRIV2PRBOFFSET(bwp->locationAndBandwidth, MAX_BWP_SIZE);
pdcch_pdu->SubcarrierSpacing = bwp->subcarrierSpacing;
@@ -702,6 +702,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu,
sps = bwp->cyclicPrefix == NULL ? 14 : 12;
}
else {
AssertFatal(type0_PDCCH_CSS_config!=NULL,"type0_PDCCH_CSS_config is null\n");
pdcch_pdu->BWPSize = type0_PDCCH_CSS_config->num_rbs;
pdcch_pdu->BWPStart = type0_PDCCH_CSS_config->cset_start_rb;
pdcch_pdu->SubcarrierSpacing = type0_PDCCH_CSS_config->scs_pdcch;