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@@ -65,7 +65,7 @@ int16_t ssb_index_from_prach(module_id_t module_idP,
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uint8_t config_index = scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.prach_ConfigurationIndex;
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uint8_t fdm = cfg->prach_config.num_prach_fd_occasions.value;
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uint8_t total_RApreambles = 64;
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uint8_t total_RApreambles = MAX_NUM_NR_PRACH_PREAMBLES;
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if( scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles != NULL)
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total_RApreambles = *scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->totalNumberOfRA_Preambles;
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@@ -520,7 +520,7 @@ void nr_initiate_ra_proc(module_id_t module_idP,
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VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 1);
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LOG_I(MAC,
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LOG_D(MAC,
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"[gNB %d][RAPROC] CC_id %d Frame %d, Slot %d Initiating RA procedure for preamble index %d\n",
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module_idP,
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CC_id,
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@@ -542,7 +542,6 @@ void nr_initiate_ra_proc(module_id_t module_idP,
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continue; // if the PRACH preamble does not correspond to any of the ones sent through RRC abort RA proc
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}
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}
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int loop = 0;
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LOG_D(MAC, "Frame %d, Slot %d: Activating RA process \n", frameP, slotP);
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ra->state = Msg2;
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ra->timing_offset = timing_offset;
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@@ -574,7 +573,11 @@ void nr_initiate_ra_proc(module_id_t module_idP,
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ra->Msg2_frame = msg2_frame;
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ra->Msg2_slot = msg2_slot;
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LOG_I(MAC, "%s() Msg2[%04d%d] SFN/SF:%04d%d\n", __FUNCTION__, ra->Msg2_frame, ra->Msg2_slot, frameP, slotP);
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LOG_D(MAC, "%s() Msg2[%04d%d] SFN/SF:%04d%d\n", __FUNCTION__, ra->Msg2_frame, ra->Msg2_slot, frameP, slotP);
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// TODO: Configure RRC with the new RNTI of the following commented lines
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/*
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int loop = 0;
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if (!ra->cfra) {
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do {
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ra->rnti = (taus() % 65518) + 1;
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@@ -587,11 +590,13 @@ void nr_initiate_ra_proc(module_id_t module_idP,
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abort();
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}
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}
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*/
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ra->RA_rnti = ra_rnti;
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ra->preamble_index = preamble_index;
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ra->beam_id = beam_index;
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LOG_I(MAC,
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LOG_D(MAC,
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"[gNB %d][RAPROC] CC_id %d Frame %d Activating Msg2 generation in frame %d, slot %d using RA rnti %x SSB "
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"index %u\n",
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module_idP,
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@@ -610,76 +615,76 @@ void nr_initiate_ra_proc(module_id_t module_idP,
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VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_INITIATE_RA_PROC, 0);
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}
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void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP)
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{
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gNB_MAC_INST *mac = RC.nrmac[module_idP];
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void nr_schedule_RA(module_id_t module_idP, frame_t frameP, sub_frame_t slotP)
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{
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gNB_MAC_INST *mac = RC.nrmac[module_idP];
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start_meas(&mac->schedule_ra);
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for (int CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
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NR_COMMON_channels_t *cc = &mac->common_channels[CC_id];
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for (int i = 0; i < NR_NB_RA_PROC_MAX; i++) {
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NR_RA_t *ra = &cc->ra[i];
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LOG_D(MAC, "RA[state:%d]\n", ra->state);
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switch (ra->state) {
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case Msg2:
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nr_generate_Msg2(module_idP, CC_id, frameP, slotP, ra);
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break;
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case Msg4:
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nr_generate_Msg4(module_idP, CC_id, frameP, slotP);
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break;
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case WAIT_Msg4_ACK:
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nr_check_Msg4_Ack(module_idP, CC_id, frameP, slotP);
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break;
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default:
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break;
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start_meas(&mac->schedule_ra);
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for (int CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
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NR_COMMON_channels_t *cc = &mac->common_channels[CC_id];
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for (int i = 0; i < NR_NB_RA_PROC_MAX; i++) {
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NR_RA_t *ra = &cc->ra[i];
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LOG_D(MAC, "RA[state:%d]\n", ra->state);
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switch (ra->state) {
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case Msg2:
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nr_generate_Msg2(module_idP, CC_id, frameP, slotP, ra);
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break;
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case Msg4:
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nr_generate_Msg4(module_idP, CC_id, frameP, slotP);
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break;
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case WAIT_Msg4_ACK:
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nr_check_Msg4_Ack(module_idP, CC_id, frameP, slotP);
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break;
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default:
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break;
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}
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}
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}
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stop_meas(&mac->schedule_ra);
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}
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stop_meas(&mac->schedule_ra);
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}
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void nr_get_Msg3alloc(module_id_t module_id,
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int CC_id,
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NR_ServingCellConfigCommon_t *scc,
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NR_BWP_Uplink_t *ubwp,
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sub_frame_t current_slot,
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frame_t current_frame,
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NR_RA_t *ra) {
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void nr_get_Msg3alloc(module_id_t module_id,
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int CC_id,
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NR_ServingCellConfigCommon_t *scc,
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NR_BWP_Uplink_t *ubwp,
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sub_frame_t current_slot,
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frame_t current_frame,
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NR_RA_t *ra) {
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// msg3 is schedulend in mixed slot in the following TDD period
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// msg3 is schedulend in mixed slot in the following TDD period
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uint16_t msg3_nb_rb = 8 + sizeof(NR_MAC_SUBHEADER_SHORT) + sizeof(NR_MAC_SUBHEADER_SHORT); // sdu has 6 or 8 bytes
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uint16_t msg3_nb_rb = 8 + sizeof(NR_MAC_SUBHEADER_SHORT) + sizeof(NR_MAC_SUBHEADER_SHORT); // sdu has 6 or 8 bytes
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int mu = ubwp->bwp_Common->genericParameters.subcarrierSpacing;
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int StartSymbolIndex, NrOfSymbols, startSymbolAndLength, temp_slot;
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ra->Msg3_tda_id = 16; // initialization to a value above limit
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int mu = ubwp->bwp_Common->genericParameters.subcarrierSpacing;
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int StartSymbolIndex, NrOfSymbols, startSymbolAndLength, temp_slot;
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ra->Msg3_tda_id = 16; // initialization to a value above limit
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for (int i=0; i<ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.count; i++) {
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startSymbolAndLength = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength;
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SLIV2SL(startSymbolAndLength, &StartSymbolIndex, &NrOfSymbols);
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// we want to transmit in the uplink symbols of mixed slot
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if (NrOfSymbols == scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols) {
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ra->Msg3_tda_id = i;
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break;
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for (int i=0; i<ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.count; i++) {
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startSymbolAndLength = ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[i]->startSymbolAndLength;
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SLIV2SL(startSymbolAndLength, &StartSymbolIndex, &NrOfSymbols);
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// we want to transmit in the uplink symbols of mixed slot
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if (NrOfSymbols == scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols) {
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ra->Msg3_tda_id = i;
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break;
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}
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}
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}
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AssertFatal(ra->Msg3_tda_id<16,"Unable to find Msg3 time domain allocation in list\n");
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AssertFatal(ra->Msg3_tda_id<16,"Unable to find Msg3 time domain allocation in list\n");
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uint8_t k2 = *ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[ra->Msg3_tda_id]->k2;
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uint8_t k2 = *ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list.array[ra->Msg3_tda_id]->k2;
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temp_slot = current_slot + k2 + DELTA[mu]; // msg3 slot according to 8.3 in 38.213
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ra->Msg3_slot = temp_slot%nr_slots_per_frame[mu];
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if (nr_slots_per_frame[mu]>temp_slot)
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ra->Msg3_frame = current_frame;
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else
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ra->Msg3_frame = current_frame + (temp_slot/nr_slots_per_frame[mu]);
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temp_slot = current_slot + k2 + DELTA[mu]; // msg3 slot according to 8.3 in 38.213
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ra->Msg3_slot = temp_slot%nr_slots_per_frame[mu];
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if (nr_slots_per_frame[mu]>temp_slot)
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ra->Msg3_frame = current_frame;
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else
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ra->Msg3_frame = current_frame + (temp_slot/nr_slots_per_frame[mu]);
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LOG_I(MAC, "[RAPROC] Msg3 slot %d: current slot %u Msg3 frame %u k2 %u Msg3_tda_id %u start symbol index %u\n", ra->Msg3_slot, current_slot, ra->Msg3_frame, k2,ra->Msg3_tda_id, StartSymbolIndex);
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uint16_t *vrb_map_UL =
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&RC.nrmac[module_id]->common_channels[CC_id].vrb_map_UL[ra->Msg3_slot * MAX_BWP_SIZE];
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const uint16_t bwpSize = NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
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LOG_D(MAC, "[RAPROC] Msg3 slot %d: current slot %u Msg3 frame %u k2 %u Msg3_tda_id %u start symbol index %u\n", ra->Msg3_slot, current_slot, ra->Msg3_frame, k2,ra->Msg3_tda_id, StartSymbolIndex);
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uint16_t *vrb_map_UL =
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&RC.nrmac[module_id]->common_channels[CC_id].vrb_map_UL[ra->Msg3_slot * MAX_BWP_SIZE];
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const uint16_t bwpSize = NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
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/* search msg3_nb_rb free RBs */
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/* search msg3_nb_rb free RBs */
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int rbSize = 0;
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int rbStart = 0;
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while (rbSize < msg3_nb_rb) {
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@@ -824,7 +829,6 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
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gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
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NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id];
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NR_RA_t *ra = &cc->ra[0];
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if ((ra->Msg2_frame == frameP) && (ra->Msg2_slot == slotP)) {
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@@ -838,14 +842,31 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
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int time_domain_assignment = 0;
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uint8_t nr_of_candidates = 0;
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uint8_t aggregation_level = 0;
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int rbStart = 0;
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int rbSize = 6;
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uint16_t *vrb_map = cc[CC_id].vrb_map;
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NR_SearchSpace_t *ss = nr_mac->sched_ctrlCommon->search_space;
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NR_BWP_Downlink_t *bwp = nr_mac->sched_ctrlCommon->active_bwp;
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NR_ControlResourceSet_t *coreset = nr_mac->sched_ctrlCommon->coreset;
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NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
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long BWPSize = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
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long BWPStart = NRRIV2PRBOFFSET(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
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nfapi_nr_dl_tti_request_body_t *dl_req = &nr_mac->DL_req[CC_id].dl_tti_request_body;
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for (int i = 0; (i < rbSize) && (rbStart <= (BWPSize - rbSize)); i++) {
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if (vrb_map[rbStart + i]) {
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rbStart += i;
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i = 0;
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}
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}
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if (rbStart > (BWPSize - rbSize)) {
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LOG_E(MAC, "%s(): cannot find free vrb_map for RA RNTI %04x!\n", __func__, ra->RA_rnti);
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return;
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}
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// Checking if the DCI allocation is feasible in current subframe
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if (dl_req->nPDUs > NFAPI_NR_MAX_DL_TTI_PDUS - 2) {
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LOG_I(MAC, "[RAPROC] Subframe %d: FAPI DL structure is full, skip scheduling UE %d\n", slotP, ra->RA_rnti);
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@@ -866,8 +887,6 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
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return;
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}
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nfapi_nr_pdu_t *tx_req = &nr_mac->TX_req[CC_id].pdu_list[nr_mac->TX_req[CC_id].Number_of_PDUs];
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// look up the PDCCH PDU for this CC, BWP, and CORESET. If it does not exist, create it. This is especially
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// important if we have multiple RAs, and the DLSCH has to reuse them, so we need to mark them
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const int bwpid = bwp->bwp_Id;
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@@ -894,14 +913,9 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
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dl_req->nPDUs+=1;
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nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15 = &dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15;
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LOG_I(NR_MAC,"[gNB %d] [RAPROC] CC_id %d Frame %d, slotP %d: Generating RA-Msg2 DCI, state %d\n", module_idP, CC_id, frameP, slotP, ra->state);
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LOG_I(NR_MAC,"[gNB %d][RAPROC] CC_id %d Frame %d, slotP %d: Generating RA-Msg2 DCI, rnti 0x%x, state %d\n", module_idP, CC_id, frameP, slotP, ra->RA_rnti, ra->state);
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// This code from this point on will not work on initialBWP or CORESET0
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AssertFatal(ra->bwp_id>0,"cannot work on initialBWP for now\n");
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AssertFatal(ra->secondaryCellGroup,
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"no secondaryCellGroup for RNTI %04x\n",
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ra->crnti);
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AssertFatal(ra->secondaryCellGroup, "no secondaryCellGroup for RNTI %04x\n", ra->crnti);
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AssertFatal(ra->secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1,
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"downlinkBWP_ToAddModList has %d BWP!\n", ra->secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count);
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@@ -912,15 +926,14 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
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// information to data and is reset every slot.
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const int pduindex = nr_mac->pdu_index[CC_id]++;
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pdsch_pdu_rel15->pduIndex = pduindex;
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pdsch_pdu_rel15->BWPSize = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
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pdsch_pdu_rel15->BWPStart = NRRIV2PRBOFFSET(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
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pdsch_pdu_rel15->BWPSize = BWPSize;
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pdsch_pdu_rel15->BWPStart = BWPStart;
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pdsch_pdu_rel15->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing;
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pdsch_pdu_rel15->CyclicPrefix = 0;
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pdsch_pdu_rel15->NrOfCodewords = 1;
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pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcsIndex,0);
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pdsch_pdu_rel15->qamModOrder[0] = 2;
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pdsch_pdu_rel15->mcsIndex[0] = mcsIndex;
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if (bwp->bwp_Dedicated->pdsch_Config->choice.setup->mcs_Table == NULL)
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pdsch_pdu_rel15->mcsTable[0] = 0;
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else{
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@@ -929,7 +942,6 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
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else
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pdsch_pdu_rel15->mcsTable[0] = 2;
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}
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pdsch_pdu_rel15->rvIndex[0] = 0;
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pdsch_pdu_rel15->dataScramblingId = *scc->physCellId;
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pdsch_pdu_rel15->nrOfLayers = 1;
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@@ -941,8 +953,8 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
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pdsch_pdu_rel15->numDmrsCdmGrpsNoData = 2;
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pdsch_pdu_rel15->dmrsPorts = 1;
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pdsch_pdu_rel15->resourceAlloc = 1;
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pdsch_pdu_rel15->rbStart = 0;
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pdsch_pdu_rel15->rbSize = 6;
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pdsch_pdu_rel15->rbStart = rbStart;
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pdsch_pdu_rel15->rbSize = rbSize;
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pdsch_pdu_rel15->VRBtoPRBMapping = 0;
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for (int i=0; i<bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.count; i++) {
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@@ -1011,17 +1023,6 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
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pdsch_pdu_rel15->BWPSize,
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nr_mac->sched_ctrlCommon->active_bwp->bwp_Id);
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// Program UL processing for Msg3
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NR_BWP_Uplink_t *ubwp=ra->secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[ra->bwp_id-1];
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nr_get_Msg3alloc(module_idP, CC_id, scc, ubwp, slotP, frameP, ra);
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LOG_I(MAC, "Frame %d, Subframe %d: Setting Msg3 reception for Frame %d Subframe %d\n", frameP, slotP, ra->Msg3_frame, ra->Msg3_slot);
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nr_add_msg3(module_idP, CC_id, frameP, slotP);
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ra->state = WAIT_Msg3;
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LOG_I(MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: RA state %d\n", module_idP, frameP, slotP, ra->state);
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x_Overhead = 0;
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nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead, pdsch_pdu_rel15->numDmrsCdmGrpsNoData, dci_payload.tb_scaling);
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// DL TX request
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nfapi_nr_pdu_t *tx_req = &nr_mac->TX_req[CC_id].pdu_list[nr_mac->TX_req[CC_id].Number_of_PDUs];
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tx_req->PDU_length = pdsch_pdu_rel15->TBSize[0];
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@@ -1031,16 +1032,25 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
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nr_mac->TX_req[CC_id].SFN = frameP;
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nr_mac->TX_req[CC_id].Number_of_PDUs++;
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nr_mac->TX_req[CC_id].Slot = slotP;
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memcpy((void*)&tx_req->TLVs[0].value.direct[0], (void*)&cc[CC_id].RAR_pdu.payload[0], tx_req->TLVs[0].length);
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// Program UL processing for Msg3
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NR_BWP_Uplink_t *ubwp=ra->secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[ra->bwp_id-1];
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nr_get_Msg3alloc(module_idP, CC_id, scc, ubwp, slotP, frameP, ra);
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LOG_I(MAC, "Frame %d, Subframe %d: Setting RA-Msg3 reception for Frame %d Subframe %d\n", frameP, slotP, ra->Msg3_frame, ra->Msg3_slot);
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nr_add_msg3(module_idP, CC_id, frameP, slotP, ra, (uint8_t *) &tx_req->TLVs[0].value.direct[0]);
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ra->state = WAIT_Msg3;
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LOG_I(MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: RA state %d\n", module_idP, frameP, slotP, ra->state);
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x_Overhead = 0;
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nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, x_Overhead, pdsch_pdu_rel15->numDmrsCdmGrpsNoData, dci_payload.tb_scaling);
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T(T_GNB_MAC_DL_RAR_PDU_WITH_DATA, T_INT(module_idP), T_INT(CC_id),
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T_INT(ra->RA_rnti), T_INT(frameP), T_INT(slotP), T_INT(0) /* harq pid, meaningful? */,
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|
|
T_BUFFER(&cc[CC_id].RAR_pdu.payload[0], tx_req->TLVs[0].length));
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T_INT(ra->RA_rnti), T_INT(frameP), T_INT(slotP), T_INT(0),
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T_BUFFER(&tx_req->TLVs[0].value.direct[0], tx_req->TLVs[0].length));
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// mark the corresponding RBs as used
|
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|
|
uint16_t *vrb_map = cc[CC_id].vrb_map;
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|
|
for (int rb = 0; rb < pdsch_pdu_rel15->rbSize; rb++) {
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|
|
vrb_map[rb + pdsch_pdu_rel15->rbStart] = 1;
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|
|
// Mark the corresponding RBs as used
|
|
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|
|
for (int rb = 0; rb < rbSize; rb++) {
|
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|
|
vrb_map[rb + rbStart] = 1;
|
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|
|
|
}
|
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|
|
}
|
|
|
|
|
}
|
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|
|
@@ -1124,10 +1134,7 @@ void nr_generate_Msg4(module_id_t module_idP,
|
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|
|
|
|
|
|
|
|
LOG_I(NR_MAC,"[gNB %d] [RAPROC] CC_id %d Frame %d, slotP %d: Generating RA-Msg4 DCI, state %d\n", module_idP, CC_id, frameP, slotP, ra->state);
|
|
|
|
|
|
|
|
|
|
// This code from this point on will not work on initialBWP or CORESET0
|
|
|
|
|
AssertFatal(ra->bwp_id>0,"cannot work on initialBWP for now\n");
|
|
|
|
|
AssertFatal(ra->secondaryCellGroup, "no secondaryCellGroup for RNTI %04x\n", ra->rnti);
|
|
|
|
|
|
|
|
|
|
AssertFatal(ra->secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1,
|
|
|
|
|
"downlinkBWP_ToAddModList has %d BWP!\n",
|
|
|
|
|
ra->secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count);
|
|
|
|
@@ -1254,7 +1261,7 @@ void nr_generate_Msg4(module_id_t module_idP,
|
|
|
|
|
nr_mac->TX_req[CC_id].Slot = slotP;
|
|
|
|
|
memcpy(tx_req->TLVs[0].value.direct, payload, tx_req->TLVs[0].length);
|
|
|
|
|
|
|
|
|
|
// mark the corresponding RBs as used
|
|
|
|
|
// Mark the corresponding RBs as used
|
|
|
|
|
uint16_t *vrb_map = cc[CC_id].vrb_map;
|
|
|
|
|
for (int rb = 0; rb < pdsch_pdu_rel15->rbSize; rb++) {
|
|
|
|
|
vrb_map[rb + pdsch_pdu_rel15->rbStart] = 1;
|
|
|
|
|