Fix REG to CCE mapping at gNB
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@@ -102,8 +102,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
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LOG_D(PHY, "Coreset rb_offset %d, nb_rb %d\n",rb_offset,n_rb);
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LOG_D(PHY, "Coreset starting subcarrier %d on symbol %d (%d symbols)\n", cset_start_sc, cset_start_symb, cset_nsymb);
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// DMRS length is per OFDM symbol
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uint32_t dmrs_length = (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED)?
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(n_rb*6) : (pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*36/cset_nsymb); //2(QPSK)*3(per RB)*6(REG per CCE)
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uint32_t dmrs_length = n_rb*6; //2(QPSK)*3(per RB)*6(REG per CCE)
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uint32_t encoded_length = pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*108; //2(QPSK)*9(per RB)*6(REG per CCE)
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LOG_D(PHY, "DMRS length per symbol %d\t DCI encoded length %d (precoder_granularity %d,reg_mapping %d)\n", dmrs_length, encoded_length,pdcch_pdu_rel15->precoderGranularity,pdcch_pdu_rel15->CceRegMappingType);
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dmrs_length += rb_offset*6; // To accommodate more DMRS symbols in case of rb offset
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@@ -164,62 +163,81 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
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printf("i %d mod_dci %d %d\n", i, mod_dci[i<<1], mod_dci[(i<<1)+1] );
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#endif
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/// Resource mapping
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if (cset_start_sc >= frame_parms.ofdm_symbol_size)
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cset_start_sc -= frame_parms.ofdm_symbol_size;
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/*Reorder REG list for a freq first mapping*/
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uint8_t reg_idx0 = pdcch_pdu_rel15->dci_pdu.CceIndex[d]*NR_NB_REG_PER_CCE;
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uint8_t nb_regs = pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*NR_NB_REG_PER_CCE;
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// Get cce_list indices by reg_idx in ascending order
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int reg_list_index = 0;
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int reg_list_order[MAX_DCI_CORESET] = {};
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for (int p = 0; p < MAX_DCI_CORESET; p++) {
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for(int p2 = 0; p2 < pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]; p2++) {
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if(gNB->cce_list[d][p2].reg_list[0].reg_idx == p * NR_NB_REG_PER_CCE) {
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reg_list_order[reg_list_index] = p2;
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reg_list_index++;
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break;
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}
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}
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}
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/*Mapping the encoded DCI along with the DMRS */
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for (int reg_idx=reg_idx0; reg_idx<(nb_regs+reg_idx0); reg_idx++) {
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k = cset_start_sc + (12*reg_idx/cset_nsymb);
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if (k >= frame_parms.ofdm_symbol_size)
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k -= frame_parms.ofdm_symbol_size;
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l = cset_start_symb + ((reg_idx/cset_nsymb)%cset_nsymb);
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// dmrs index depends on reference point for k according to 38.211 7.4.1.3.2
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if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG)
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dmrs_idx = (reg_idx/cset_nsymb)*3;
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else
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dmrs_idx = ((reg_idx/cset_nsymb)+rb_offset)*3;
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k_prime = 0;
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for (int m=0; m<NR_NB_SC_PER_RB; m++) {
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if ( m == (k_prime<<2)+1) { // DMRS if not already mapped
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//if (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED) {
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((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = (amp * mod_dmrs[l][dmrs_idx<<1]) >> 15;
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((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (amp * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15;
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for (int cce_count = 0; cce_count < pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]; cce_count ++) {
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int8_t cce_idx = reg_list_order[cce_count];
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for (int reg_in_cce_idx = 0; reg_in_cce_idx < NR_NB_REG_PER_CCE; reg_in_cce_idx++) {
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k = cset_start_sc + gNB->cce_list[d][cce_idx].reg_list[reg_in_cce_idx].start_sc_idx;
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if (k >= frame_parms.ofdm_symbol_size)
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k -= frame_parms.ofdm_symbol_size;
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l = cset_start_symb + gNB->cce_list[d][cce_idx].reg_list[reg_in_cce_idx].symb_idx;
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// dmrs index depends on reference point for k according to 38.211 7.4.1.3.2
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if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG)
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dmrs_idx =gNB->cce_list[d][cce_idx].reg_list[reg_in_cce_idx].reg_idx * 3;
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else
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dmrs_idx = (gNB->cce_list[d][cce_idx].reg_list[reg_in_cce_idx].reg_idx + rb_offset) * 3;
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k_prime = 0;
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for (int m = 0; m < NR_NB_SC_PER_RB; m++) {
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if (m == (k_prime << 2) + 1) { // DMRS if not already mapped
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((int16_t *) txdataF)[(l * frame_parms.ofdm_symbol_size + k) << 1] =
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(amp * mod_dmrs[l][dmrs_idx << 1]) >> 15;
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((int16_t *) txdataF)[((l * frame_parms.ofdm_symbol_size + k) << 1) + 1] =
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(amp * mod_dmrs[l][(dmrs_idx << 1) + 1]) >> 15;
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#ifdef DEBUG_PDCCH_DMRS
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printf("PDCCH DMRS: l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1],
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((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]);
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#endif
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dmrs_idx++;
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//}
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k_prime++;
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} else { // DCI payload
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((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = (amp * mod_dci[dci_idx<<1]) >> 15;
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((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (amp * mod_dci[(dci_idx<<1) + 1]) >> 15;
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dmrs_idx++;
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k_prime++;
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} else { // DCI payload
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((int16_t *) txdataF)[(l * frame_parms.ofdm_symbol_size + k) << 1] = (amp * mod_dci[dci_idx << 1]) >> 15;
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((int16_t *) txdataF)[((l * frame_parms.ofdm_symbol_size + k) << 1) + 1] =
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(amp * mod_dci[(dci_idx << 1) + 1]) >> 15;
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#ifdef DEBUG_DCI
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printf("PDCCH: l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1],
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((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]);
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#endif
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dci_idx++;
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}
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k++;
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if (k >= frame_parms.ofdm_symbol_size)
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k -= frame_parms.ofdm_symbol_size;
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} // m
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} // reg_idx
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dci_idx++;
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}
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k++;
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if (k >= frame_parms.ofdm_symbol_size)
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k -= frame_parms.ofdm_symbol_size;
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} // m
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} // reg_in_cce_idx
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} // cce_count
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LOG_I(PHY, "DCI: payloadSize = %d | payload = %llx\n",
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*pdcch_pdu_rel15->dci_pdu.PayloadSizeBits,*(unsigned long long*)pdcch_pdu_rel15->dci_pdu.Payload);
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@@ -987,7 +987,7 @@ int8_t nr_ue_decode_mib(module_id_t module_id,
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LOG_D(MAC,"cell barred (0=barred,1=notBarred): %d\n", (int)mac->mib->cellBarred);
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LOG_D(MAC,"intra frequency reselection (0=allowed,1=notAllowed): %d\n", (int)mac->mib->intraFreqReselection);
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LOG_D(MAC,"half frame bit(extra bits): %d\n", (int)half_frame_bit);
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LOG_I(MAC,"ssb index(extra bits): %d\n", (int)ssb_index);
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LOG_D(MAC,"ssb index(extra bits): %d\n", (int)ssb_index);
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//storing ssb index in the mac structure
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mac->mib_ssb = ssb_index;
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@@ -420,7 +420,51 @@ uint8_t do_SIB1_NR(rrc_gNB_carrier_data_t *carrier,
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sib1->servingCellConfigCommon->uplinkConfigCommon->initialUplinkBWP.pucch_ConfigCommon = configuration->scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon;
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sib1->servingCellConfigCommon->n_TimingAdvanceOffset = configuration->scc->n_TimingAdvanceOffset;
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sib1->servingCellConfigCommon->ssb_PositionsInBurst.inOneGroup = configuration->scc->ssb_PositionsInBurst->choice.shortBitmap;
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sib1->servingCellConfigCommon->ssb_PositionsInBurst.inOneGroup.buf = calloc(1, sizeof(uint8_t));
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uint8_t bitmap8,temp_bitmap=0;
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switch (configuration->scc->ssb_PositionsInBurst->present) {
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case NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_shortBitmap:
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sib1->servingCellConfigCommon->ssb_PositionsInBurst.inOneGroup = configuration->scc->ssb_PositionsInBurst->choice.shortBitmap;
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break;
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case NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_mediumBitmap:
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sib1->servingCellConfigCommon->ssb_PositionsInBurst.inOneGroup = configuration->scc->ssb_PositionsInBurst->choice.mediumBitmap;
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break;
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/*
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groupPresence: This field is present when maximum number of SS/PBCH blocks per half frame equals to 64 as defined in TS 38.213 [13], clause 4.1.
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The first/leftmost bit corresponds to the SS/PBCH index 0-7, the second bit corresponds to SS/PBCH block 8-15, and so on.
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Value 0 in the bitmap indicates that the SSBs according to inOneGroup are absent. Value 1 indicates that the SS/PBCH blocks are transmitted in accordance with inOneGroup.
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inOneGroup: When maximum number of SS/PBCH blocks per half frame equals to 64 as defined in TS 38.213 [13], clause 4.1, all 8 bit are valid;
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The first/ leftmost bit corresponds to the first SS/PBCH block index in the group (i.e., to SSB index 0, 8, and so on); the second bit corresponds to the second SS/PBCH block index in the group
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(i.e., to SSB index 1, 9, and so on), and so on. Value 0 in the bitmap indicates that the corresponding SS/PBCH block is not transmitted while value 1 indicates that the corresponding SS/PBCH block is transmitted.
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*/
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case NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_longBitmap:
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sib1->servingCellConfigCommon->ssb_PositionsInBurst.inOneGroup.size = 1;
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sib1->servingCellConfigCommon->ssb_PositionsInBurst.inOneGroup.bits_unused = 0;
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sib1->servingCellConfigCommon->ssb_PositionsInBurst.groupPresence = calloc(1, sizeof(BIT_STRING_t));
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memset(sib1->servingCellConfigCommon->ssb_PositionsInBurst.groupPresence, 0, sizeof(BIT_STRING_t));
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sib1->servingCellConfigCommon->ssb_PositionsInBurst.groupPresence->size = 1;
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sib1->servingCellConfigCommon->ssb_PositionsInBurst.groupPresence->bits_unused = 0;
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sib1->servingCellConfigCommon->ssb_PositionsInBurst.groupPresence->buf = calloc(1, sizeof(uint8_t));
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sib1->servingCellConfigCommon->ssb_PositionsInBurst.groupPresence->buf[0] = 0;
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for (int i=0; i<8; i++){
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bitmap8 = configuration->scc->ssb_PositionsInBurst->choice.longBitmap.buf[i];
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if (bitmap8!=0){
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if(temp_bitmap==0)
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temp_bitmap = bitmap8;
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else
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AssertFatal(temp_bitmap==bitmap8,"For longBitmap the groups of 8 SSBs containing at least 1 transmitted SSB should be all the same\n");
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sib1->servingCellConfigCommon->ssb_PositionsInBurst.inOneGroup.buf[0] = bitmap8;
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sib1->servingCellConfigCommon->ssb_PositionsInBurst.groupPresence->buf[0] |= 1<<(7-i);
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}
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}
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break;
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default:
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AssertFatal(false,"ssb_PositionsInBurst not present\n");
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break;
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}
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sib1->servingCellConfigCommon->ssb_PeriodicityServingCell = *configuration->scc->ssb_periodicityServingCell;
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sib1->servingCellConfigCommon->tdd_UL_DL_ConfigurationCommon = CALLOC(1,sizeof(struct NR_TDD_UL_DL_ConfigCommon));
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sib1->servingCellConfigCommon->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing = configuration->scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing;
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