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This commit is contained in:
francescomani
2026-01-16 00:43:00 +01:00
parent b64c4e5708
commit 7173bb6cac
1 changed files with 92 additions and 82 deletions
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openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
+38 -28
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@@ -3560,26 +3560,23 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
uint32_t ssb_period, uint32_t ssb_period,
uint32_t ssb_offset_point_a) uint32_t ssb_offset_point_a)
{ {
NR_SubcarrierSpacing_t scs_pdcch;
channel_bandwidth_t min_channel_bw;
// according to Table 5.3.5-1 in 38.104 // according to Table 5.3.5-1 in 38.104
// band 79 is the only one which minimum is 40 // band 79 is the only one which minimum is 40
// for all the other channels it is either 10 or 5 // for all the other channels it is either 10 or 5
// and there is no difference between the two for this implementation so it is set it to 10 // and there is no difference between the two for this implementation so it is set it to 10
channel_bandwidth_t min_channel_bw;
if (nr_band == 79) if (nr_band == 79)
min_channel_bw = bw_40MHz; min_channel_bw = bw_40MHz;
else else
min_channel_bw = bw_10MHz; min_channel_bw = bw_10MHz;
NR_SubcarrierSpacing_t scs_pdcch;
if (frequency_range == FR2) { if (frequency_range == FR2) {
if(mib->subCarrierSpacingCommon == NR_MIB__subCarrierSpacingCommon_scs15or60) if(mib->subCarrierSpacingCommon == NR_MIB__subCarrierSpacingCommon_scs15or60)
scs_pdcch = NR_SubcarrierSpacing_kHz60; scs_pdcch = NR_SubcarrierSpacing_kHz60;
else else
scs_pdcch = NR_SubcarrierSpacing_kHz120; scs_pdcch = NR_SubcarrierSpacing_kHz120;
} } else {
else {
frequency_range = FR1; frequency_range = FR1;
if(mib->subCarrierSpacingCommon == NR_MIB__subCarrierSpacingCommon_scs15or60) if(mib->subCarrierSpacingCommon == NR_MIB__subCarrierSpacingCommon_scs15or60)
scs_pdcch = NR_SubcarrierSpacing_kHz15; scs_pdcch = NR_SubcarrierSpacing_kHz15;
@@ -3591,7 +3588,6 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
type0_PDCCH_CSS_config->frame = frameP; type0_PDCCH_CSS_config->frame = frameP;
uint8_t ssb_slot = ssb_start_symbol / 14; uint8_t ssb_slot = ssb_start_symbol / 14;
uint32_t is_condition_A = (ssb_subcarrier_offset == 0); // 38.213 ch.13 uint32_t is_condition_A = (ssb_subcarrier_offset == 0); // 38.213 ch.13
uint32_t index_4msb = (mib->pdcch_ConfigSIB1.controlResourceSetZero); uint32_t index_4msb = (mib->pdcch_ConfigSIB1.controlResourceSetZero);
uint32_t index_4lsb = (mib->pdcch_ConfigSIB1.searchSpaceZero); uint32_t index_4lsb = (mib->pdcch_ConfigSIB1.searchSpaceZero);
@@ -3599,7 +3595,12 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
type0_PDCCH_CSS_config->num_rbs = -1; type0_PDCCH_CSS_config->num_rbs = -1;
type0_PDCCH_CSS_config->num_symbols = -1; type0_PDCCH_CSS_config->num_symbols = -1;
type0_PDCCH_CSS_config->rb_offset = -1; type0_PDCCH_CSS_config->rb_offset = -1;
LOG_D(NR_MAC,"NR_SubcarrierSpacing_kHz30 %d, scs_ssb %d, scs_pdcch %d, min_chan_bw %d\n",(int)NR_SubcarrierSpacing_kHz30,(int)scs_ssb,(int)scs_pdcch,min_channel_bw); LOG_D(NR_MAC,
"NR_SubcarrierSpacing_kHz30 %d, scs_ssb %d, scs_pdcch %d, min_chan_bw %d\n",
(int)NR_SubcarrierSpacing_kHz30,
(int)scs_ssb,
(int)scs_pdcch,
min_channel_bw);
// type0-pdcch coreset // type0-pdcch coreset
switch(((int)scs_ssb << 3) | (int)scs_pdcch) { switch(((int)scs_ssb << 3) | (int)scs_pdcch) {
@@ -3610,7 +3611,6 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
type0_PDCCH_CSS_config->num_symbols = table_38213_13_1_c3[index_4msb]; type0_PDCCH_CSS_config->num_symbols = table_38213_13_1_c3[index_4msb];
type0_PDCCH_CSS_config->rb_offset = table_38213_13_1_c4[index_4msb]; type0_PDCCH_CSS_config->rb_offset = table_38213_13_1_c4[index_4msb];
break; break;
case (NR_SubcarrierSpacing_kHz15 << 3) | NR_SubcarrierSpacing_kHz30: case (NR_SubcarrierSpacing_kHz15 << 3) | NR_SubcarrierSpacing_kHz30:
AssertFatal(index_4msb < 14, "38.213 Table 13-2 4 MSB out of range\n"); AssertFatal(index_4msb < 14, "38.213 Table 13-2 4 MSB out of range\n");
type0_PDCCH_CSS_config->type0_pdcch_ss_mux_pattern = 1; type0_PDCCH_CSS_config->type0_pdcch_ss_mux_pattern = 1;
@@ -3618,7 +3618,6 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
type0_PDCCH_CSS_config->num_symbols = table_38213_13_2_c3[index_4msb]; type0_PDCCH_CSS_config->num_symbols = table_38213_13_2_c3[index_4msb];
type0_PDCCH_CSS_config->rb_offset = table_38213_13_2_c4[index_4msb]; type0_PDCCH_CSS_config->rb_offset = table_38213_13_2_c4[index_4msb];
break; break;
case (NR_SubcarrierSpacing_kHz30 << 3) | NR_SubcarrierSpacing_kHz15: case (NR_SubcarrierSpacing_kHz30 << 3) | NR_SubcarrierSpacing_kHz15:
if((min_channel_bw & bw_5MHz) | (min_channel_bw & bw_10MHz)) { if((min_channel_bw & bw_5MHz) | (min_channel_bw & bw_10MHz)) {
AssertFatal(index_4msb < 9, "38.213 Table 13-3 4 MSB out of range\n"); AssertFatal(index_4msb < 9, "38.213 Table 13-3 4 MSB out of range\n");
@@ -3633,9 +3632,7 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
type0_PDCCH_CSS_config->num_symbols = table_38213_13_5_c3[index_4msb]; type0_PDCCH_CSS_config->num_symbols = table_38213_13_5_c3[index_4msb];
type0_PDCCH_CSS_config->rb_offset = table_38213_13_5_c4[index_4msb]; type0_PDCCH_CSS_config->rb_offset = table_38213_13_5_c4[index_4msb];
} else{ ; } } else{ ; }
break; break;
case (NR_SubcarrierSpacing_kHz30 << 3) | NR_SubcarrierSpacing_kHz30: case (NR_SubcarrierSpacing_kHz30 << 3) | NR_SubcarrierSpacing_kHz30:
if((min_channel_bw & bw_5MHz) | (min_channel_bw & bw_10MHz)) { if((min_channel_bw & bw_5MHz) | (min_channel_bw & bw_10MHz)) {
type0_PDCCH_CSS_config->type0_pdcch_ss_mux_pattern = 1; type0_PDCCH_CSS_config->type0_pdcch_ss_mux_pattern = 1;
@@ -3651,7 +3648,6 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
type0_PDCCH_CSS_config->rb_offset = table_38213_13_6_c4[index_4msb]; type0_PDCCH_CSS_config->rb_offset = table_38213_13_6_c4[index_4msb];
} else{ ; } } else{ ; }
break; break;
case (NR_SubcarrierSpacing_kHz120 << 3) | NR_SubcarrierSpacing_kHz60: case (NR_SubcarrierSpacing_kHz120 << 3) | NR_SubcarrierSpacing_kHz60:
AssertFatal(index_4msb < 12, "38.213 Table 13-7 4 MSB out of range\n"); AssertFatal(index_4msb < 12, "38.213 Table 13-7 4 MSB out of range\n");
if (index_4msb < 8) { if (index_4msb < 8) {
@@ -3668,7 +3664,6 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
type0_PDCCH_CSS_config->rb_offset = table_38213_13_7_c4[index_4msb]; type0_PDCCH_CSS_config->rb_offset = table_38213_13_7_c4[index_4msb];
} }
break; break;
case (NR_SubcarrierSpacing_kHz120 << 3) | NR_SubcarrierSpacing_kHz120: case (NR_SubcarrierSpacing_kHz120 << 3) | NR_SubcarrierSpacing_kHz120:
AssertFatal(index_4msb < 8, "38.213 Table 13-8 4 MSB out of range\n"); AssertFatal(index_4msb < 8, "38.213 Table 13-8 4 MSB out of range\n");
if (index_4msb < 4) { if (index_4msb < 4) {
@@ -3685,7 +3680,6 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
type0_PDCCH_CSS_config->rb_offset = table_38213_13_8_c4[index_4msb]; type0_PDCCH_CSS_config->rb_offset = table_38213_13_8_c4[index_4msb];
} }
break; break;
case (NR_SubcarrierSpacing_kHz240 << 3) | NR_SubcarrierSpacing_kHz60: case (NR_SubcarrierSpacing_kHz240 << 3) | NR_SubcarrierSpacing_kHz60:
AssertFatal(index_4msb < 4, "38.213 Table 13-9 4 MSB out of range\n"); AssertFatal(index_4msb < 4, "38.213 Table 13-9 4 MSB out of range\n");
type0_PDCCH_CSS_config->type0_pdcch_ss_mux_pattern = 1; type0_PDCCH_CSS_config->type0_pdcch_ss_mux_pattern = 1;
@@ -3693,7 +3687,6 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
type0_PDCCH_CSS_config->num_symbols = table_38213_13_9_c3[index_4msb]; type0_PDCCH_CSS_config->num_symbols = table_38213_13_9_c3[index_4msb];
type0_PDCCH_CSS_config->rb_offset = table_38213_13_9_c4[index_4msb]; type0_PDCCH_CSS_config->rb_offset = table_38213_13_9_c4[index_4msb];
break; break;
case (NR_SubcarrierSpacing_kHz240 << 3) | NR_SubcarrierSpacing_kHz120: case (NR_SubcarrierSpacing_kHz240 << 3) | NR_SubcarrierSpacing_kHz120:
AssertFatal(index_4msb < 8, "38.213 Table 13-10 4 MSB out of range\n"); AssertFatal(index_4msb < 8, "38.213 Table 13-10 4 MSB out of range\n");
if (index_4msb < 4) { if (index_4msb < 4) {
@@ -3708,18 +3701,30 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
} else { } else {
type0_PDCCH_CSS_config->rb_offset = table_38213_13_10_c4[index_4msb]; type0_PDCCH_CSS_config->rb_offset = table_38213_13_10_c4[index_4msb];
} }
break; break;
default: default:
LOG_E(NR_MAC,"NR_SubcarrierSpacing_kHz30 %d, scs_ssb %d, scs_pdcch %d, min_chan_bw %d\n",NR_SubcarrierSpacing_kHz30,(int)scs_ssb,(int)scs_pdcch,min_channel_bw); LOG_E(NR_MAC,
"NR_SubcarrierSpacing_kHz30 %d, scs_ssb %d, scs_pdcch %d, min_chan_bw %d\n",
NR_SubcarrierSpacing_kHz30,
(int)scs_ssb,
(int)scs_pdcch,
min_channel_bw);
break; break;
} }
LOG_D(NR_MAC,"Coreset0: index_4msb=%d, num_rbs=%d, num_symb=%d, rb_offset=%d\n", LOG_D(NR_MAC,
index_4msb,type0_PDCCH_CSS_config->num_rbs,type0_PDCCH_CSS_config->num_symbols,type0_PDCCH_CSS_config->rb_offset ); "Coreset0: index_4msb=%d, num_rbs=%d, num_symb=%d, rb_offset=%d\n",
index_4msb,
type0_PDCCH_CSS_config->num_rbs,
type0_PDCCH_CSS_config->num_symbols,
type0_PDCCH_CSS_config->rb_offset);
AssertFatal(type0_PDCCH_CSS_config->num_rbs != -1, "Type0 PDCCH coreset num_rbs undefined, index_4msb=%d, min_channel_bw %d, scs_ssb %d, scs_pdcch %d\n",index_4msb,min_channel_bw,(int)scs_ssb,(int)scs_pdcch); AssertFatal(type0_PDCCH_CSS_config->num_rbs != -1,
"Type0 PDCCH coreset num_rbs undefined, index_4msb=%d, min_channel_bw %d, scs_ssb %d, scs_pdcch %d\n",
index_4msb,
min_channel_bw,
(int)scs_ssb,
(int)scs_pdcch);
AssertFatal(type0_PDCCH_CSS_config->num_symbols != -1, "Type0 PDCCH coreset num_symbols undefined"); AssertFatal(type0_PDCCH_CSS_config->num_symbols != -1, "Type0 PDCCH coreset num_symbols undefined");
AssertFatal(type0_PDCCH_CSS_config->rb_offset != -1, "Type0 PDCCH coreset rb_offset undefined"); AssertFatal(type0_PDCCH_CSS_config->rb_offset != -1, "Type0 PDCCH coreset rb_offset undefined");
@@ -3796,9 +3801,9 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
case 3: case 3:
type0_PDCCH_CSS_config->first_symbol_index = 7; type0_PDCCH_CSS_config->first_symbol_index = 7;
break; break;
default: break; default:
break;
} }
} else if((scs_ssb == NR_SubcarrierSpacing_kHz240) && (scs_pdcch == NR_SubcarrierSpacing_kHz120)) { } else if((scs_ssb == NR_SubcarrierSpacing_kHz240) && (scs_pdcch == NR_SubcarrierSpacing_kHz120)) {
// 38.213 Table 13-14 // 38.213 Table 13-14
AssertFatal(index_4lsb == 0, "38.213 Table 13-14 4 LSB out of range\n"); AssertFatal(index_4lsb == 0, "38.213 Table 13-14 4 LSB out of range\n");
@@ -3832,7 +3837,8 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
case 7: case 7:
type0_PDCCH_CSS_config->first_symbol_index = 1; type0_PDCCH_CSS_config->first_symbol_index = 1;
break; break;
default: break; default:
break;
} }
} else { ; } } else { ; }
// 38.213 chapter 13: over one slot // 38.213 chapter 13: over one slot
@@ -3862,7 +3868,8 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
case 3: case 3:
type0_PDCCH_CSS_config->first_symbol_index = 6; type0_PDCCH_CSS_config->first_symbol_index = 6;
break; break;
default: break; default:
break;
} }
} else { ; } } else { ; }
// 38.213 chapter 13: over one slot // 38.213 chapter 13: over one slot
@@ -3873,8 +3880,11 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
AssertFatal(type0_PDCCH_CSS_config->slot != UINT_MAX, "type0_PDCCH_CSS_config slot not configured"); AssertFatal(type0_PDCCH_CSS_config->slot != UINT_MAX, "type0_PDCCH_CSS_config slot not configured");
type0_PDCCH_CSS_config->cset_start_rb = ssb_offset_point_a - type0_PDCCH_CSS_config->rb_offset; type0_PDCCH_CSS_config->cset_start_rb = ssb_offset_point_a - type0_PDCCH_CSS_config->rb_offset;
AssertFatal(type0_PDCCH_CSS_config->cset_start_rb >= 0, "Invalid CSET0 start PRB %d SSB offset point A %d RB offset %d\n", AssertFatal(type0_PDCCH_CSS_config->cset_start_rb >= 0,
type0_PDCCH_CSS_config->cset_start_rb, ssb_offset_point_a, type0_PDCCH_CSS_config->rb_offset); "Invalid CSET0 start PRB %d SSB offset point A %d RB offset %d\n",
type0_PDCCH_CSS_config->cset_start_rb,
ssb_offset_point_a,
type0_PDCCH_CSS_config->rb_offset);
} }
void fill_coresetZero(NR_ControlResourceSet_t *coreset0, NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config) void fill_coresetZero(NR_ControlResourceSet_t *coreset0, NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config)