fixes to make multiplexing pattern 2 and 3 work for Type0-PDCCH CSS
Correct how the slot for SIB1 is computed in case of MUX pattern 2 and 3. Renamed n_0 to slot for clarity. n_c was never used outside of the function, so remove it where it is not used.
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@@ -472,8 +472,7 @@ typedef struct Type0_PDCCH_CSS_config_s {
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uint32_t type0_pdcch_ss_mux_pattern;
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uint16_t frame;
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int sfn_c;
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uint32_t n_c;
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uint32_t n_0;
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uint32_t slot;
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uint32_t first_symbol_index;
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uint32_t search_space_duration;
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uint32_t search_space_frame_period; // in slots
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@@ -3726,8 +3726,8 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
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// type0-pdcch search space
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float big_o = 0.0f;
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float big_m = 0.0f;
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type0_PDCCH_CSS_config->sfn_c = -1; // only valid for mux=1
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type0_PDCCH_CSS_config->n_c = UINT_MAX;
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type0_PDCCH_CSS_config->sfn_c = 0; // only valid for mux=1
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type0_PDCCH_CSS_config->slot = UINT_MAX;
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type0_PDCCH_CSS_config->first_symbol_index = UINT_MAX;
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type0_PDCCH_CSS_config->search_space_duration = 0; // element of search space
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// 38.213 table 10.1-1
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@@ -3738,9 +3738,9 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
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big_o = table_38213_13_11_c1[index_4lsb];
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big_m = table_38213_13_11_c3[index_4lsb];
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uint32_t temp = (uint32_t)(big_o*(1<<scs_pdcch)) + (uint32_t)(type0_PDCCH_CSS_config->ssb_index*big_m);
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type0_PDCCH_CSS_config->n_c = temp / num_slot_per_frame;
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type0_PDCCH_CSS_config->sfn_c = type0_PDCCH_CSS_config->n_c % 2;
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uint32_t temp = (uint32_t)(big_o * (1 << scs_pdcch)) + (uint32_t)(type0_PDCCH_CSS_config->ssb_index * big_m);
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type0_PDCCH_CSS_config->slot = temp % num_slot_per_frame;
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type0_PDCCH_CSS_config->sfn_c = (temp / num_slot_per_frame) % 2;
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if((index_4lsb == 1 || index_4lsb == 3 || index_4lsb == 5 || index_4lsb == 7) && (type0_PDCCH_CSS_config->ssb_index&1)){
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type0_PDCCH_CSS_config->first_symbol_index = type0_PDCCH_CSS_config->num_symbols;
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@@ -3757,9 +3757,9 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
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big_o = table_38213_13_12_c1[index_4lsb];
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big_m = table_38213_13_12_c3[index_4lsb];
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uint32_t temp = (uint32_t)(big_o*(1<<scs_pdcch)) + (uint32_t)(type0_PDCCH_CSS_config->ssb_index*big_m);
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type0_PDCCH_CSS_config->n_c = temp / num_slot_per_frame;
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type0_PDCCH_CSS_config->sfn_c = type0_PDCCH_CSS_config->n_c % 2;
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uint32_t temp = (uint32_t)(big_o * (1 << scs_pdcch)) + (uint32_t)(type0_PDCCH_CSS_config->ssb_index * big_m);
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type0_PDCCH_CSS_config->slot = temp % num_slot_per_frame;
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type0_PDCCH_CSS_config->sfn_c = (temp / num_slot_per_frame) % 2;
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if((index_4lsb == 1 || index_4lsb == 3 || index_4lsb == 5 || index_4lsb == 10) && (type0_PDCCH_CSS_config->ssb_index&1)){
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type0_PDCCH_CSS_config->first_symbol_index = 7;
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@@ -3782,7 +3782,7 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
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AssertFatal(index_4lsb == 0, "38.213 Table 13-13 4 LSB out of range\n");
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// PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot
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// sfn_c = SFN_C_EQ_SFN_SSB;
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type0_PDCCH_CSS_config->n_c = ssb_slot;
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type0_PDCCH_CSS_config->slot = ssb_slot;
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switch(type0_PDCCH_CSS_config->ssb_index & 0x3){ // ssb_index(i) mod 4
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case 0:
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type0_PDCCH_CSS_config->first_symbol_index = 0;
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@@ -3804,7 +3804,7 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
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AssertFatal(index_4lsb == 0, "38.213 Table 13-14 4 LSB out of range\n");
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// PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot
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// sfn_c = SFN_C_EQ_SFN_SSB;
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type0_PDCCH_CSS_config->n_c = ssb_slot;
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type0_PDCCH_CSS_config->slot = ssb_slot;
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switch(type0_PDCCH_CSS_config->ssb_index & 0x7){ // ssb_index(i) mod 8
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case 0:
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type0_PDCCH_CSS_config->first_symbol_index = 0;
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@@ -3820,11 +3820,11 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
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break;
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case 4:
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type0_PDCCH_CSS_config->first_symbol_index = 12;
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type0_PDCCH_CSS_config->n_c = ssb_slot - 1;
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type0_PDCCH_CSS_config->slot = ssb_slot - 1;
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break;
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case 5:
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type0_PDCCH_CSS_config->first_symbol_index = 13;
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type0_PDCCH_CSS_config->n_c = ssb_slot - 1;
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type0_PDCCH_CSS_config->slot = ssb_slot - 1;
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break;
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case 6:
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type0_PDCCH_CSS_config->first_symbol_index = 0;
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@@ -3848,7 +3848,7 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
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AssertFatal(index_4lsb == 0, "38.213 Table 13-15 4 LSB out of range\n");
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// PDCCH monitoring occasions (SFN and slot number) same as SSB frame-slot
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// sfn_c = SFN_C_EQ_SFN_SSB;
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type0_PDCCH_CSS_config->n_c = ssb_slot;
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type0_PDCCH_CSS_config->slot = ssb_slot;
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switch(type0_PDCCH_CSS_config->ssb_index & 0x3){ // ssb_index(i) mod 4
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case 0:
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type0_PDCCH_CSS_config->first_symbol_index = 4;
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@@ -3870,11 +3870,8 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
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// SSB periodicity in slots
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type0_PDCCH_CSS_config->search_space_frame_period = ssb_period * slots_per_frame;
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}
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AssertFatal(type0_PDCCH_CSS_config->slot != UINT_MAX, "type0_PDCCH_CSS_config slot not configured");
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AssertFatal(type0_PDCCH_CSS_config->sfn_c >= 0, "");
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AssertFatal(type0_PDCCH_CSS_config->n_c != UINT_MAX, "");
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type0_PDCCH_CSS_config->n_0 = ((uint32_t)(big_o*(1<<scs_pdcch)) + (uint32_t)(type0_PDCCH_CSS_config->ssb_index*big_m))%num_slot_per_frame;
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type0_PDCCH_CSS_config->cset_start_rb = ssb_offset_point_a - type0_PDCCH_CSS_config->rb_offset;
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AssertFatal(type0_PDCCH_CSS_config->cset_start_rb >= 0, "Invalid CSET0 start PRB %d SSB offset point A %d RB offset %d\n",
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type0_PDCCH_CSS_config->cset_start_rb, ssb_offset_point_a, type0_PDCCH_CSS_config->rb_offset);
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@@ -3950,8 +3947,8 @@ void fill_searchSpaceZero(NR_SearchSpace_t *ss0, int slots_per_frame, NR_Type0_P
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const uint32_t periodicity = type0_PDCCH_CSS_config->search_space_frame_period;
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const uint32_t offset = type0_PDCCH_CSS_config->type0_pdcch_ss_mux_pattern == 1 ?
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type0_PDCCH_CSS_config->n_0 + (slots_per_frame * type0_PDCCH_CSS_config->sfn_c) :
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type0_PDCCH_CSS_config->n_c;
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type0_PDCCH_CSS_config->slot + (slots_per_frame * type0_PDCCH_CSS_config->sfn_c) :
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type0_PDCCH_CSS_config->slot;
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ss0->searchSpaceId = 0;
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*ss0->controlResourceSetId = 0;
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@@ -85,7 +85,7 @@ static void schedule_ssb(frame_t frame,
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dl_config_pdu->ssb_pdu.ssb_pdu_rel15.precoding_and_beamforming.prgs_list[0].dig_bf_interface_list[0].beam_idx = beam_index;
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dl_req->nPDUs++;
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LOG_D(MAC,"Scheduling ssb %d at frame %d and slot %d\n", i_ssb, frame, slot);
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LOG_D(NR_MAC,"Scheduling ssb %d at frame %d and slot %d\n", i_ssb, frame, slot);
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}
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static void fill_ssb_vrb_map(NR_COMMON_channels_t *cc,
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@@ -521,6 +521,19 @@ static bool check_sib1_tda(gNB_MAC_INST *gNB_mac,
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}
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}
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static bool check_frame_sib1(NR_ServingCellConfigCommon_t *scc, NR_Type0_PDCCH_CSS_config_t *type0, int frame)
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{
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if (type0->type0_pdcch_ss_mux_pattern == 1)
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return frame % 2 == type0->sfn_c;
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else {
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long ssb_period = *scc->ssb_periodicityServingCell;
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int ssb_frame_periodicity = 1; // every how many frames SSB are generated
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if (ssb_period > 1) // 0 is every half frame
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ssb_frame_periodicity = 1 << (ssb_period -1);
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return frame % ssb_frame_periodicity == 0;
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}
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}
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void schedule_nr_sib1(module_id_t module_idP,
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frame_t frameP,
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slot_t slotP,
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@@ -553,13 +566,14 @@ void schedule_nr_sib1(module_id_t module_idP,
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NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config = &gNB_mac->type0_PDCCH_CSS_config[i];
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if((frameP % 2 == type0_PDCCH_CSS_config->sfn_c) &&
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(slotP == type0_PDCCH_CSS_config->n_0) &&
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if(check_frame_sib1(scc, type0_PDCCH_CSS_config, frameP) &&
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(slotP == type0_PDCCH_CSS_config->slot) &&
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(type0_PDCCH_CSS_config->num_rbs > 0) &&
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(type0_PDCCH_CSS_config->active == true)) {
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AssertFatal(is_dl_slot(slotP, &gNB_mac->frame_structure),
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"Trying to schedule SIB1 in slot %d which is not DL. Check searchSpaceZero configuration.\n",
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"Trying to schedule SIB1 for SSB %d in slot %d which is not DL. Check searchSpaceZero configuration.\n",
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type0_PDCCH_CSS_config->ssb_index,
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slotP);
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const int n_slots_frame = gNB_mac->frame_structure.numb_slots_frame;
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int beam_index = get_beam_from_ssbidx(gNB_mac, i);
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