NR_UE: further cleanup of DMRS configuration
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@@ -186,23 +186,6 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue,
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/////////////////////////PUSCH DMRS init/////////////////////////
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///////////
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// default values until overwritten by RRCConnectionReconfiguration
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for (i=0; i<MAX_NR_OF_UL_ALLOCATIONS; i++) {
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ue->pusch_config.pusch_TimeDomainResourceAllocation[i] = (PUSCH_TimeDomainResourceAllocation_t *)malloc16(sizeof(PUSCH_TimeDomainResourceAllocation_t));
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ue->pusch_config.pusch_TimeDomainResourceAllocation[i]->mappingType = typeB;
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}
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for (i=0;i<MAX_NR_OF_DL_ALLOCATIONS;i++){
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ue->PDSCH_Config.pdsch_TimeDomainResourceAllocation[i] = (PDSCH_TimeDomainResourceAllocation_t *)malloc16(sizeof(PDSCH_TimeDomainResourceAllocation_t));
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ue->PDSCH_Config.pdsch_TimeDomainResourceAllocation[i]->mappingType = typeA;
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}
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//------------- config DMRS parameters--------------//
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ue->dmrs_DownlinkConfig.pdsch_dmrs_AdditionalPosition = pdsch_dmrs_pos0;
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//-------------------------------------------------//
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ue->nr_gold_pusch_dmrs = (uint32_t ****)malloc16(fp->slots_per_frame*sizeof(uint32_t ***));
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pusch_dmrs = ue->nr_gold_pusch_dmrs;
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n_scid = 0; // This quantity is indicated by higher layer parameter dmrs-SeqInitialization
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@@ -701,11 +701,11 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
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int8_t delta = get_delta(p, config_type);
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// checking if re-initialization of scrambling IDs is needed
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if ((ue->dmrs_DownlinkConfig.scramblingID0 != ue->scramblingID[0]) || (ue->dmrs_DownlinkConfig.scramblingID1 != ue->scramblingID[1])){
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ue->scramblingID[0]=ue->dmrs_DownlinkConfig.scramblingID0;
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ue->scramblingID[1]=ue->dmrs_DownlinkConfig.scramblingID1;
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/*if ((XXX.scramblingID0 != ue->scramblingID[0]) || (XXX.scramblingID1 != ue->scramblingID[1])){
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ue->scramblingID[0] = XXX.scramblingID0;
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ue->scramblingID[1] = XXX.scramblingID1;
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nr_gold_pdsch(ue,ue->scramblingID);
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}
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}*/
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nr_pdsch_dmrs_rx(ue, Ns, ue->nr_gold_pdsch[gNB_id][Ns][symbol][0], &pilot[0], 1000+p, 0, nb_rb_pdsch+rb_offset, config_type);
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@@ -968,17 +968,14 @@ typedef struct {
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CellGroupConfig_t cell_group_config;
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PDSCH_ServingCellConfig_t PDSCH_ServingCellConfig;
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PDSCH_Config_t PDSCH_Config;
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PUCCH_ConfigCommon_nr_t pucch_config_common_nr[NUMBER_OF_CONNECTED_gNB_MAX];
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PUCCH_Config_t pucch_config_dedicated_nr[NUMBER_OF_CONNECTED_gNB_MAX];
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PUSCH_Config_t pusch_config;
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SRS_NR srs;
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crossCarrierSchedulingConfig_t crossCarrierSchedulingConfig;
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supplementaryUplink_t supplementaryUplink;
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dmrs_DownlinkConfig_t dmrs_DownlinkConfig;
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csi_MeasConfig_t csi_MeasConfig;
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PUSCH_ServingCellConfig_t PUSCH_ServingCellConfig;
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+1
-108
@@ -401,62 +401,6 @@ typedef struct{
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int startSymbolAndLength;
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}PDSCH_TimeDomainResourceAllocation_t;
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typedef struct {
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/*
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* resourceAllocation
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*/
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dl_resourceAllocation_t dl_resourceAllocation;
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/*
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* corresponds to I, where I the number of entries in the higher layer parameter pdsch-AllocationList
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*/
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uint8_t n_pdsh_alloc_list;
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/*
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* rateMatchPatternToAddModList
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*/
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rateMatchPattern_t rateMatchPatternToAddModList[MAX_NR_RATE_MATCH_PATTERNS];
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/*
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* rateMatchPatternToReleaseList
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*/
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uint8_t rateMatchPatternToReleaseList[MAX_NR_RATE_MATCH_PATTERNS];
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/*
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* n_rateMatchPatterns indicates the number of rateMatchPatterns defined currently
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*/
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uint8_t n_rateMatchPatterns;
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/*
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* zp-CSI-RS-ResourceToAddModList
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*/
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zp_CSI_RS_Resource_t zp_CSI_RS_Resource[MAX_NR_ZP_CSI_RS_RESOURCES];
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/*
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* zp-CSI-RS-ResourceToReleaseList
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*/
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uint8_t zp_CSI_RS_ResourceId[MAX_NR_ZP_CSI_RS_RESOURCES];
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/*
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* n_zp-CSI-RS-Resource
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*/
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uint8_t n_zp_CSI_RS_ResourceId;
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/*
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* rgb_Size
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*/
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dl_rgb_Size_t dl_rgbSize;
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/*
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* prb-BundlingType
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*/
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prb_bundleType_t prbBundleType;
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/*
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* pdsch-HARQ-ACK-Codebook: this is part of the IE PhysicalCellGroupConfig which is used to configure cell-group specific L1 parameters (TS 38.331)
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*/
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pdsch_HARQ_ACK_Codebook_t pdsch_HARQ_ACK_Codebook;
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////////////////////////////////////////////////////////////////////////////////################################
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/*
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Maximum number of code words that a single DCI may schedule. This changes the number of MCS/RV/NDI bits in the DCI message from 1 to 2.
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*/
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maxNrofCodeWordsScheduledByDCI_t maxNrofCodeWordsScheduledByDCI;
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PDSCH_TimeDomainResourceAllocation_t *pdsch_TimeDomainResourceAllocation[MAX_NR_OF_DL_ALLOCATIONS];
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} PDSCH_Config_t;
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/***********************************************************************
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*
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@@ -507,6 +451,7 @@ typedef enum {
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typedef enum {
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pdsch_dmrs_pos0 = 0,
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pdsch_dmrs_pos1 = 1,
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pdsch_dmrs_pos2 = 2,
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pdsch_dmrs_pos3 = 3,
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} pdsch_dmrs_AdditionalPosition_t;
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typedef enum {
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@@ -534,11 +479,6 @@ typedef struct {
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uint16_t n_rb0;
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uint16_t n_rb1;
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} ptrs_frequency_density_t;
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typedef struct { // The IE DMRS-DownlinkConfig is used to configure downlink demodulation reference signals for PDSCH
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pdsch_dmrs_AdditionalPosition_t pdsch_dmrs_AdditionalPosition;
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uint16_t scramblingID0;
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uint16_t scramblingID1;
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} dmrs_DownlinkConfig_t;
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typedef struct {
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/*
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* Serving cell ID of a PSCell. The PCell of the Master Cell Group uses ID = 0
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@@ -603,53 +543,6 @@ typedef struct {
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betaOffset_type_t betaOffset_type;
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betaOffset_t betaOffset;
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} uci_onPusch_t;
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typedef struct {
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/*
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* txConfig
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*/
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txConfig_t txConfig;
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/*
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* frequencyHopping
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*/
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frequencyHopping_t frequencyHopping;
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/*
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* frequencyHoppingOffsetLists
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*/
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uint16_t frequencyHoppingOffsetLists[4];
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// n_frequencyHoppingOffsetLists contains the number of offsets listed. We can list up to 4 offsets
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uint8_t n_frequencyHoppingOffsetLists;
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/*
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* resourceAllocation
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*/
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ul_resourceAllocation_t ul_resourceAllocation;
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/*
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* rgb_Size
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*/
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ul_rgb_Size_t ul_rgbSize;
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/*
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* corresponds to I, where I the number of entries in the higher layer parameter pusch-AllocationList
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*/
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uint8_t n_push_alloc_list;
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/*
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* transformPrecoder
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*/
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transformPrecoder_t transformPrecoder;
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/*
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* codebookSubset
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*/
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codebookSubset_t codebookSubset;
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/*
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* maxRank
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*/
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uint8_t maxRank;
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/*
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* uci_onPusch
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*/
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uci_onPusch_t uci_onPusch;
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////////////////////////////////////////////////////////////////////////////////################################
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PUSCH_PowerControl_t pusch_PowerControl;
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PUSCH_TimeDomainResourceAllocation_t *pusch_TimeDomainResourceAllocation[MAX_NR_OF_UL_ALLOCATIONS];
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} PUSCH_Config_t;
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/***********************************************************************
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*
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@@ -1155,7 +1155,7 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
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}
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}
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if (ue->mac_enabled == 1) {
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if (ue->mac_enabled == 1) { // TODO: move this from PHY to MAC layer!
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/* Time Alignment procedure
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// - UE processing capability 1
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@@ -1176,11 +1176,34 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
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const int Ta_max = 3846; // Max value of 12 bits TA Command
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const double N_TA_max = Ta_max * bw_scaling * tc_factor;
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NR_UE_MAC_INST_t *mac = get_mac_inst(0);
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NR_BWP_Id_t ul_bwp_id = mac->UL_BWP_Id;
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NR_PUSCH_Config_t *pusch_Config = mac->ULbwp[ul_bwp_id-1]->bwp_Dedicated->pusch_Config->choice.setup;
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NR_PUSCH_TimeDomainResourceAllocationList_t *pusch_TimeDomainAllocationList = pusch_Config->pusch_TimeDomainAllocationList->choice.setup;
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long mapping_type_ul = pusch_TimeDomainAllocationList->list.array[0]->mappingType;
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NR_BWP_Id_t dl_bwp_id = mac->DL_BWP_Id;
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NR_PDSCH_Config_t *pdsch_Config = mac->DLbwp[dl_bwp_id-1]->bwp_Dedicated->pdsch_Config->choice.setup;
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NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_TimeDomainAllocationList = pdsch_Config->pdsch_TimeDomainAllocationList->choice.setup;
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long mapping_type_dl = pdsch_TimeDomainAllocationList->list.array[0]->mappingType;
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NR_DMRS_DownlinkConfig_t *NR_DMRS_dlconfig;
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if (mapping_type_dl == NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA)
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NR_DMRS_dlconfig = (NR_DMRS_DownlinkConfig_t *)pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup;
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else
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NR_DMRS_dlconfig = (NR_DMRS_DownlinkConfig_t *)pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeB->choice.setup;
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pdsch_dmrs_AdditionalPosition_t add_pos_dl = pdsch_dmrs_pos2;
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if (NR_DMRS_dlconfig->dmrs_AdditionalPosition)
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add_pos_dl = *NR_DMRS_dlconfig->dmrs_AdditionalPosition;
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/* PDSCH decoding time N_1 for processing capability 1 */
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int N_1;
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if (ue->dmrs_DownlinkConfig.pdsch_dmrs_AdditionalPosition == pdsch_dmrs_pos0)
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if (add_pos_dl == pdsch_dmrs_pos0)
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N_1 = pdsch_N_1_capability_1[numerology][1];
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else if (ue->dmrs_DownlinkConfig.pdsch_dmrs_AdditionalPosition == pdsch_dmrs_pos1 || ue->dmrs_DownlinkConfig.pdsch_dmrs_AdditionalPosition == 2) // TODO set to pdsch_dmrs_pos2 when available
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else if (add_pos_dl == pdsch_dmrs_pos1 || add_pos_dl == pdsch_dmrs_pos2)
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N_1 = pdsch_N_1_capability_1[numerology][2];
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else
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N_1 = pdsch_N_1_capability_1[numerology][3];
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@@ -1191,8 +1214,7 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
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/* d_1_1 depending on the number of PDSCH symbols allocated */
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const int d = 0; // TODO number of overlapping symbols of the scheduling PDCCH and the scheduled PDSCH
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int d_1_1 = 0;
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mappingType_t mapping_type_dl = ue->PDSCH_Config.pdsch_TimeDomainResourceAllocation[0]->mappingType;
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if (mapping_type_dl == typeA)
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if (mapping_type_dl == NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA)
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if (nb_symb_sch + start_symbol < 7)
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d_1_1 = 7 - (nb_symb_sch + start_symbol);
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else
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@@ -1207,8 +1229,7 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
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/* d_2_1 */
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int d_2_1;
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mappingType_t mapping_type_ul = ue->pusch_config.pusch_TimeDomainResourceAllocation[0]->mappingType;
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if (mapping_type_ul == typeB && start_symbol != 0)
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if (mapping_type_ul == NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB && start_symbol != 0)
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d_2_1 = 0;
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else
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d_2_1 = 1;
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@@ -158,13 +158,14 @@ int16_t get_pucch_tx_power_ue(PHY_VARS_NR_UE *ue,
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}
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}
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int k2;
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if (power_config->twoPUCCH_PC_AdjustmentStates > 1) {
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LOG_E(PHY,"PUCCH power control adjustment states with 2 states not yet implemented : at line %d in function %s of file %s \n", LINE_FILE , __func__, __FILE__);
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return (PUCCH_POWER_DEFAULT);
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}
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#if 0
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int k2;
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/* response to a detection by the UE of a DCI format 1_0 or DCI format 1_1 */
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//int K_PUCCH = 0;
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if (O_ACK != 0) {
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@@ -201,6 +202,7 @@ int16_t get_pucch_tx_power_ue(PHY_VARS_NR_UE *ue,
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}
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//K_PUCCH = N_SYMB_SLOT * k2; /* the product of a number of symbols per slot and the minimum of the values provided by higher layer parameter k2 */
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}
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#endif
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int contributor = (10 * log10((double)(pow(2,(ue->frame_parms.numerology_index)) * nb_of_prbs)));
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