nr_fill_nfapi_dl_pdu(): MCS + other params configurable
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@@ -446,12 +446,23 @@ void nr_schedule_ue_spec(module_id_t module_id,
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int pucch_sched;
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nr_update_pucch_scheduling(module_id, UE_id, frame, slot, num_slots_per_tdd, &pucch_sched);
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NR_sched_pucch *pucch = &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched];
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const int nrOfLayers = 1;
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const uint8_t mcs = 9;
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const uint8_t numDmrsCdmGrpsNoData = 1;
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const nfapi_nr_dmrs_type_e dmrsConfigType = bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type == NULL ? 0 : 1;
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const int TBS_bytes = nr_fill_nfapi_dl_pdu(module_id,
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UE_id,
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bwp_id,
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dl_req,
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pucch,
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9 /* mcs */,
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nrOfLayers,
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mcs,
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bwpSize,
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0 /* bwpStart */);
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0 /* bwpStart */,
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numDmrsCdmGrpsNoData,
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dmrsConfigType);
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if (TBS_bytes == 0)
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return;
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@@ -408,11 +408,16 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
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}
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int nr_fill_nfapi_dl_pdu(int Mod_idP,
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int UE_id,
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int bwp_id,
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nfapi_nr_dl_tti_request_body_t *dl_req,
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NR_sched_pucch *pucch_sched,
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int nrOfLayers,
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uint8_t mcs,
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uint16_t rbSize,
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uint16_t rbStart) {
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uint16_t rbStart,
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uint8_t numDmrsCdmGrpsNoData,
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nfapi_nr_dmrs_type_e dmrsConfigType) {
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gNB_MAC_INST *nr_mac = RC.nrmac[Mod_idP];
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NR_COMMON_channels_t *cc = nr_mac->common_channels;
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NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
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@@ -420,10 +425,6 @@ int nr_fill_nfapi_dl_pdu(int Mod_idP,
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nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu;
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nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu;
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int bwp_id=1;
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int UE_id = 0;
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const int nrOfLayers = 1;
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NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list;
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NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id];
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@@ -475,10 +476,10 @@ int nr_fill_nfapi_dl_pdu(int Mod_idP,
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pdsch_pdu_rel15->transmissionScheme = 0;
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pdsch_pdu_rel15->refPoint = 0; // Point A
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UE_list->mac_stats[UE_id].dlsch_rounds[UE_list->UE_sched_ctrl[UE_id].harq_processes[current_harq_pid].round]++;
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pdsch_pdu_rel15->dmrsConfigType = bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type == NULL ? 0 : 1;
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pdsch_pdu_rel15->dmrsConfigType = dmrsConfigType;
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pdsch_pdu_rel15->dlDmrsScramblingId = *scc->physCellId;
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pdsch_pdu_rel15->SCID = 0;
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pdsch_pdu_rel15->numDmrsCdmGrpsNoData = 1;
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pdsch_pdu_rel15->numDmrsCdmGrpsNoData = numDmrsCdmGrpsNoData;
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pdsch_pdu_rel15->dmrsPorts = 1;
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pdsch_pdu_rel15->resourceAlloc = 1;
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pdsch_pdu_rel15->rbStart = rbStart;
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@@ -523,7 +524,7 @@ int nr_fill_nfapi_dl_pdu(int Mod_idP,
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// time domain assignment
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dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment; // row index used here instead of SLIV;
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// mcs and rv
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dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0];
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dci_pdu_rel15[0].mcs = mcs;
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dci_pdu_rel15[0].rv = pdsch_pdu_rel15->rvIndex[0];
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// harq pid and ndi
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dci_pdu_rel15[0].harq_pid = current_harq_pid;
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@@ -614,14 +615,14 @@ int nr_fill_nfapi_dl_pdu(int Mod_idP,
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const uint16_t N_PRB_oh = 0; // overhead should be 0 for initialBWP
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uint8_t N_PRB_DMRS;
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if (pdsch_pdu_rel15->dmrsConfigType == NFAPI_NR_DMRS_TYPE1) {
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if (dmrsConfigType == NFAPI_NR_DMRS_TYPE1) {
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// if no data in dmrs cdm group is 1 only even REs have no data
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// if no data in dmrs cdm group is 2 both odd and even REs have no data
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N_PRB_DMRS = pdsch_pdu_rel15->numDmrsCdmGrpsNoData * 6;
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N_PRB_DMRS = numDmrsCdmGrpsNoData * 6;
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} else {
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N_PRB_DMRS = pdsch_pdu_rel15->numDmrsCdmGrpsNoData * 4;
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N_PRB_DMRS = numDmrsCdmGrpsNoData * 4;
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}
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const uint8_t N_sh_symb = pdsch_pdu_rel15->NrOfSymbols;
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const uint8_t N_sh_symb = NrOfSymbols;
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const uint8_t table_idx = 0;
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const uint16_t R = nr_get_code_rate_dl(mcs, table_idx);
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@@ -130,11 +130,16 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
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sub_frame_t subframeP);
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int nr_fill_nfapi_dl_pdu(int Mod_id,
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int UE_id,
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int bwp_id,
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nfapi_nr_dl_tti_request_body_t *dl_req,
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NR_sched_pucch *pucch_sched,
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int nrOfLayers,
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uint8_t mcs,
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uint16_t rbSize,
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uint16_t rbStart);
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uint16_t rbStart,
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uint8_t numDmrsCdmGrpsNoData,
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nfapi_nr_dmrs_type_e dmrsConfigType);
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int configure_fapi_dl_pdu_phytest(int Mod_id,
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nfapi_nr_dl_tti_request_body_t *dl_req,
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