generation of csi-rs sequence
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@@ -179,6 +179,23 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
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LOG_D(PHY,"Initializing PUSCH DMRS Gold sequence with (%x,%x)\n",Nid_pusch[0],Nid_pusch[1]);
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nr_gold_pusch(gNB, &Nid_pusch[0]);
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//CSI RS init
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gNB->nr_gold_csi_rs = (uint32_t ***)malloc16(fp->slots_per_frame*sizeof(uint32_t **));
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uint32_t ***csi_rs = gNB->nr_gold_csi_rs;
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AssertFatal(csi_rs!=NULL, "NR init: csi reference signal malloc failed\n");
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for (int slot=0; slot<fp->slots_per_frame; slot++) {
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csi_rs[slot] = (uint32_t **)malloc16(fp->symbols_per_slot*sizeof(uint32_t *));
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AssertFatal(csi_rs[slot]!=NULL, "NR init: csi reference signal for slot %d - malloc failed\n", slot);
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for (int symb=0; symb<fp->symbols_per_slot; symb++) {
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csi_rs[slot][symb] = (uint32_t *)malloc16(NR_MAX_CSI_RS_INIT_LENGTH_DWORD*sizeof(uint32_t));
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AssertFatal(csi_rs[slot][symb]!=NULL, "NR init: csi reference signal for slot %d symbol %d - malloc failed\n", slot, symb);
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}
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}
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nr_init_csi_rs(gNB, 0); // TODO scramblingID currently hardcoded to 0, to be taken from higher layer parameter scramblingID when implemented
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/// Transport init necessary for NR synchro
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init_nr_transport(gNB);
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@@ -65,7 +65,11 @@ void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid)
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for (uint8_t symb=0; symb<fp->symbols_per_slot; symb++) {
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reset = 1;
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<<<<<<< HEAD
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x2 = ((1<<17) * (14*slot+symb+1) * ((Nid<<1)+1)) + (Nid<<1);
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=======
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x2 = ((1<<17) * (fp->symbols_per_slot*slot+symb+1) * ((Nid<<1)+1) + (Nid<<1));
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>>>>>>> 3752a5f0a... generation of csi-rs sequence
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for (uint32_t n=0; n<NR_MAX_PDCCH_DMRS_INIT_LENGTH_DWORD; n++) {
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pdcch_dmrs[slot][symb][n] = lte_gold_generic(&x1, &x2, reset);
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@@ -130,3 +134,26 @@ void nr_gold_pusch(PHY_VARS_gNB* gNB, uint32_t *Nid) {
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}
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}
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}
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void nr_init_csi_rs(PHY_VARS_gNB* gNB, uint32_t Nid)
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{
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NR_DL_FRAME_PARMS *fp = &gNB->frame_parms;
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uint32_t ***csi_rs = gNB->nr_gold_csi_rs;
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uint32_t x1, x2;
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uint8_t reset;
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for (uint8_t slot=0; slot<fp->slots_per_frame; slot++) {
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for (uint8_t symb=0; symb<fp->symbols_per_slot; symb++) {
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reset = 1;
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x2 = ((1<<10) * (fp->symbols_per_slot*slot+symb+1) * ((Nid<<1)+1) + (Nid));
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for (uint32_t n=0; n<NR_MAX_PDCCH_DMRS_INIT_LENGTH_DWORD; n++) {
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csi_rs[slot][symb][n] = lte_gold_generic(&x1, &x2, reset);
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reset = 0;
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}
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}
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}
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}
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@@ -38,6 +38,7 @@ void nr_init_pbch_dmrs(PHY_VARS_gNB* gNB);
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*/
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void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid);
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void nr_init_pdsch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid);
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void nr_init_csi_rs(PHY_VARS_gNB* gNB, uint32_t Nid);
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void nr_gold_pusch(PHY_VARS_gNB* gNB, uint32_t *Nid);
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@@ -719,6 +719,9 @@ typedef struct PHY_VARS_gNB_s {
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uint32_t rb_mask_ul[9];
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int ulmask_symb;
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/// CSI RS sequence
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uint32_t ***nr_gold_csi_rs;
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/// Indicator set to 0 after first SR
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uint8_t first_sr[NUMBER_OF_NR_SR_MAX];
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@@ -82,6 +82,9 @@
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#define NR_MAX_PDSCH_DMRS_LENGTH 3300 //275*6(k)*2(QPSK real+imag)
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#define NR_MAX_PDSCH_DMRS_INIT_LENGTH_DWORD 104 // ceil(NR_MAX_PDSCH_DMRS_LENGTH/32)
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#define NR_MAX_CSI_RS_LENGTH 5500 //275*10(max allocation per RB)*2(QPSK)
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#define NR_MAX_CSI_RS_INIT_LENGTH_DWORD 172 // ceil(NR_MAX_CSI_RS_LENGTH/32)
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#define NR_MAX_PUSCH_DMRS_LENGTH NR_MAX_PDSCH_DMRS_LENGTH
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#define NR_MAX_PUSCH_DMRS_INIT_LENGTH_DWORD NR_MAX_PDSCH_DMRS_INIT_LENGTH_DWORD
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