fix for pusch num_dmrs_cdm_grps_no_data
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@@ -1387,8 +1387,10 @@ void ulsch_modulation(int32_t **txdataF,
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NR_UE_ULSCH_t *ulsch);
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uint8_t allowed_ulsch_re_in_dmrs_symbol(uint16_t k,
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uint16_t start_sc,
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uint8_t numDmrsCdmGrpsNoData,
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uint8_t dmrs_type);
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int generate_ue_dlsch_params_from_dci(int frame,
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@@ -114,7 +114,6 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
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uint8_t data_existing =0;
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uint8_t L_ptrs, K_ptrs; // PTRS parameters
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uint16_t beta_ptrs; // PTRS parameter related to power control
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uint8_t no_data_in_dmrs = 1;
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NR_UE_ULSCH_t *ulsch_ue;
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NR_UL_UE_HARQ_t *harq_process_ul_ue=NULL;
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@@ -128,7 +127,6 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
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N_PRB_oh = 0; // higher layer (RRC) parameter xOverhead in PUSCH-ServingCellConfig
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number_dmrs_symbols = 0;
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for (cwd_index = 0;cwd_index < num_of_codewords; cwd_index++) {
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ulsch_ue = UE->ulsch[thread_id][gNB_id][cwd_index];
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@@ -149,10 +147,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
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rnti = harq_process_ul_ue->pusch_pdu.rnti;
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ulsch_ue->Nid_cell = Nid_cell;
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if(no_data_in_dmrs)
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nb_dmrs_re_per_rb = 12;
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else
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nb_dmrs_re_per_rb = ((dmrs_type == pusch_dmrs_type1) ? 6:4);
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nb_dmrs_re_per_rb = ((dmrs_type == pusch_dmrs_type1) ? 6:4)*harq_process_ul_ue->pusch_pdu.num_dmrs_cdm_grps_no_data;
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N_RE_prime = NR_NB_SC_PER_RB*number_of_symbols - nb_dmrs_re_per_rb*number_dmrs_symbols - N_PRB_oh;
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@@ -174,7 +169,6 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
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0,
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harq_process_ul_ue->pusch_pdu.nrOfLayers);
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uint8_t access_mode = SCHEDULED_ACCESS;
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//-----------------------------------------------------//
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@@ -439,7 +433,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
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ptrs_idx++;
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} else if (((ul_dmrs_symb_pos >> l) & 0x01) == 0) {
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} else if (allowed_ulsch_re_in_dmrs_symbol(k,start_sc,harq_process_ul_ue->pusch_pdu.num_dmrs_cdm_grps_no_data,dmrs_type)) {
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((int16_t*)txdataF[ap])[(sample_offsetF)<<1] = ((int16_t *) ulsch_ue->y)[m<<1];
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((int16_t*)txdataF[ap])[((sample_offsetF)<<1) + 1] = ((int16_t *) ulsch_ue->y)[(m<<1) + 1];
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@@ -474,6 +468,27 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
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}
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uint8_t allowed_ulsch_re_in_dmrs_symbol(uint16_t k,
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uint16_t start_sc,
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uint8_t numDmrsCdmGrpsNoData,
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uint8_t dmrs_type) {
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uint8_t delta;
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for (int i = 0; i<numDmrsCdmGrpsNoData; i++){
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if (dmrs_type==NFAPI_NR_DMRS_TYPE1) {
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delta = i;
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if (((k-start_sc)%2) == delta)
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return (0);
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}
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else {
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delta = i<<1;
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if ( (((k-start_sc)%6) == delta) || (((k-start_sc)%6) == (delta+1)) )
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return (0);
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}
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}
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return (1);
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}
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uint8_t nr_ue_pusch_common_procedures(PHY_VARS_NR_UE *UE,
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uint8_t harq_pid,
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uint8_t slot,
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@@ -266,6 +266,7 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, int frame_rx, int slot_rx, int ULSCH
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G);
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stop_meas(&gNB->ulsch_decoding_stats);
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if (ret > gNB->ulsch[ULSCH_id][0]->max_ldpc_iterations){
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LOG_I(PHY, "ULSCH %d in error\n",ULSCH_id);
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nr_fill_indication(gNB,frame_rx, slot_rx, ULSCH_id, harq_pid, 1);
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@@ -2768,9 +2768,9 @@ int nr_ue_pdcch_procedures(uint8_t gNB_id,
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nr_tti_rx,
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&dci_ind);
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//#ifdef NR_PDCCH_SCHED_DEBUG
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#ifdef NR_PDCCH_SCHED_DEBUG
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LOG_I(PHY,"<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Ending function nr_dci_decoding_procedure() -> dci_cnt=%u\n",dci_cnt);
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//#endif
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#endif
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VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DCI_DECODING, VCD_FUNCTION_OUT);
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//LOG_D(PHY,"[UE %d][PUSCH] Frame %d nr_tti_rx %d PHICH RX\n",ue->Mod_id,frame_rx,nr_tti_rx);
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@@ -648,7 +648,7 @@ int main(int argc, char **argv)
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pusch_pdu->ul_dmrs_scrambling_id = *scc->physCellId;
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pusch_pdu->scid = 0;
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pusch_pdu->dmrs_ports = 1;
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pusch_pdu->num_dmrs_cdm_grps_no_data = 2;
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pusch_pdu->num_dmrs_cdm_grps_no_data = 1;
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pusch_pdu->resource_alloc = 1;
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pusch_pdu->rb_start = start_rb;
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pusch_pdu->rb_size = nb_rb;
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@@ -703,10 +703,7 @@ int main(int argc, char **argv)
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//there are plenty of other parameters that we don't seem to be using for now. e.g.
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ul_config.ul_config_list[0].pusch_config_pdu.absolute_delta_PUSCH = 0;
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if(no_data_in_dmrs)
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nb_re_dmrs = 12;
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else
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nb_re_dmrs = ((ul_config.ul_config_list[0].pusch_config_pdu.dmrs_config_type == pusch_dmrs_type1) ? 6 : 4);
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nb_re_dmrs = ((ul_config.ul_config_list[0].pusch_config_pdu.dmrs_config_type == pusch_dmrs_type1) ? 6 : 4);
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available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, number_dmrs_symbols, mod_order, 1);
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TBS = nr_compute_tbs(mod_order, code_rate, nb_rb, nb_symb_sch, nb_re_dmrs * number_dmrs_symbols, 0, 0, precod_nbr_layers);
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@@ -818,6 +818,7 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in
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scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.dmrs_config_type = dmrs_config_type;
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scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.mcs_index = mcs_index;
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scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.mcs_table = mcs_table;
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scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.num_dmrs_cdm_grps_no_data = 1;
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scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.new_data_indicator = 0;
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scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.pusch_data.rv_index = rv_index;
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scheduled_response.ul_config->ul_config_list[0].pusch_config_pdu.nrOfLayers = nrOfLayers;
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@@ -872,6 +872,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
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0,
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pusch_pdu->nrOfLayers)>>3;
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pusch_pdu->pusch_data.num_cb = 0; //CBG not supported
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//pusch_pdu->pusch_data.cb_present_and_position;
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//pusch_pdu->pusch_uci;
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@@ -283,7 +283,7 @@ int nr_ue_dcireq(nr_dcireq_t *dcireq) {
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dl_config->slot=UE_mac->dl_config_request.slot;
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dl_config->number_pdus=0;
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printf(" UE_mac->dl_config_request.slot %d VS dcireq->slot %d \n", UE_mac->dl_config_request.slot, dcireq->slot);
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//printf(" UE_mac->dl_config_request.slot %d VS dcireq->slot %d \n", UE_mac->dl_config_request.slot, dcireq->slot);
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LOG_D(PHY, "Entering UE DCI configuration frame %d slot %d \n", dcireq->frame, dcireq->slot);
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