adapting coreset0 parameter
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@@ -362,7 +362,7 @@ uint32_t schedule_control_sib1(module_id_t module_id,
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const uint16_t bwpSize = type0_PDCCH_CSS_config->num_rbs;
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const uint16_t bwpSize = type0_PDCCH_CSS_config->num_rbs;
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int rbStart = type0_PDCCH_CSS_config->cset_start_rb;
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int rbStart = type0_PDCCH_CSS_config->cset_start_rb;
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printf("%d %d\n",bwpSize,rbStart);
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// TODO: There are exceptions to this in table 5.1.2.1.1-4,5 (Default time domain allocation tables B, C)
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// TODO: There are exceptions to this in table 5.1.2.1.1-4,5 (Default time domain allocation tables B, C)
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int mappingtype = (startSymbolIndex <= 3)? typeA: typeB;
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int mappingtype = (startSymbolIndex <= 3)? typeA: typeB;
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@@ -40,7 +40,7 @@ gNBs =
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pdcch_ConfigSIB1 = (
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pdcch_ConfigSIB1 = (
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{
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{
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controlResourceSetZero = 12;
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controlResourceSetZero = 11;
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searchSpaceZero = 0;
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searchSpaceZero = 0;
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}
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}
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);
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);
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