removal of bwp from sib1, removal of fill_default_initialDownlinkBWP
This commit is contained in:
@@ -484,6 +484,7 @@ int nr_initial_sync(UE_nr_rxtx_proc_t *proc,
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// if stand alone and sync on ssb do sib1 detection as part of initial sync
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if (sa==1 && ret==0) {
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bool dec = false;
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NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[proc->thread_id][0];
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int gnb_id = 0; //FIXME
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int coreset_nb_rb=0;
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@@ -534,20 +535,22 @@ int nr_initial_sync(UE_nr_rxtx_proc_t *proc,
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ue->dlsch_SI[gnb_id],
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NULL);
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if (ret >= 0)
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nr_ue_dlsch_procedures(ue,
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proc,
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gnb_id,
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SI_PDSCH,
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ue->dlsch_SI[gnb_id],
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NULL,
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&ue->dlsch_SI_errors[gnb_id],
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dlsch_parallel);
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dec = nr_ue_dlsch_procedures(ue,
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proc,
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gnb_id,
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SI_PDSCH,
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ue->dlsch_SI[gnb_id],
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NULL,
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&ue->dlsch_SI_errors[gnb_id],
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dlsch_parallel);
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// deactivate dlsch once dlsch proc is done
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ue->dlsch_SI[gnb_id]->active = 0;
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}
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}
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}
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if (dec == false) // sib1 not decoded
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ret = -1;
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}
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// exit_fun("debug exit");
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VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_INITIAL_UE_SYNC, VCD_FUNCTION_OUT);
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@@ -416,14 +416,14 @@ void nr_fill_rx_indication(fapi_nr_rx_indication_t *rx_ind,
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NR_UE_DLSCH_t *dlsch0,
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uint16_t n_pdus);
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void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
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UE_nr_rxtx_proc_t *proc,
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int gNB_id,
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PDSCH_t pdsch,
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NR_UE_DLSCH_t *dlsch0,
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NR_UE_DLSCH_t *dlsch1,
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int *dlsch_errors,
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uint8_t dlsch_parallel);
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bool nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
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UE_nr_rxtx_proc_t *proc,
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int gNB_id,
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PDSCH_t pdsch,
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NR_UE_DLSCH_t *dlsch0,
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NR_UE_DLSCH_t *dlsch1,
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int *dlsch_errors,
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uint8_t dlsch_parallel);
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int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue,
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UE_nr_rxtx_proc_t *proc,
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@@ -872,18 +872,18 @@ int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_
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return 0;
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}
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void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
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UE_nr_rxtx_proc_t *proc,
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int gNB_id,
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PDSCH_t pdsch,
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NR_UE_DLSCH_t *dlsch0,
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NR_UE_DLSCH_t *dlsch1,
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int *dlsch_errors,
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uint8_t dlsch_parallel) {
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bool nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
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UE_nr_rxtx_proc_t *proc,
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int gNB_id,
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PDSCH_t pdsch,
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NR_UE_DLSCH_t *dlsch0,
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NR_UE_DLSCH_t *dlsch1,
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int *dlsch_errors,
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uint8_t dlsch_parallel) {
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if (dlsch0==NULL)
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AssertFatal(0,"dlsch0 should be defined at this level \n");
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bool dec = false;
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int harq_pid = dlsch0->current_harq_pid;
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int frame_rx = proc->frame_rx;
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int nr_slot_rx = proc->nr_slot_rx;
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@@ -937,11 +937,11 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
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case PDSCH1:
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LOG_E(PHY,"Illegal PDSCH %d for ue_pdsch_procedures\n",pdsch);
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pdsch_vars = NULL;
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return;
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return false;
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break;
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default:
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pdsch_vars = NULL;
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return;
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return false;
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break;
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}
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@@ -950,17 +950,17 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
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if (pdsch == RA_PDSCH) {
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if (ue->prach_resources[gNB_id]!=NULL)
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dlsch0->rnti = ue->prach_resources[gNB_id]->ra_RNTI;
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dlsch0->rnti = ue->prach_resources[gNB_id]->ra_RNTI;
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else {
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LOG_E(PHY,"[UE %d] Frame %d, nr_slot_rx %d: FATAL, prach_resources is NULL\n", ue->Mod_id, frame_rx, nr_slot_rx);
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//mac_xface->macphy_exit("prach_resources is NULL");
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return;
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LOG_E(PHY,"[UE %d] Frame %d, nr_slot_rx %d: FATAL, prach_resources is NULL\n", ue->Mod_id, frame_rx, nr_slot_rx);
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//mac_xface->macphy_exit("prach_resources is NULL");
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return false;
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}
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}
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// exit dlsch procedures as there are no active dlsch
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if (is_cw0_active != ACTIVE && is_cw1_active != ACTIVE)
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return;
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return false;
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// start ldpc decode for CW 0
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dlsch0->harq_processes[harq_pid]->G = nr_get_G(dlsch0->harq_processes[harq_pid]->nb_rb,
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@@ -1141,6 +1141,7 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
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LOG_D(PHY, "harq_pid: %d, TBS expected dlsch0: %d \n",harq_pid, dlsch0->harq_processes[harq_pid]->TBS);
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if(ret<dlsch0->max_ldpc_iterations+1){
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dec = true;
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switch (pdsch) {
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case RA_PDSCH:
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nr_fill_dl_indication(&dl_indication, NULL, &rx_ind, proc, ue, gNB_id);
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@@ -1248,10 +1249,12 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
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}
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// reset TA flag
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ul_time_alignment->apply_ta = 0;
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LOG_D(PHY,"Frame %d slot %d -- Starting UL time alignment procedures. TA update will be applied at frame %d slot %d\n", frame_rx, nr_slot_rx, ul_time_alignment->ta_frame, ul_time_alignment->ta_slot);
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LOG_D(PHY,"Frame %d slot %d -- Starting UL time alignment procedures. TA update will be applied at frame %d slot %d\n",
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frame_rx, nr_slot_rx, ul_time_alignment->ta_frame, ul_time_alignment->ta_slot);
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}
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}
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}
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return dec;
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}
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@@ -38,6 +38,8 @@
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#include <string.h>
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#include <stdbool.h>
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#include "NR_SubcarrierSpacing.h"
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#define TABLE_38213_13_1_NUM_INDEXES 15
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#define TABLE_38213_13_2_NUM_INDEXES 14
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#define TABLE_38213_13_3_NUM_INDEXES 9
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@@ -456,6 +458,7 @@ typedef struct Type0_PDCCH_CSS_config_s {
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uint32_t ssb_length;
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uint32_t ssb_index;
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uint32_t cset_start_rb;
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NR_SubcarrierSpacing_t scs_pdcch;
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bool active;
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} NR_Type0_PDCCH_CSS_config_t;
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@@ -3286,7 +3286,7 @@ void get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PD
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else
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scs_pdcch = NR_SubcarrierSpacing_kHz30;
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}
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type0_PDCCH_CSS_config->scs_pdcch = scs_pdcch;
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type0_PDCCH_CSS_config->ssb_index = ssb_index;
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type0_PDCCH_CSS_config->frame = frameP;
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@@ -852,8 +852,8 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
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{
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int mcsIndex;
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int startSymbolAndLength = 0, StartSymbolIndex = -1, NrOfSymbols = 14, StartSymbolIndex_tmp, NrOfSymbols_tmp, x_Overhead, time_domain_assignment = 0;
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gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
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NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id];
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gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
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NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id];
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NR_SearchSpace_t *ss = ra->ra_ss;
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// This code from this point on will not work on initialBWP or CORESET0
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@@ -936,7 +936,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
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dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2 + sizeof(nfapi_nr_dl_tti_pdcch_pdu));
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dl_req->nPDUs += 1;
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pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
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nr_configure_pdcch(pdcch_pdu_rel15, ss, coreset, scc, bwp);
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nr_configure_pdcch(nr_mac,pdcch_pdu_rel15, ss, coreset, scc, bwp);
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nr_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid] = pdcch_pdu_rel15;
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}
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@@ -319,7 +319,6 @@ void schedule_control_sib1(module_id_t module_id,
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int num_total_bytes) {
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gNB_MAC_INST *gNB_mac = RC.nrmac[module_id];
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NR_ServingCellConfigCommon_t *servingcellconfigcommon = gNB_mac->common_channels[CC_id].ServingCellConfigCommon;
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uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
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int ret;
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@@ -327,14 +326,12 @@ void schedule_control_sib1(module_id_t module_id,
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gNB_mac->sched_ctrlCommon = calloc(1,sizeof(*gNB_mac->sched_ctrlCommon));
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gNB_mac->sched_ctrlCommon->search_space = calloc(1,sizeof(*gNB_mac->sched_ctrlCommon->search_space));
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gNB_mac->sched_ctrlCommon->coreset = calloc(1,sizeof(*gNB_mac->sched_ctrlCommon->coreset));
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gNB_mac->sched_ctrlCommon->active_bwp = calloc(1,sizeof(*gNB_mac->sched_ctrlCommon->active_bwp));
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for (int i=0; i<3; i++){ // loop over possible aggregation levels
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ret = fill_searchSpaceZero(gNB_mac->sched_ctrlCommon->search_space,type0_PDCCH_CSS_config,4<<i);
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if (ret == 1) break;
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}
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AssertFatal(ret==1,"No aggregation level for type0_PDCCH_CSS found\n");
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fill_coresetZero(gNB_mac->sched_ctrlCommon->coreset,type0_PDCCH_CSS_config);
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fill_default_initialDownlinkBWP(gNB_mac->sched_ctrlCommon->active_bwp,servingcellconfigcommon);
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}
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gNB_mac->sched_ctrlCommon->time_domain_allocation = time_domain_allocation;
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gNB_mac->sched_ctrlCommon->mcsTableIdx = mcsTableIdx;
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@@ -345,7 +342,7 @@ void schedule_control_sib1(module_id_t module_id,
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find_aggregation_candidates(&gNB_mac->sched_ctrlCommon->aggregation_level, &nr_of_candidates, gNB_mac->sched_ctrlCommon->search_space);
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gNB_mac->sched_ctrlCommon->cce_index = allocate_nr_CCEs(RC.nrmac[module_id],
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gNB_mac->sched_ctrlCommon->active_bwp,
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NULL,
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gNB_mac->sched_ctrlCommon->coreset,
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gNB_mac->sched_ctrlCommon->aggregation_level,
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0,
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@@ -414,7 +411,6 @@ void nr_fill_nfapi_dl_sib1_pdu(int Mod_idP,
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NR_COMMON_channels_t *cc = gNB_mac->common_channels;
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NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
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NR_CellGroupConfig_t *secondaryCellGroup = gNB_mac->secondaryCellGroupCommon;
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NR_BWP_Downlink_t *bwp = gNB_mac->sched_ctrlCommon->active_bwp;
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nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdcch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
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memset((void*)dl_tti_pdcch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t));
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@@ -422,15 +418,12 @@ void nr_fill_nfapi_dl_sib1_pdu(int Mod_idP,
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dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu));
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dl_req->nPDUs += 1;
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15 = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
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nr_configure_pdcch(pdcch_pdu_rel15,
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nr_configure_pdcch(gNB_mac,
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pdcch_pdu_rel15,
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gNB_mac->sched_ctrlCommon->search_space,
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gNB_mac->sched_ctrlCommon->coreset,
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scc,
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bwp);
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// TODO: This assignment should be done in function nr_configure_pdcch()
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pdcch_pdu_rel15->BWPSize = gNB_mac->type0_PDCCH_CSS_config->num_rbs;
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pdcch_pdu_rel15->BWPStart = gNB_mac->type0_PDCCH_CSS_config->cset_start_rb;
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NULL);
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nfapi_nr_dl_tti_request_pdu_t *dl_tti_pdsch_pdu = &dl_req->dl_tti_pdu_list[dl_req->nPDUs];
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memset((void*)dl_tti_pdsch_pdu,0,sizeof(nfapi_nr_dl_tti_request_pdu_t));
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@@ -448,12 +441,8 @@ void nr_fill_nfapi_dl_sib1_pdu(int Mod_idP,
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pdsch_pdu_rel15->BWPSize = type0_PDCCH_CSS_config->num_rbs;
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pdsch_pdu_rel15->BWPStart = type0_PDCCH_CSS_config->cset_start_rb;
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pdsch_pdu_rel15->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing;
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if (bwp->bwp_Common->genericParameters.cyclicPrefix) {
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pdsch_pdu_rel15->CyclicPrefix = *bwp->bwp_Common->genericParameters.cyclicPrefix;
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} else {
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pdsch_pdu_rel15->CyclicPrefix = 0;
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}
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pdsch_pdu_rel15->SubcarrierSpacing = type0_PDCCH_CSS_config->scs_pdcch;
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pdsch_pdu_rel15->CyclicPrefix = 0;
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pdsch_pdu_rel15->NrOfCodewords = 1;
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pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(gNB_mac->sched_ctrlCommon->mcs,0);
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@@ -465,7 +454,7 @@ void nr_fill_nfapi_dl_sib1_pdu(int Mod_idP,
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pdsch_pdu_rel15->nrOfLayers = 1;
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pdsch_pdu_rel15->transmissionScheme = 0;
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pdsch_pdu_rel15->refPoint = 1;
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pdsch_pdu_rel15->dmrsConfigType = gNB_mac->sched_ctrlCommon->active_bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type == NULL ? 0 : 1;
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pdsch_pdu_rel15->dmrsConfigType = 0;
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pdsch_pdu_rel15->dlDmrsScramblingId = *scc->physCellId;
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pdsch_pdu_rel15->SCID = 0;
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pdsch_pdu_rel15->numDmrsCdmGrpsNoData = gNB_mac->sched_ctrlCommon->numDmrsCdmGrpsNoData;
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@@ -499,7 +488,7 @@ void nr_fill_nfapi_dl_sib1_pdu(int Mod_idP,
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dci_pdu_rel15_t dci_payload;
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memset(&dci_payload, 0, sizeof(dci_pdu_rel15_t));
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dci_payload.bwp_indicator.val = gNB_mac->sched_ctrlCommon->active_bwp->bwp_Id;
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dci_payload.bwp_indicator.val = 0;
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// frequency domain assignment
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dci_payload.frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(
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@@ -527,7 +516,7 @@ void nr_fill_nfapi_dl_sib1_pdu(int Mod_idP,
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dci_format,
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rnti_type,
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pdsch_pdu_rel15->BWPSize,
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gNB_mac->sched_ctrlCommon->active_bwp->bwp_Id);
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0);
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LOG_D(MAC,"BWPSize: %i\n", pdcch_pdu_rel15->BWPSize);
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LOG_D(MAC,"BWPStart: %i\n", pdcch_pdu_rel15->BWPStart);
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@@ -780,7 +780,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
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dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu));
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dl_req->nPDUs += 1;
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pdcch_pdu = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
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nr_configure_pdcch(pdcch_pdu, sched_ctrl->search_space, sched_ctrl->coreset, scc, bwp);
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nr_configure_pdcch(gNB_mac,pdcch_pdu, sched_ctrl->search_space, sched_ctrl->coreset, scc, bwp);
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gNB_mac->pdcch_pdu_idx[CC_id][bwpid][coresetid] = pdcch_pdu;
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}
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@@ -175,7 +175,7 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
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int coreset_id = coreset->controlResourceSetId;
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int *cce_list;
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if(bwp->bwp_Id == 0) {
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if(bwp == NULL || bwp->bwp_Id == 0) {
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cce_list = nr_mac->cce_list[1][0];
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} else {
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cce_list = nr_mac->cce_list[bwp->bwp_Id][coreset_id];
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@@ -554,70 +554,75 @@ void config_uldci(const NR_BWP_Uplink_t *ubwp,
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dci_pdu_rel15->rv);
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}
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void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu,
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void nr_configure_pdcch(gNB_MAC_INST *gNB_mac,
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nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu,
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NR_SearchSpace_t *ss,
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NR_ControlResourceSet_t *coreset,
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NR_ServingCellConfigCommon_t *scc,
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NR_BWP_Downlink_t *bwp)
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{
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if (bwp) { // This is not the InitialBWP
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||||
int sps;
|
||||
if (bwp) { // This is not for SIB1
|
||||
pdcch_pdu->BWPSize = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
|
||||
pdcch_pdu->BWPStart = NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
|
||||
pdcch_pdu->SubcarrierSpacing = bwp->bwp_Common->genericParameters.subcarrierSpacing;
|
||||
pdcch_pdu->CyclicPrefix = (bwp->bwp_Common->genericParameters.cyclicPrefix==NULL) ? 0 : *bwp->bwp_Common->genericParameters.cyclicPrefix;
|
||||
|
||||
// first symbol
|
||||
//AssertFatal(pdcch_scs==kHz15, "PDCCH SCS above 15kHz not allowed if a symbol above 2 is monitored");
|
||||
int sps = bwp->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12;
|
||||
|
||||
AssertFatal(ss->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n");
|
||||
AssertFatal(ss->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n");
|
||||
|
||||
// for SPS=14 8 MSBs in positions 13 downto 6
|
||||
uint16_t monitoringSymbolsWithinSlot = (ss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) |
|
||||
(ss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps));
|
||||
|
||||
for (int i=0; i<sps; i++) {
|
||||
if ((monitoringSymbolsWithinSlot>>(sps-1-i))&1) {
|
||||
pdcch_pdu->StartSymbolIndex=i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
pdcch_pdu->DurationSymbols = coreset->duration;
|
||||
|
||||
for (int i=0;i<6;i++)
|
||||
pdcch_pdu->FreqDomainResource[i] = coreset->frequencyDomainResources.buf[i];
|
||||
|
||||
|
||||
//cce-REG-MappingType
|
||||
pdcch_pdu->CceRegMappingType = coreset->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved?
|
||||
NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED : NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED;
|
||||
|
||||
if (pdcch_pdu->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) {
|
||||
pdcch_pdu->RegBundleSize = (coreset->cce_REG_MappingType.choice.interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+coreset->cce_REG_MappingType.choice.interleaved->reg_BundleSize);
|
||||
pdcch_pdu->InterleaverSize = (coreset->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+coreset->cce_REG_MappingType.choice.interleaved->interleaverSize);
|
||||
AssertFatal(scc->physCellId != NULL,"scc->physCellId is null\n");
|
||||
pdcch_pdu->ShiftIndex = coreset->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *coreset->cce_REG_MappingType.choice.interleaved->shiftIndex : *scc->physCellId;
|
||||
}
|
||||
else {
|
||||
pdcch_pdu->RegBundleSize = 0;
|
||||
pdcch_pdu->InterleaverSize = 0;
|
||||
pdcch_pdu->ShiftIndex = 0;
|
||||
}
|
||||
|
||||
if(coreset->controlResourceSetId == 0) {
|
||||
pdcch_pdu->CoreSetType = NFAPI_NR_CSET_CONFIG_MIB_SIB1;
|
||||
} else{
|
||||
pdcch_pdu->CoreSetType = NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG;
|
||||
}
|
||||
|
||||
//precoderGranularity
|
||||
pdcch_pdu->precoderGranularity = coreset->precoderGranularity;
|
||||
sps = bwp->bwp_Common->genericParameters.cyclicPrefix == NULL ? 14 : 12;
|
||||
}
|
||||
else { // this is for InitialBWP
|
||||
AssertFatal(1==0,"Fill in InitialBWP PDCCH configuration\n");
|
||||
else {
|
||||
pdcch_pdu->BWPSize = gNB_mac->type0_PDCCH_CSS_config->num_rbs;
|
||||
pdcch_pdu->BWPStart = gNB_mac->type0_PDCCH_CSS_config->cset_start_rb;
|
||||
pdcch_pdu->SubcarrierSpacing = gNB_mac->type0_PDCCH_CSS_config->scs_pdcch;
|
||||
pdcch_pdu->CyclicPrefix = 0;
|
||||
sps = 14;
|
||||
}
|
||||
|
||||
AssertFatal(ss->monitoringSymbolsWithinSlot!=NULL,"ss->monitoringSymbolsWithinSlot is null\n");
|
||||
AssertFatal(ss->monitoringSymbolsWithinSlot->buf!=NULL,"ss->monitoringSymbolsWithinSlot->buf is null\n");
|
||||
|
||||
// for SPS=14 8 MSBs in positions 13 downto 6
|
||||
uint16_t monitoringSymbolsWithinSlot = (ss->monitoringSymbolsWithinSlot->buf[0]<<(sps-8)) |
|
||||
(ss->monitoringSymbolsWithinSlot->buf[1]>>(16-sps));
|
||||
|
||||
for (int i=0; i<sps; i++) {
|
||||
if ((monitoringSymbolsWithinSlot>>(sps-1-i))&1) {
|
||||
pdcch_pdu->StartSymbolIndex=i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
pdcch_pdu->DurationSymbols = coreset->duration;
|
||||
|
||||
for (int i=0;i<6;i++)
|
||||
pdcch_pdu->FreqDomainResource[i] = coreset->frequencyDomainResources.buf[i];
|
||||
|
||||
|
||||
//cce-REG-MappingType
|
||||
pdcch_pdu->CceRegMappingType = coreset->cce_REG_MappingType.present == NR_ControlResourceSet__cce_REG_MappingType_PR_interleaved?
|
||||
NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED : NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED;
|
||||
|
||||
if (pdcch_pdu->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) {
|
||||
pdcch_pdu->RegBundleSize = (coreset->cce_REG_MappingType.choice.interleaved->reg_BundleSize == NR_ControlResourceSet__cce_REG_MappingType__interleaved__reg_BundleSize_n6) ? 6 : (2+coreset->cce_REG_MappingType.choice.interleaved->reg_BundleSize);
|
||||
pdcch_pdu->InterleaverSize = (coreset->cce_REG_MappingType.choice.interleaved->interleaverSize==NR_ControlResourceSet__cce_REG_MappingType__interleaved__interleaverSize_n6) ? 6 : (2+coreset->cce_REG_MappingType.choice.interleaved->interleaverSize);
|
||||
AssertFatal(scc->physCellId != NULL,"scc->physCellId is null\n");
|
||||
pdcch_pdu->ShiftIndex = coreset->cce_REG_MappingType.choice.interleaved->shiftIndex != NULL ? *coreset->cce_REG_MappingType.choice.interleaved->shiftIndex : *scc->physCellId;
|
||||
}
|
||||
else {
|
||||
pdcch_pdu->RegBundleSize = 0;
|
||||
pdcch_pdu->InterleaverSize = 0;
|
||||
pdcch_pdu->ShiftIndex = 0;
|
||||
}
|
||||
|
||||
if(coreset->controlResourceSetId == 0) {
|
||||
pdcch_pdu->CoreSetType = NFAPI_NR_CSET_CONFIG_MIB_SIB1;
|
||||
} else{
|
||||
pdcch_pdu->CoreSetType = NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG;
|
||||
}
|
||||
|
||||
//precoderGranularity
|
||||
pdcch_pdu->precoderGranularity = coreset->precoderGranularity;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -1090,7 +1090,7 @@ void nr_schedule_ulsch(module_id_t module_id,
|
||||
ul_dci_request_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu));
|
||||
pdcch_pdu = &ul_dci_request_pdu->pdcch_pdu.pdcch_pdu_rel15;
|
||||
ul_dci_req->numPdus += 1;
|
||||
nr_configure_pdcch(pdcch_pdu, sched_ctrl->search_space, sched_ctrl->coreset, scc, sched_ctrl->active_bwp);
|
||||
nr_configure_pdcch(RC.nrmac[module_id], pdcch_pdu, sched_ctrl->search_space, sched_ctrl->coreset, scc, sched_ctrl->active_bwp);
|
||||
pdcch_pdu_bwp_coreset[bwpid][coresetid] = pdcch_pdu;
|
||||
}
|
||||
|
||||
|
||||
@@ -241,7 +241,8 @@ void find_search_space(int ss_type,
|
||||
NR_BWP_Downlink_t *bwp,
|
||||
NR_SearchSpace_t *ss);
|
||||
|
||||
void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu,
|
||||
void nr_configure_pdcch(gNB_MAC_INST *gNB_mac,
|
||||
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu,
|
||||
NR_SearchSpace_t *ss,
|
||||
NR_ControlResourceSet_t *coreset,
|
||||
NR_ServingCellConfigCommon_t *scc,
|
||||
|
||||
@@ -72,8 +72,6 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_
|
||||
|
||||
void rrc_remove_nsa_user(gNB_RRC_INST *rrc, int rnti);
|
||||
|
||||
void fill_default_initialDownlinkBWP(NR_BWP_Downlink_t *bwp, NR_ServingCellConfigCommon_t *servingcellconfigcommon);
|
||||
|
||||
void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellconfigcommon,
|
||||
NR_ServingCellConfig_t *servingcellconfigdedicated,
|
||||
NR_CellGroupConfig_t *secondaryCellGroup,
|
||||
|
||||
@@ -49,31 +49,6 @@
|
||||
#define false 0
|
||||
#define true 1
|
||||
|
||||
void fill_default_initialDownlinkBWP(NR_BWP_Downlink_t *bwp, NR_ServingCellConfigCommon_t *servingcellconfigcommon) {
|
||||
|
||||
bwp->bwp_Id = 0;
|
||||
|
||||
bwp->bwp_Common=calloc(1,sizeof(*bwp->bwp_Common));
|
||||
memcpy((void*)&bwp->bwp_Common,
|
||||
&servingcellconfigcommon->downlinkConfigCommon->initialDownlinkBWP,
|
||||
sizeof(bwp->bwp_Common));
|
||||
|
||||
bwp->bwp_Dedicated=calloc(1,sizeof(*bwp->bwp_Dedicated));
|
||||
bwp->bwp_Dedicated->pdsch_Config = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config));
|
||||
bwp->bwp_Dedicated->pdsch_Config->present = NR_SetupRelease_PDSCH_Config_PR_setup;
|
||||
bwp->bwp_Dedicated->pdsch_Config->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup));
|
||||
bwp->bwp_Dedicated->pdsch_Config->choice.setup->dataScramblingIdentityPDSCH = NULL;
|
||||
bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA));
|
||||
bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->present= NR_SetupRelease_DMRS_DownlinkConfig_PR_setup;
|
||||
bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup));
|
||||
bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type=NULL;
|
||||
bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->maxLength=NULL;
|
||||
bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID0=NULL;
|
||||
bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->scramblingID1=NULL;
|
||||
bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->phaseTrackingRS=NULL;
|
||||
bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = calloc(1,sizeof(*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition));
|
||||
*bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_AdditionalPosition = NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0;
|
||||
}
|
||||
|
||||
void fill_default_secondaryCellGroup(NR_ServingCellConfigCommon_t *servingcellconfigcommon,
|
||||
NR_ServingCellConfig_t *servingcellconfigdedicated,
|
||||
|
||||
Reference in New Issue
Block a user