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@@ -864,316 +864,11 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id,
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t[UE_template->pre_first_nb_rb_ul + i] = UE_id + '0';
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}
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}
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// step 3: assigne RBS
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for (UE_id = UE_list->head_ul; UE_id >= 0; UE_id = UE_list->next_ul[UE_id]) {
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// if (continueTable[UE_id]) continue;
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for (n = 0; n < UE_list->numactiveULCCs[UE_id]; n++) {
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// This is the actual CC_id in the list
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CC_id = UE_list->ordered_ULCCids[n][UE_id];
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UE_template = &UE_list->UE_template[CC_id][UE_id];
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harq_pid = subframe2harqpid(&RC.mac[module_idP]->common_channels[CC_id],
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sched_frameP, sched_subframeP);
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// mac_xface->get_ue_active_harq_pid(module_idP,CC_id,rnti,frameP,subframeP,&harq_pid,&round,openair_harq_UL);
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if (UE_list->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid] > 0) {
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nb_allocated_rbs[CC_id][UE_id] = UE_list->UE_template[CC_id][UE_id].nb_rb_ul[harq_pid];
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} else {
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nb_allocated_rbs[CC_id][UE_id] =
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cmin(UE_list->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul[slice_idx], average_rbs_per_user[CC_id]);
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}
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total_allocated_rbs[CC_id] += nb_allocated_rbs[CC_id][UE_id];
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LOG_D(MAC, "In ulsch_preprocessor: assigning %d RBs for UE %d/%x CCid %d, harq_pid %d, nb_rb_ul %d, %d ,%d, slice %d, round ul %d\n",
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nb_allocated_rbs[CC_id][UE_id],
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UE_id,
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rntiTable[UE_id],
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CC_id,
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harq_pid,
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UE_list->UE_template[CC_id][UE_id].nb_rb_ul[harq_pid],
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UE_list->UE_template[CC_id][UE_id].pre_allocated_nb_rb_ul[slice_idx],
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average_rbs_per_user[CC_id],
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slice_idx,
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UE_list->UE_sched_ctrl[UE_id].round_UL[CC_id][harq_pid]);
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}
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}
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// step 4: assigne the remaining RBs and set the pre_allocated rbs accordingly
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for (UE_id = UE_list->head_ul; UE_id >= 0; UE_id = UE_list->next_ul[UE_id]) {
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// if (continueTable[UE_id]) continue;
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ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
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for (n = 0; n < UE_list->numactiveULCCs[UE_id]; n++) {
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// This is the actual CC_id in the list
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CC_id = UE_list->ordered_ULCCids[n][UE_id];
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UE_template = &UE_list->UE_template[CC_id][UE_id];
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N_RB_UL = to_prb(eNB->common_channels[CC_id].ul_Bandwidth);
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first_rb_offset = UE_list->first_rb_offset[CC_id][slice_idx];
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available_rbs = cmin(ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_idx], N_RB_UL - first_rb[CC_id] - first_rb_offset);
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total_remaining_rbs[CC_id] = available_rbs - total_allocated_rbs[CC_id];
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if (total_ue_count[CC_id] == 1) {
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total_remaining_rbs[CC_id]++;
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}
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while (UE_template->pre_allocated_nb_rb_ul[slice_idx] > 0 &&
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nb_allocated_rbs[CC_id][UE_id] < UE_template->pre_allocated_nb_rb_ul[slice_idx] &&
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total_remaining_rbs[CC_id] > 0) {
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nb_allocated_rbs[CC_id][UE_id] = cmin(nb_allocated_rbs[CC_id][UE_id] + 1, UE_template->pre_allocated_nb_rb_ul[slice_idx]);
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total_remaining_rbs[CC_id]--;
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total_allocated_rbs[CC_id]++;
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}
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UE_template->pre_allocated_nb_rb_ul[slice_idx] = nb_allocated_rbs[CC_id][UE_id];
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LOG_D(MAC, "******************UL Scheduling Information for UE%d CC_id %d ************************\n",
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UE_id,
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CC_id);
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LOG_D(MAC, "[eNB %d] total RB allocated for UE%d CC_id %d = %d\n",
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module_idP,
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UE_id,
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CC_id,
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UE_template->pre_allocated_nb_rb_ul[slice_idx]);
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}
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}
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return;
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}
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void
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assign_max_mcs_min_rb(module_id_t module_idP,
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int slice_idx,
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int frameP,
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sub_frame_t subframeP,
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uint16_t *first_rb) {
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int i;
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uint16_t n, UE_id;
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uint8_t CC_id;
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int mcs;
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int rb_table_index = 0, tbs, tx_power;
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eNB_MAC_INST *eNB = RC.mac[module_idP];
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UE_list_t *UE_list = &eNB->UE_list;
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slice_info_t *sli = &eNB->slice_info;
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UE_TEMPLATE *UE_template;
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UE_sched_ctrl_t *ue_sched_ctl;
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int Ncp;
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int N_RB_UL;
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int first_rb_offset, available_rbs;
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for (i = UE_list->head_ul; i >= 0; i = UE_list->next_ul[i]) {
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if (UE_list->UE_sched_ctrl[i].phr_received == 1) {
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/* if we've received the power headroom information the UE, we can go to
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* maximum mcs */
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mcs = cmin(20, sli->ul[slice_idx].maxmcs);
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} else {
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/* otherwise, limit to QPSK PUSCH */
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mcs = cmin(10, sli->ul[slice_idx].maxmcs);
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}
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UE_id = i;
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for (n = 0; n < UE_list->numactiveULCCs[UE_id]; n++) {
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// This is the actual CC_id in the list
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CC_id = UE_list->ordered_ULCCids[n][UE_id];
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AssertFatal(CC_id < RC.nb_mac_CC[module_idP], "CC_id %u should be < %u, loop n=%u < numactiveULCCs[%u]=%u",
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CC_id,
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NFAPI_CC_MAX,
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n,
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UE_id,
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UE_list->numactiveULCCs[UE_id]);
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UE_template = &UE_list->UE_template[CC_id][UE_id];
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UE_template->pre_assigned_mcs_ul = mcs;
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ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
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Ncp = eNB->common_channels[CC_id].Ncp;
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N_RB_UL = to_prb(eNB->common_channels[CC_id].ul_Bandwidth);
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ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_idx] = nb_rbs_allowed_slice(sli->ul[slice_idx].pct, N_RB_UL);
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int bytes_to_schedule = UE_template->estimated_ul_buffer - UE_template->scheduled_ul_bytes;
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if (bytes_to_schedule < 0) bytes_to_schedule = 0;
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int bits_to_schedule = bytes_to_schedule * 8;
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// if this UE has UL traffic
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if (bits_to_schedule > 0) {
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tbs = get_TBS_UL(UE_template->pre_assigned_mcs_ul, 3) << 3; // 1 or 2 PRB with cqi enabled does not work well!
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rb_table_index = 2;
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// fixme: set use_srs flag
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tx_power = estimate_ue_tx_power(tbs, rb_table[rb_table_index], 0, Ncp, 0);
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while ((UE_template->phr_info - tx_power < 0 || tbs > bits_to_schedule) && UE_template->pre_assigned_mcs_ul > 3) {
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// LOG_I(MAC,"UE_template->phr_info %d tx_power %d mcs %d\n", UE_template->phr_info,tx_power, mcs);
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UE_template->pre_assigned_mcs_ul--;
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tbs = get_TBS_UL(UE_template->pre_assigned_mcs_ul, rb_table[rb_table_index]) << 3;
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tx_power = estimate_ue_tx_power(tbs, rb_table[rb_table_index], 0, Ncp, 0); // fixme: set use_srs
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}
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first_rb_offset = UE_list->first_rb_offset[CC_id][slice_idx];
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available_rbs =
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cmin(ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_idx], N_RB_UL - first_rb[CC_id] - first_rb_offset);
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while (tbs < bits_to_schedule &&
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rb_table[rb_table_index] < available_rbs &&
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UE_template->phr_info - tx_power > 0 &&
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rb_table_index < 32) {
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rb_table_index++;
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tbs = get_TBS_UL(UE_template->pre_assigned_mcs_ul, rb_table[rb_table_index]) << 3;
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tx_power = estimate_ue_tx_power(tbs, rb_table[rb_table_index], 0, Ncp, 0);
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}
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if (rb_table[rb_table_index] > (available_rbs - 1)) {
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rb_table_index--;
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}
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// 1 or 2 PRB with cqi enabled does not work well
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if (rb_table[rb_table_index] < 3) {
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rb_table_index = 2; //3PRB
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}
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UE_template->pre_allocated_rb_table_index_ul = rb_table_index;
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UE_template->pre_allocated_nb_rb_ul[slice_idx] = rb_table[rb_table_index];
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LOG_D(MAC, "[eNB %d] frame %d subframe %d: for UE %d CC %d: pre-assigned mcs %d, pre-allocated rb_table[%d]=%d RBs (phr %d, tx power %d)\n",
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module_idP,
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frameP,
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subframeP,
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UE_id,
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CC_id,
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UE_template->pre_assigned_mcs_ul,
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UE_template->pre_allocated_rb_table_index_ul,
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UE_template->pre_allocated_nb_rb_ul[slice_idx],
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UE_template->phr_info, tx_power);
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} else {
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/* if UE has pending scheduling request then pre-allocate 3 RBs */
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//if (UE_template->ul_active == 1 && UE_template->ul_SR == 1) {
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if (UE_is_to_be_scheduled(module_idP, CC_id, i)) {
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/* use QPSK mcs */
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UE_template->pre_assigned_mcs_ul = 10;
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UE_template->pre_allocated_rb_table_index_ul = 2;
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UE_template->pre_allocated_nb_rb_ul[slice_idx] = 3;
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} else {
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UE_template->pre_assigned_mcs_ul = 0;
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UE_template->pre_allocated_rb_table_index_ul = -1;
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UE_template->pre_allocated_nb_rb_ul[slice_idx] = 0;
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}
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}
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}
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}
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}
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struct sort_ue_ul_params {
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int module_idP;
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int sched_frameP;
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int sched_subframeP;
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};
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static int ue_ul_compare(const void *_a, const void *_b, void *_params) {
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struct sort_ue_ul_params *params = _params;
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UE_list_t *UE_list = &RC.mac[params->module_idP]->UE_list;
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int UE_id1 = *(const int *) _a;
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int UE_id2 = *(const int *) _b;
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int rnti1 = UE_RNTI(params->module_idP, UE_id1);
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int pCCid1 = UE_PCCID(params->module_idP, UE_id1);
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int round1 = maxround_ul(params->module_idP, rnti1, params->sched_frameP,
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params->sched_subframeP);
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int rnti2 = UE_RNTI(params->module_idP, UE_id2);
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int pCCid2 = UE_PCCID(params->module_idP, UE_id2);
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int round2 = maxround_ul(params->module_idP, rnti2, params->sched_frameP,
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params->sched_subframeP);
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if (round1 > round2)
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return -1;
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if (round1 < round2)
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return 1;
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if (UE_list->UE_template[pCCid1][UE_id1].ul_buffer_info[LCGID0] >
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UE_list->UE_template[pCCid2][UE_id2].ul_buffer_info[LCGID0])
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return -1;
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if (UE_list->UE_template[pCCid1][UE_id1].ul_buffer_info[LCGID0] <
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UE_list->UE_template[pCCid2][UE_id2].ul_buffer_info[LCGID0])
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return 1;
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int bytes_to_schedule1 = UE_list->UE_template[pCCid1][UE_id1].estimated_ul_buffer - UE_list->UE_template[pCCid1][UE_id1].scheduled_ul_bytes;
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if (bytes_to_schedule1 < 0) bytes_to_schedule1 = 0;
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int bytes_to_schedule2 = UE_list->UE_template[pCCid2][UE_id2].estimated_ul_buffer - UE_list->UE_template[pCCid2][UE_id2].scheduled_ul_bytes;
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if (bytes_to_schedule2 < 0) bytes_to_schedule2 = 0;
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if (bytes_to_schedule1 > bytes_to_schedule2)
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return -1;
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if (bytes_to_schedule1 < bytes_to_schedule2)
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return 1;
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if (UE_list->UE_template[pCCid1][UE_id1].pre_assigned_mcs_ul >
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UE_list->UE_template[pCCid2][UE_id2].pre_assigned_mcs_ul)
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return -1;
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if (UE_list->UE_template[pCCid1][UE_id1].pre_assigned_mcs_ul <
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UE_list->UE_template[pCCid2][UE_id2].pre_assigned_mcs_ul)
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return 1;
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if (UE_list->UE_sched_ctrl[UE_id1].cqi_req_timer >
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UE_list->UE_sched_ctrl[UE_id2].cqi_req_timer)
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return -1;
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if (UE_list->UE_sched_ctrl[UE_id1].cqi_req_timer <
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UE_list->UE_sched_ctrl[UE_id2].cqi_req_timer)
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return 1;
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return 0;
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}
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//-----------------------------------------------------------------------------
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/*
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* This function sorts the UEs in order, depending on their ulsch buffer and CQI
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*/
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void sort_ue_ul(module_id_t module_idP,
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|
int slice_idx,
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|
int sched_frameP,
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|
sub_frame_t sched_subframeP,
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|
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|
rnti_t *rntiTable)
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|
|
//-----------------------------------------------------------------------------
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|
{
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|
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|
int list[MAX_MOBILES_PER_ENB];
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|
int list_size = 0;
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|
struct sort_ue_ul_params params = { module_idP, sched_frameP, sched_subframeP };
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|
UE_list_t *UE_list = &RC.mac[module_idP]->UE_list;
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|
|
UE_sched_ctrl_t *UE_scheduling_control = NULL;
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for (int i = 0; i < MAX_MOBILES_PER_ENB; i++) {
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UE_scheduling_control = &(UE_list->UE_sched_ctrl[i]);
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|
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|
|
|
/* Check CDRX configuration and if UE is in active time for this subframe */
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|
|
|
if (UE_scheduling_control->cdrx_configured == TRUE) {
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|
|
|
if (UE_scheduling_control->in_active_time == FALSE) {
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|
continue;
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|
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|
}
|
|
|
|
|
}
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|
|
rntiTable[i] = UE_RNTI(module_idP, i);
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|
// Valid element and is not the actual CC_id in the list
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|
|
|
if (UE_list->active[i] == TRUE &&
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|
|
|
rntiTable[i] != NOT_A_RNTI &&
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|
|
|
UE_list->UE_sched_ctrl[i].ul_out_of_sync != 1 &&
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|
|
|
ue_ul_slice_membership(module_idP, i, slice_idx)) {
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|
|
list[list_size++] = i; // Add to list
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|
|
|
}
|
|
|
|
|
}
|
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|
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|
|
qsort_r(list, list_size, sizeof(int), ue_ul_compare, ¶ms);
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|
|
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|
|
|
|
if (list_size) { // At mimimum one list element
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|
|
|
for (int i = 0; i < list_size - 1; i++) {
|
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|
|
|
UE_list->next_ul[list[i]] = list[i + 1];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
UE_list->next_ul[list[list_size - 1]] = -1;
|
|
|
|
|
UE_list->head_ul = list[0];
|
|
|
|
|
} else { // No element
|
|
|
|
|
UE_list->head_ul = -1;
|
|
|
|
|
}
|
|
|
|
|
if (print)
|
|
|
|
|
LOG_D(MAC,
|
|
|
|
|
"%4d.%d UL scheduler allocation list: %s\n",
|
|
|
|
|
sched_frameP,
|
|
|
|
|
sched_subframeP,
|
|
|
|
|
t);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|