Rewrite assign_max_mcs_min_rb() more concisely
This commit is contained in:
Robert Schmidt
@@ -474,100 +474,105 @@ void ulsch_scheduler_pre_processor(module_id_t module_idP,
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}
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}
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void calculate_max_mcs_min_rb(module_id_t mod_id,
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int CC_id,
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int bytes,
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int phr,
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int max_mcs,
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int *mcs,
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int max_rbs,
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int *rb_index,
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int *tx_power) {
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const int Ncp = RC.mac[mod_id]->common_channels[CC_id].Ncp;
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/* TODO shouldn't we consider the SRS or other quality indicators? */
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*mcs = max_mcs;
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*rb_index = 2;
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int tbs = get_TBS_UL(*mcs, rb_table[*rb_index]);
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// fixme: set use_srs flag
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*tx_power = estimate_ue_tx_power(tbs * 8, rb_table[*rb_index], 0, Ncp, 0);
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/* find maximum MCS */
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while ((phr - *tx_power < 0 || tbs > bytes) && *mcs > 3) {
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mcs--;
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tbs = get_TBS_UL(*mcs, rb_table[*rb_index]);
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*tx_power = estimate_ue_tx_power(tbs * 8, rb_table[*rb_index], 0, Ncp, 0);
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}
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/* find minimum necessary RBs */
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while (tbs < bytes
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&& *rb_index < 32
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&& rb_table[*rb_index] < max_rbs
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&& phr - *tx_power > 0) {
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(*rb_index)++;
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tbs = get_TBS_UL(*mcs, rb_table[*rb_index]);
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*tx_power = estimate_ue_tx_power(tbs * 8, rb_table[*rb_index], 0, Ncp, 0);
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}
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/* Decrease if we went to far in last iteration */
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if (rb_table[*rb_index] > max_rbs)
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(*rb_index)--;
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// 1 or 2 PRB with cqi enabled does not work well
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if (rb_table[*rb_index] < 3) {
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*rb_index = 2; //3PRB
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}
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}
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void
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assign_max_mcs_min_rb(module_id_t module_idP,
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int CC_id,
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int frameP,
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sub_frame_t subframeP,
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uint16_t *first_rb) {
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int mcs;
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int rb_table_index = 0, tbs, tx_power;
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eNB_MAC_INST *eNB = RC.mac[module_idP];
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UE_info_t *UE_info = &eNB->UE_info;
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slice_info_t *sli = &eNB->slice_info;
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UE_TEMPLATE *UE_template;
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UE_sched_ctrl_t *ue_sched_ctl;
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int Ncp;
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int N_RB_UL;
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int first_rb_offset, available_rbs;
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const int N_RB_UL = to_prb(RC.mac[module_idP]->common_channels[CC_id].ul_Bandwidth);
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const int available_rbs = N_RB_UL - 2 * first_rb[CC_id]; // top and bottom - UE_info->first_rb_offset[CC_id];
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const int Ncp = RC.mac[module_idP]->common_channels[CC_id].Ncp;
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UE_info_t *UE_info = &RC.mac[module_idP]->UE_info;
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for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) {
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/* if we've received the power headroom information the UE, we can go to
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* maximum mcs */
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mcs = UE_info->UE_sched_ctrl[UE_id].phr_received == 1 ? 20 : 10;
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UE_TEMPLATE *UE_template = &UE_info->UE_template[CC_id][UE_id];
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UE_template = &UE_info->UE_template[CC_id][UE_id];
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UE_template->pre_assigned_mcs_ul = mcs;
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ue_sched_ctl = &UE_info->UE_sched_ctrl[UE_id];
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Ncp = eNB->common_channels[CC_id].Ncp;
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N_RB_UL = to_prb(eNB->common_channels[CC_id].ul_Bandwidth);
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int bytes_to_schedule = UE_template->estimated_ul_buffer - UE_template->scheduled_ul_bytes;
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const int B = cmax(UE_template->estimated_ul_buffer - UE_template->scheduled_ul_bytes, 0);
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if (bytes_to_schedule < 0) bytes_to_schedule = 0;
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const int UE_to_be_scheduled = UE_is_to_be_scheduled(module_idP, CC_id, UE_id);
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if (B == 0 && !UE_to_be_scheduled)
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continue;
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int bits_to_schedule = bytes_to_schedule * 8;
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// if this UE has UL traffic
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if (bits_to_schedule > 0) {
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tbs = get_TBS_UL(UE_template->pre_assigned_mcs_ul, 3) << 3; // 1 or 2 PRB with cqi enabled does not work well!
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rb_table_index = 2;
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// fixme: set use_srs flag
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tx_power = estimate_ue_tx_power(tbs, rb_table[rb_table_index], 0, Ncp, 0);
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while ((UE_template->phr_info - tx_power < 0 || tbs > bits_to_schedule) && UE_template->pre_assigned_mcs_ul > 3) {
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// LOG_I(MAC,"UE_template->phr_info %d tx_power %d mcs %d\n", UE_template->phr_info,tx_power, mcs);
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UE_template->pre_assigned_mcs_ul--;
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tbs = get_TBS_UL(UE_template->pre_assigned_mcs_ul, rb_table[rb_table_index]) << 3;
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tx_power = estimate_ue_tx_power(tbs, rb_table[rb_table_index], 0, Ncp, 0); // fixme: set use_srs
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}
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first_rb_offset = UE_info->first_rb_offset[CC_id];
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available_rbs = N_RB_UL - 2 * first_rb[CC_id];
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while (tbs < bits_to_schedule &&
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rb_table[rb_table_index] < available_rbs &&
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UE_template->phr_info - tx_power > 0 &&
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rb_table_index < 32) {
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rb_table_index++;
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tbs = get_TBS_UL(UE_template->pre_assigned_mcs_ul, rb_table[rb_table_index]) << 3;
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tx_power = estimate_ue_tx_power(tbs, rb_table[rb_table_index], 0, Ncp, 0);
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}
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if (rb_table[rb_table_index] > (available_rbs - 1)) {
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rb_table_index--;
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}
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// 1 or 2 PRB with cqi enabled does not work well
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if (rb_table[rb_table_index] < 3) {
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rb_table_index = 2; //3PRB
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}
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UE_template->pre_allocated_rb_table_index_ul = rb_table_index;
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UE_template->pre_allocated_nb_rb_ul = rb_table[rb_table_index];
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if (UE_template->pre_allocated_nb_rb_ul > 0)
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LOG_W(MAC, "[eNB %d] frame %d subframe %d: for UE %d CC %d: pre-assigned mcs %d, pre-allocated rb_table[%d]=%d RBs (phr %d, tx power %d)\n",
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module_idP,
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frameP,
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subframeP,
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UE_id,
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CC_id,
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UE_template->pre_assigned_mcs_ul,
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UE_template->pre_allocated_rb_table_index_ul,
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UE_template->pre_allocated_nb_rb_ul,
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UE_template->phr_info, tx_power);
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} else {
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/* if UE has pending scheduling request then pre-allocate 3 RBs */
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//if (UE_template->ul_active == 1 && UE_template->ul_SR == 1) {
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if (UE_is_to_be_scheduled(module_idP, CC_id, UE_id)) {
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/* use QPSK mcs */
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UE_template->pre_assigned_mcs_ul = 10;
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UE_template->pre_allocated_rb_table_index_ul = 2;
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UE_template->pre_allocated_nb_rb_ul = 3;
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} else {
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UE_template->pre_assigned_mcs_ul = 0;
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UE_template->pre_allocated_rb_table_index_ul = -1;
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UE_template->pre_allocated_nb_rb_ul = 0;
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}
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/* if UE has pending scheduling request then pre-allocate 3 RBs */
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if (B == 0 && UE_to_be_scheduled) {
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UE_template->pre_assigned_mcs_ul = 10; /* use QPSK mcs only */
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UE_template->pre_allocated_rb_table_index_ul = 2;
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UE_template->pre_allocated_nb_rb_ul = 3;
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continue;
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}
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int mcs;
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int rb_table_index;
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int tx_power;
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calculate_max_mcs_min_rb(
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module_idP,
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CC_id,
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B,
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UE_template->phr_info,
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UE_info->UE_sched_ctrl[UE_id].phr_received == 1 ? 20 : 10,
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&mcs,
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available_rbs,
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&rb_table_index,
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&tx_power);
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UE_template->pre_assigned_mcs_ul = mcs;
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UE_template->pre_allocated_rb_table_index_ul = rb_table_index;
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UE_template->pre_allocated_nb_rb_ul = rb_table[rb_table_index];
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LOG_D(MAC, "[eNB %d] frame %d subframe %d: for UE %d CC %d: pre-assigned mcs %d, pre-allocated rb_table[%d]=%d RBs (phr %d, tx power %d)\n",
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module_idP,
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frameP,
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subframeP,
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UE_id,
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CC_id,
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UE_template->pre_assigned_mcs_ul,
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UE_template->pre_allocated_rb_table_index_ul,
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UE_template->pre_allocated_nb_rb_ul,
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UE_template->phr_info, tx_power);
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}
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}
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