@@ -55,8 +55,8 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
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unsigned int frame_length_samples = frame_parms->samples_per_subframe * 10;
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unsigned int rx_offset;
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NR_UE_PDCCH *pdcch_vars = ue->pdcch_vars[ue->current_thread_id[Ns>>1]][0];
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uint16_t coreset_start_subcarrier = frame_parms->first_carrier_offset + pdcch_vars->coreset[0].rb_offset*NR_NB_SC_PER_RB;//+((int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_vars->coreset[0].rb_offset)*NR_NB_SC_PER_RB;
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uint16_t nb_rb_coreset = pdcch_vars->coreset[0].rb_offset;
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uint16_t coreset_start_subcarrier = frame_parms->first_carrier_offset;//+((int)floor(frame_parms->ssb_start_subcarrier/NR_NB_SC_PER_RB)+pdcch_vars->coreset[0].rb_offset)*NR_NB_SC_PER_RB;
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uint16_t nb_rb_coreset = 24;
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uint16_t bwp_start_subcarrier = frame_parms->first_carrier_offset;//+516;
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uint16_t nb_rb_pdsch = 50;
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uint8_t p=0;
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@@ -32,7 +32,7 @@
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#include "nr_dci.h"
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#define DEBUG_PDCCH_DMRS
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//#define DEBUG_PDCCH_DMRS
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#define DEBUG_DCI
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#define DEBUG_CHANNEL_CODING
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@@ -207,12 +207,12 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
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/// DMRS QPSK modulation
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/*There is a need to shift from which index the pregenerated DMRS sequence is used
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* see 38211 r15.2.0 section 7.4.1.3.2: assumption is the reference point for k refers to the DMRS sequence*/
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/*if (pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG) {
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if (pdcch_params.config_type == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG) {
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for (int symb=cset_start_symb; symb<cset_start_symb + pdcch_params.n_symb; symb++)
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gold_pdcch_dmrs[symb] += (pdcch_params.rb_offset*3)>>5;
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dmrs_offset = (pdcch_params.rb_offset*3)&0x1f;
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LOG_I(PHY, "PDCCH DMRS offset %d\n", dmrs_offset);
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}*/ // DMRS shift currently disable for compatibility with the OAI UE
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}
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for (int symb=cset_start_symb; symb<cset_start_symb + pdcch_params.n_symb; symb++) {
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if (dmrs_offset) {
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@@ -21,7 +21,7 @@
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/*! \file PHY/LTE_TRANSPORT/dlsch_coding.c
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* \brief Top-level routines for implementing LDPC-coded (DLSCH) transport channels from 38-212, 15.2
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* \author H.Wang, Guy De Souza
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* \author H.Wang
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* \date 2018
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* \version 0.1
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* \company Eurecom
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@@ -29,7 +29,7 @@
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#include "filt16a_32.h"
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#include "T.h"
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//#define DEBUG_PDSCH
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#define DEBUG_PDCCH
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//#define DEBUG_PDCCH
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int nr_pbch_channel_estimation(PHY_VARS_NR_UE *ue,
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@@ -262,7 +262,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
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unsigned short coreset_start_subcarrier,
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unsigned short nb_rb_coreset)
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{
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int pilot[300] __attribute__((aligned(16)));
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int pilot[200] __attribute__((aligned(16)));
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unsigned char aarx,p;
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unsigned short k;
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unsigned int pilot_cnt;
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@@ -604,7 +604,7 @@ int main(int argc, char **argv)
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uint64_t mask = 0x0;
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uint16_t num_rbs=24;
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uint16_t rb_offset=24;
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||||
uint16_t rb_offset=0;
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||||
uint16_t cell_id=0;
|
||||
uint16_t num_symbols=2;
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||||
for(i=0; i<(num_rbs/6); ++i){ // 38.331 Each bit corresponds a group of 6 RBs
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||||
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||||
@@ -47,7 +47,7 @@ extern RAN_CONTEXT_t RC;
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void nr_init_coreset(nfapi_nr_coreset_t *coreset) {
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coreset->coreset_id = 1;
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coreset->frequency_domain_resources = 0x1E000000000;//0x1FFFE0000000; // 96 RB starting from CRB0
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coreset->frequency_domain_resources = 0x1E0000000000;//0x1FFFE0000000; // 96 RB starting from CRB0
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coreset->duration = 2;
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||||
coreset->cce_reg_mapping_type = NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED;
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||||
coreset->reg_bundle_size = 6;
|
||||
|
||||
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Block a user