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Merge remote-tracking branch 'origin/develop' into NR_PUCCH_RRC_Resources

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This commit is contained in:
francescomani
2022-06-01 09:06:57 +02:00
parent a724c1febc 5ea828e149
commit 9a43678ed0
76 changed files with 2220 additions and 3726 deletions
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cmake_targets/autotests/test_case_list.xml
+21 -16
View File
@@ -1104,7 +1104,8 @@
(Test19: Mapping type A, 3 DMRS Symbols),
(Test20: Mapping type B, 4 DMRS Symbols),
(Test21: 4x4 MIMO, 1 Layer),
(Test22: 4x4 MIMO, 2 Layers)</desc>
(Test22: 4x4 MIMO, 2 Layers),
(Test23: 25 PRBs, 15 kHz SCS)</desc>
<pre_compile_prog></pre_compile_prog>
<compile_prog>$OPENAIR_DIR/cmake_targets/build_oai</compile_prog>
<compile_prog_args> --phy_simulators -c </compile_prog_args>
@@ -1132,8 +1133,9 @@
-n100 -s2 -U 2 0 2
-n100 -s2 -U 2 1 3
-n10 -s20 -U 3 0 0 2 -gR -x1 -y4 -z4
-n10 -s20 -U 3 0 0 2 -gR -x2 -y4 -z4</main_exec_args>
<tags>nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 nr_dlsim.test11 nr_dlsim.test12 nr_dlsim.test13 nr_dlsim.test14 nr_dlsim.test15 nr_dlsim.test16 nr_dlsim.test17 nr_dlsim.test18 nr_dlsim.test19 nr_dlsim.test20 nr_dlsim.test21 nr_dlsim.test22</tags>
-n10 -s20 -U 3 0 0 2 -gR -x2 -y4 -z4
-n100 -m0 -e0 -R25 -b25 -i</main_exec_args>
<tags>nr_dlsim.test1 nr_dlsim.test2 nr_dlsim.test3 nr_dlsim.test4 nr_dlsim.test5 nr_dlsim.test6 nr_dlsim.test7 nr_dlsim.test8 nr_dlsim.test9 nr_dlsim.test10 nr_dlsim.test11 nr_dlsim.test12 nr_dlsim.test13 nr_dlsim.test14 nr_dlsim.test15 nr_dlsim.test16 nr_dlsim.test17 nr_dlsim.test18 nr_dlsim.test19 nr_dlsim.test20 nr_dlsim.test21 nr_dlsim.test22 nr_dlsim.test23</tags>
<search_expr_true>PDSCH test OK</search_expr_true>
<search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false>
<nruns>3</nruns>
@@ -1306,9 +1308,10 @@
(Test12: SC-FDMA, 216 PRBs),
(Test13: SC-FDMA, 273 PRBs),
(Test14: SC-FDMA, 3 DMRS),
(Test15: MCS 19 50 PRBs 2 RX_Antenna)
(Test16: MCS 9 106 PRBs MIMO 2 layers)
(Test17: MCS 9 106 PRBs MIMO 4 layers)</desc>
(Test15: MCS 19 50 PRBs 2 RX_Antenna),
(Test16: MCS 9 106 PRBs MIMO 2 layers),
(Test17: MCS 9 106 PRBs MIMO 4 layers),
(Test18: 25 PRBs, 15 kHz SCS)</desc>
<pre_compile_prog></pre_compile_prog>
<compile_prog>$OPENAIR_DIR/cmake_targets/build_oai</compile_prog>
<compile_prog_args> --phy_simulators -c </compile_prog_args>
@@ -1331,9 +1334,9 @@
-n100 -s5 -Z -U 2 0 2
-n100 -m19 -s10 -S15 -z2
-n100 -m9 -r106 -s10 -W2 -y2 -z2
-n100 -m9 -r106 -s20 -W4 -y4 -z4</main_exec_args>
<tags>nr_ulsim.test1 nr_ulsim.test2 nr_ulsim.test3 nr_ulsim.test4 nr_ulsim.test5 nr_ulsim.test6 nr_ulsim.test7 nr_ulsim.test8 nr_ulsim.test9 nr_ulsim.test10 nr_ulsim.test11 nr_ulsim.test12 nr_ulsim.test13 nr_ulsim.test14 nr_ulsim.test15 nr_ulsim.test16 nr_ulsim.test17</tags>
-n100 -m9 -r106 -s20 -W4 -y4 -z4
-n100 -u0 -m0 -R25 -r25 -i</main_exec_args>
<tags>nr_ulsim.test1 nr_ulsim.test2 nr_ulsim.test3 nr_ulsim.test4 nr_ulsim.test5 nr_ulsim.test6 nr_ulsim.test7 nr_ulsim.test8 nr_ulsim.test9 nr_ulsim.test10 nr_ulsim.test11 nr_ulsim.test12 nr_ulsim.test13 nr_ulsim.test14 nr_ulsim.test15 nr_ulsim.test16 nr_ulsim.test17 nr_ulsim.test18</tags>
<search_expr_true>PUSCH test OK</search_expr_true>
<search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false>
<nruns>3</nruns>
@@ -1344,10 +1347,11 @@
<desc>nr_prachsim Test cases. (Test1: 30kHz SCS, 106 PRBs, Prach format A2),
(Test2: 30kHz SCS, 217 PRBs, Prach format A2),
(Test3: 30kHz SCS, 273 PRBs, Prach format A2),
(Test4: 30kHz SCS, 106 PRBs, Prach format 0),
(Test4: 30kHz SCS, 106 PRBs, Prach format 0),
(Test5: 120kHz SCS, 32 PRBs, Prach format A2),
(Test6: 120kHz SCS, 66 PRBs, Prach format A2),
(Test7: 120kHz SCS, 66 PRBs, High Speed Enabled)</desc>
(Test7: 120kHz SCS, 66 PRBs, High Speed Enabled),
(Test8: 15kHz SCS, 25 PRBs)</desc>
<pre_compile_prog></pre_compile_prog>
<compile_prog>$OPENAIR_DIR/cmake_targets/build_oai</compile_prog>
<compile_prog_args> --phy_simulators -c </compile_prog_args>
@@ -1357,11 +1361,12 @@
<main_exec_args>-a -s -30 -n 100 -p 63 -R 106
-a -s -30 -n 100 -p 63 -R 217
-a -s -30 -n 100 -p 63 -R 273
-a -s -30 -n 100 -p 63 -R 106 -c 4
-a -s -30 -n 100 -p 32 -R 32 -m 3 -c52
-a -s -30 -n 100 -p 32 -R 66 -m 3 -c52
-a -s -30 -n 100 -R 66 -m 3 -c52 -H</main_exec_args>
<tags>nr_prachsim.test1 nr_prachsim.test2 nr_prachsim.test3 nr_prachsim.test4 nr_prachsim.test5 nr_prachsim.test6 nr_prachsim.test7</tags>
-a -s -30 -n 100 -p 63 -R 106 -c 4
-a -s -30 -n 100 -p 32 -R 32 -m 3 -c52
-a -s -30 -n 100 -p 32 -R 66 -m 3 -c52
-a -s -30 -n 100 -R 66 -m 3 -c52 -H
-a -s -30 -n 100 -p 99 -R 25 -m 0</main_exec_args>
<tags>nr_prachsim.test1 nr_prachsim.test2 nr_prachsim.test3 nr_prachsim.test4 nr_prachsim.test5 nr_prachsim.test6 nr_prachsim.test7 nr_prachsim.test8</tags>
<search_expr_true>PRACH test OK</search_expr_true>
<search_expr_false>segmentation fault|assertion|exiting|fatal</search_expr_false>
<nruns>3</nruns>
common/utils/nr/nr_common.c
-61
View File
@@ -191,67 +191,6 @@ int PRBalloc_to_locationandbandwidth(int NPRB,int RBstart) {
return(PRBalloc_to_locationandbandwidth0(NPRB,RBstart,275));
}
/// Target code rate tables indexed by Imcs
/* TS 38.214 table 5.1.3.1-1 - MCS index table 1 for PDSCH */
uint16_t nr_target_code_rate_table1[29] = {120, 157, 193, 251, 308, 379, 449, 526, 602, 679, 340, 378, 434, 490, 553, \
616, 658, 438, 466, 517, 567, 616, 666, 719, 772, 822, 873, 910, 948};
/* TS 38.214 table 5.1.3.1-2 - MCS index table 2 for PDSCH */
// Imcs values 20 and 26 have been multiplied by 2 to avoid the floating point
uint16_t nr_target_code_rate_table2[28] = {120, 193, 308, 449, 602, 378, 434, 490, 553, 616, 658, 466, 517, 567, \
616, 666, 719, 772, 822, 873, 1365, 711, 754, 797, 841, 885, 1833, 948};
/* TS 38.214 table 5.1.3.1-3 - MCS index table 3 for PDSCH */
uint16_t nr_target_code_rate_table3[29] = {30, 40, 50, 64, 78, 99, 120, 157, 193, 251, 308, 379, 449, 526, 602, 340, \
378, 434, 490, 553, 616, 438, 466, 517, 567, 616, 666, 719, 772};
uint16_t nr_tbs_table[93] = {24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, 192, 208, 224, 240, 256, 272, 288, 304, 320, \
336, 352, 368, 384, 408, 432, 456, 480, 504, 528, 552, 576, 608, 640, 672, 704, 736, 768, 808, 848, 888, 928, 984, 1032, 1064, 1128, 1160, 1192, 1224, 1256, \
1288, 1320, 1352, 1416, 1480, 1544, 1608, 1672, 1736, 1800, 1864, 1928, 2024, 2088, 2152, 2216, 2280, 2408, 2472, 2536, 2600, 2664, 2728, 2792, 2856, 2976, \
3104, 3240, 3368, 3496, 3624, 3752, 3824};
uint8_t nr_get_Qm(uint8_t Imcs, uint8_t table_idx) {
switch(table_idx) {
case 1:
return (((Imcs<10)||(Imcs==29))?2:((Imcs<17)||(Imcs==30))?4:((Imcs<29)||(Imcs==31))?6:-1);
break;
case 2:
return (((Imcs<5)||(Imcs==28))?2:((Imcs<11)||(Imcs==29))?4:((Imcs<20)||(Imcs==30))?6:((Imcs<28)||(Imcs==31))?8:-1);
break;
case 3:
return (((Imcs<15)||(Imcs==29))?2:((Imcs<21)||(Imcs==30))?4:((Imcs<29)||(Imcs==31))?6:-1);
break;
default:
AssertFatal(0, "Invalid MCS table index %d (expected in range [1,3])\n", table_idx);
return(0);
break;
}
}
uint32_t nr_get_code_rate(uint8_t Imcs, uint8_t table_idx) {
switch(table_idx) {
case 1:
return (nr_target_code_rate_table1[Imcs]);
break;
case 2:
return (nr_target_code_rate_table2[Imcs]);
break;
case 3:
return (nr_target_code_rate_table3[Imcs]);
break;
default:
AssertFatal(0, "Invalid MCS table index %d (expected in range [1,3])\n", table_idx);
return(0);
break;
}
}
void get_coreset_rballoc(uint8_t *FreqDomainResource,int *n_rb,int *rb_offset) {
uint8_t count=0, start=0, start_set=0;
common/utils/nr/nr_common.h
-6
View File
@@ -69,12 +69,6 @@ int NRRIV2BW(int locationAndBandwidth,int N_RB);
int NRRIV2PRBOFFSET(int locationAndBandwidth,int N_RB);
int PRBalloc_to_locationandbandwidth0(int NPRB,int RBstart,int BWPsize);
int PRBalloc_to_locationandbandwidth(int NPRB,int RBstart);
extern uint16_t nr_target_code_rate_table1[29];
extern uint16_t nr_target_code_rate_table2[28];
extern uint16_t nr_target_code_rate_table3[29];
extern uint16_t nr_tbs_table[93];
uint8_t nr_get_Qm(uint8_t Imcs, uint8_t table_idx);
uint32_t nr_get_code_rate(uint8_t Imcs, uint8_t table_idx);
int get_subband_size(int NPRB,int size);
void SLIV2SL(int SLIV,int *S,int *L);
int get_dmrs_port(int nl, uint16_t dmrs_ports);
common/utils/threadPool/thread-pool.h
+1 -1
View File
@@ -80,7 +80,7 @@ static inline notifiedFIFO_elt_t *newNotifiedFIFO_elt(int size,
notifiedFIFO_t *reponseFifo,
void (*processingFunc)(void *)) {
notifiedFIFO_elt_t *ret;
AssertFatal( NULL != (ret=(notifiedFIFO_elt_t *) malloc(sizeof(notifiedFIFO_elt_t)+size+32)), "");
AssertFatal( NULL != (ret=(notifiedFIFO_elt_t *) calloc(1, sizeof(notifiedFIFO_elt_t)+size+32)), "");
ret->next=NULL;
ret->key=key;
ret->reponseFifo=reponseFifo;
executables/nr-ru.c
+17 -7
View File
@@ -719,10 +719,17 @@ void tx_rf(RU_t *ru,int frame,int slot, uint64_t timestamp) {
AssertFatal(txsymb>0,"illegal txsymb %d\n",txsymb);
if(slot%(fp->slots_per_subframe/2))
siglen = txsymb * (fp->ofdm_symbol_size + fp->nb_prefix_samples);
else
siglen = (fp->ofdm_symbol_size + fp->nb_prefix_samples0) + (txsymb - 1) * (fp->ofdm_symbol_size + fp->nb_prefix_samples);
if (fp->slots_per_subframe == 1) {
if (txsymb <= 7)
siglen = (fp->ofdm_symbol_size + fp->nb_prefix_samples0) + (txsymb - 1) * (fp->ofdm_symbol_size + fp->nb_prefix_samples);
else
siglen = 2 * (fp->ofdm_symbol_size + fp->nb_prefix_samples0) + (txsymb - 2) * (fp->ofdm_symbol_size + fp->nb_prefix_samples);
} else {
if(slot%(fp->slots_per_subframe/2))
siglen = txsymb * (fp->ofdm_symbol_size + fp->nb_prefix_samples);
else
siglen = (fp->ofdm_symbol_size + fp->nb_prefix_samples0) + (txsymb - 1) * (fp->ofdm_symbol_size + fp->nb_prefix_samples);
}
//+ ru->end_of_burst_delay;
flags = 3; // end of burst
@@ -1049,11 +1056,12 @@ void fill_rf_config(RU_t *ru, char *rf_config_file) {
cfg->tx_gain[i] = ru->att_tx;
cfg->rx_gain[i] = ru->max_rxgain-ru->att_rx;
cfg->configFilename = rf_config_file;
LOG_I(PHY, "Channel %d: setting tx_gain offset %f, rx_gain offset %f, tx_freq %lu Hz, rx_freq %lu Hz\n",
LOG_I(PHY, "Channel %d: setting tx_gain offset %.0f, rx_gain offset %.0f, tx_freq %.0f Hz, rx_freq %.0f Hz, tune_offset %.0f Hz\n",
i, cfg->tx_gain[i],
cfg->rx_gain[i],
(unsigned long)cfg->tx_freq[i],
(unsigned long)cfg->rx_freq[i]);
cfg->tx_freq[i],
cfg->rx_freq[i],
cfg->tune_offset);
}
}
@@ -2051,6 +2059,8 @@ static void NRRCconfig_RU(void) {
RC.ru[j]->openair0_cfg.time_source = internal;
}
RC.ru[j]->openair0_cfg.tune_offset = get_softmodem_params()->tune_offset;
if (strcmp(*(RUParamList.paramarray[j][RU_LOCAL_RF_IDX].strptr), "yes") == 0) {
if ( !(config_isparamset(RUParamList.paramarray[j],RU_LOCAL_IF_NAME_IDX)) ) {
RC.ru[j]->if_south = LOCAL_RF;
executables/nr-uesoftmodem.c
+1
View File
@@ -354,6 +354,7 @@ void init_openair0(void) {
openair0_cfg[card].num_rb_dl = frame_parms->N_RB_DL;
openair0_cfg[card].clock_source = get_softmodem_params()->clock_source;
openair0_cfg[card].time_source = get_softmodem_params()->timing_source;
openair0_cfg[card].tune_offset = get_softmodem_params()->tune_offset;
openair0_cfg[card].tx_num_channels = min(4, frame_parms->nb_antennas_tx);
openair0_cfg[card].rx_num_channels = min(4, frame_parms->nb_antennas_rx);
executables/softmodem-common.h
+4
View File
@@ -60,6 +60,7 @@ extern "C"
#define CONFIG_HLP_DMRSSYNC "tells RU to insert DMRS in subframe 1 slot 0"
#define CONFIG_HLP_CLK "tells hardware to use a clock reference (0:internal, 1:external, 2:gpsdo)\n"
#define CONFIG_HLP_TME "tells hardware to use a time reference (0:internal, 1:external, 2:gpsdo)\n"
#define CONFIG_HLP_TUNE_OFFSET "LO tuning offset to use in Hz\n"
#define CONFIG_HLP_USIM "use XOR autentication algo in case of test usim mode\n"
#define CONFIG_HLP_NOSNGLT "Disables single-thread mode in lte-softmodem\n"
#define CONFIG_HLP_DLF "Set the downlink frequency for all component carriers\n"
@@ -118,6 +119,7 @@ extern "C"
#define EMULATE_RF softmodem_params.emulate_rf
#define CLOCK_SOURCE softmodem_params.clock_source
#define TIMING_SOURCE softmodem_params.timing_source
#define TUNE_OFFSET softmodem_params.tune_offset
#define SEND_DMRSSYNC softmodem_params.send_dmrs_sync
#define USIM_TEST softmodem_params.usim_test
#define PRB_INTERPOLATION softmodem_params.prb_interpolation
@@ -141,6 +143,7 @@ extern int usrp_tx_thread;
{"usim-test", CONFIG_HLP_USIM, PARAMFLAG_BOOL, u8ptr:&USIM_TEST, defintval:0, TYPE_UINT8, 0}, \
{"clock-source", CONFIG_HLP_CLK, 0, uptr:&CLOCK_SOURCE, defintval:0, TYPE_UINT, 0}, \
{"time-source", CONFIG_HLP_TME, 0, uptr:&TIMING_SOURCE, defintval:0, TYPE_UINT, 0}, \
{"tune-offset", CONFIG_HLP_TUNE_OFFSET, 0, dblptr:&TUNE_OFFSET, defintval:0, TYPE_DOUBLE, 0}, \
{"wait-for-sync", NULL, PARAMFLAG_BOOL, iptr:&WAIT_FOR_SYNC, defintval:0, TYPE_INT, 0}, \
{"single-thread-enable", CONFIG_HLP_NOSNGLT, PARAMFLAG_BOOL, iptr:&SINGLE_THREAD_FLAG, defintval:0, TYPE_INT, 0}, \
{"C" , CONFIG_HLP_DLF, 0, u64ptr:&(downlink_frequency[0][0]), defuintval:0, TYPE_UINT64, 0}, \
@@ -245,6 +248,7 @@ typedef struct {
int band;
uint32_t clock_source;
uint32_t timing_source;
double tune_offset;
int hw_timing_advance;
uint32_t send_dmrs_sync;
int prb_interpolation;
nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
+3
View File
@@ -434,6 +434,9 @@ typedef struct {
uint8_t mcs;
uint8_t ndi;
uint8_t rv;
uint16_t targetCodeRate;
uint8_t qamModOrder;
uint32_t TBS;
uint8_t tb2_mcs;
uint8_t tb2_ndi;
uint8_t tb2_rv;
openair1/PHY/CODING/coding_defs.h
-12
View File
@@ -469,18 +469,6 @@ int32_t nr_segmentation(unsigned char *input_buffer,
unsigned int *F,
uint8_t BG);
/*!\fn uint32_t nr_compute_tbs
\brief This function returns the TBS in bits as per 6.1.4.2 of TS 38.214
*/
uint32_t nr_compute_tbs(uint16_t Qm,
uint16_t R,
uint16_t nb_rb,
uint16_t nb_symb_sch,
uint16_t nb_dmrs_prb,
uint16_t nb_rb_oh,
uint8_t tb_scaling,
uint8_t Nl);
void nr_interleaving_ldpc(uint32_t E, uint8_t Qm, uint8_t *e,uint8_t *f);
void nr_deinterleaving_ldpc(uint32_t E, uint8_t Qm, int16_t *e,int16_t *f);
openair1/PHY/INIT/nr_init.c
+24 -24
View File
@@ -673,14 +673,18 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
int N_RB_UL = cfg->carrier_config.ul_grid_size[cfg->ssb_config.scs_common.value].value;
int n_buf = Prx*max_ul_mimo_layers;
int nb_re_pusch = N_RB_UL * NR_NB_SC_PER_RB;
#ifdef __AVX2__
int nb_re_pusch2 = nb_re_pusch + (nb_re_pusch&7);
#else
int nb_re_pusch2 = nb_re_pusch;
#endif
for (int ULSCH_id=0; ULSCH_id<gNB->number_of_nr_ulsch_max; ULSCH_id++) {
pusch_vars[ULSCH_id] = (NR_gNB_PUSCH *)malloc16_clear( sizeof(NR_gNB_PUSCH) );
pusch_vars[ULSCH_id]->rxdataF_ext = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->rxdataF_ext2 = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_estimates = (int32_t **)malloc16(n_buf*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_estimates_ext = (int32_t **)malloc16(n_buf*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_ptrs_estimates = (int32_t **)malloc16(n_buf*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_ptrs_estimates_ext = (int32_t **)malloc16(n_buf*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ptrs_phase_per_slot = (int32_t **)malloc16(n_buf*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_estimates_time = (int32_t **)malloc16(n_buf*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->rxdataF_comp = (int32_t **)malloc16(n_buf*sizeof(int32_t *) );
@@ -688,32 +692,29 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
pusch_vars[ULSCH_id]->ul_ch_magb0 = (int32_t **)malloc16(n_buf*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_mag = (int32_t **)malloc16(n_buf*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_magb = (int32_t **)malloc16(n_buf*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->rho = (int32_t ***)malloc16_clear(Prx*sizeof(int32_t**) );
pusch_vars[ULSCH_id]->rho = (int32_t ***)malloc16(Prx*sizeof(int32_t **) );
pusch_vars[ULSCH_id]->llr_layers = (int16_t **)malloc16(max_ul_mimo_layers*sizeof(int32_t *) );
for (i=0; i<Prx; i++) {
pusch_vars[ULSCH_id]->rxdataF_ext[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->rxdataF_ext2[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->rxdataF_ext[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*nb_re_pusch2*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->rho[i] = (int32_t **)malloc16_clear(NR_MAX_NB_LAYERS*NR_MAX_NB_LAYERS*sizeof(int32_t*));
for (int j=0; j< max_ul_mimo_layers; j++) {
for (int k=0; k<max_ul_mimo_layers; k++) {
pusch_vars[ULSCH_id]->rho[i][j*max_ul_mimo_layers+k]=(int32_t *)malloc16_clear( sizeof(int32_t) * fp->N_RB_UL*12*7*2 );
pusch_vars[ULSCH_id]->rho[i][j*max_ul_mimo_layers+k]=(int32_t *)malloc16_clear( sizeof(int32_t)*nb_re_pusch2*fp->symbols_per_slot );
}
}
}
for (i=0; i<n_buf; i++) {
pusch_vars[ULSCH_id]->ul_ch_estimates[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*fp->ofdm_symbol_size*2*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->ul_ch_estimates_ext[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->ul_ch_estimates_time[i] = (int32_t *)malloc16_clear( 2*sizeof(int32_t)*fp->ofdm_symbol_size );
pusch_vars[ULSCH_id]->ul_ch_ptrs_estimates[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*fp->ofdm_symbol_size*2*fp->symbols_per_slot ); // max intensity in freq is 1 sc every 2 RBs
pusch_vars[ULSCH_id]->ul_ch_ptrs_estimates_ext[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->ul_ch_estimates[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*fp->ofdm_symbol_size*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->ul_ch_estimates_ext[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*nb_re_pusch2*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->ul_ch_estimates_time[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*fp->ofdm_symbol_size );
pusch_vars[ULSCH_id]->ptrs_phase_per_slot[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*fp->symbols_per_slot); // symbols per slot
pusch_vars[ULSCH_id]->rxdataF_comp[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->ul_ch_mag0[i] = (int32_t *)malloc16_clear( fp->symbols_per_slot*sizeof(int32_t)*N_RB_UL*12 );
pusch_vars[ULSCH_id]->ul_ch_magb0[i] = (int32_t *)malloc16_clear( fp->symbols_per_slot*sizeof(int32_t)*N_RB_UL*12 );
pusch_vars[ULSCH_id]->ul_ch_mag[i] = (int32_t *)malloc16_clear( fp->symbols_per_slot*sizeof(int32_t)*N_RB_UL*12 );
pusch_vars[ULSCH_id]->ul_ch_magb[i] = (int32_t *)malloc16_clear( fp->symbols_per_slot*sizeof(int32_t)*N_RB_UL*12 );
pusch_vars[ULSCH_id]->rxdataF_comp[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*nb_re_pusch2*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->ul_ch_mag0[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*nb_re_pusch2*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->ul_ch_magb0[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*nb_re_pusch2*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->ul_ch_mag[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*nb_re_pusch2*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->ul_ch_magb[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*nb_re_pusch2*fp->symbols_per_slot );
}
for (i=0; i< max_ul_mimo_layers; i++) {
@@ -838,7 +839,6 @@ void phy_free_nr_gNB(PHY_VARS_gNB *gNB)
free_and_zero(pusch_vars[ULSCH_id]->llr_layers[i]);
for (int i = 0; i < Prx; i++) {
free_and_zero(pusch_vars[ULSCH_id]->rxdataF_ext[i]);
free_and_zero(pusch_vars[ULSCH_id]->rxdataF_ext2[i]);
for (int j=0; j< max_ul_mimo_layers; j++) {
for (int k=0; k<max_ul_mimo_layers; k++)
free_and_zero(pusch_vars[ULSCH_id]->rho[i][j*max_ul_mimo_layers+k]);
@@ -849,8 +849,6 @@ void phy_free_nr_gNB(PHY_VARS_gNB *gNB)
free_and_zero(pusch_vars[ULSCH_id]->ul_ch_estimates[i]);
free_and_zero(pusch_vars[ULSCH_id]->ul_ch_estimates_ext[i]);
free_and_zero(pusch_vars[ULSCH_id]->ul_ch_estimates_time[i]);
free_and_zero(pusch_vars[ULSCH_id]->ul_ch_ptrs_estimates[i]);
free_and_zero(pusch_vars[ULSCH_id]->ul_ch_ptrs_estimates_ext[i]);
free_and_zero(pusch_vars[ULSCH_id]->ptrs_phase_per_slot[i]);
free_and_zero(pusch_vars[ULSCH_id]->rxdataF_comp[i]);
free_and_zero(pusch_vars[ULSCH_id]->ul_ch_mag0[i]);
@@ -860,11 +858,8 @@ void phy_free_nr_gNB(PHY_VARS_gNB *gNB)
}
free_and_zero(pusch_vars[ULSCH_id]->llr_layers);
free_and_zero(pusch_vars[ULSCH_id]->rxdataF_ext);
free_and_zero(pusch_vars[ULSCH_id]->rxdataF_ext2);
free_and_zero(pusch_vars[ULSCH_id]->ul_ch_estimates);
free_and_zero(pusch_vars[ULSCH_id]->ul_ch_estimates_ext);
free_and_zero(pusch_vars[ULSCH_id]->ul_ch_ptrs_estimates);
free_and_zero(pusch_vars[ULSCH_id]->ul_ch_ptrs_estimates_ext);
free_and_zero(pusch_vars[ULSCH_id]->ptrs_phase_per_slot);
free_and_zero(pusch_vars[ULSCH_id]->ul_ch_estimates_time);
free_and_zero(pusch_vars[ULSCH_id]->ul_valid_re_per_slot);
@@ -928,7 +923,12 @@ void nr_phy_config_request_sim(PHY_VARS_gNB *gNB,
//gNB_config->subframe_config.dl_cyclic_prefix_type.value = (fp->Ncp == NORMAL) ? NFAPI_CP_NORMAL : NFAPI_CP_EXTENDED;
gNB->mac_enabled = 1;
if (mu==1) {
if (mu==0) {
fp->dl_CarrierFreq = 2600000000;//from_nrarfcn(gNB_config->nfapi_config.rf_bands.rf_band[0],gNB_config->nfapi_config.nrarfcn.value);
fp->ul_CarrierFreq = 2600000000;//fp->dl_CarrierFreq - (get_uldl_offset(gNB_config->nfapi_config.rf_bands.rf_band[0])*100000);
fp->nr_band = 38;
// fp->threequarter_fs= 0;
} else if (mu==1) {
fp->dl_CarrierFreq = 3600000000;//from_nrarfcn(gNB_config->nfapi_config.rf_bands.rf_band[0],gNB_config->nfapi_config.nrarfcn.value);
fp->ul_CarrierFreq = 3600000000;//fp->dl_CarrierFreq - (get_uldl_offset(gNB_config->nfapi_config.rf_bands.rf_band[0])*100000);
fp->nr_band = 78;
openair1/PHY/INIT/nr_init_ue.c
-4
View File
@@ -76,7 +76,6 @@ void phy_init_nr_ue_PDSCH(NR_UE_PDSCH *const pdsch,
pdsch->dl_ch_magr0 = (int32_t **)malloc16_clear( NR_MAX_NB_LAYERS*fp->nb_antennas_rx*sizeof(int32_t *) );
pdsch->ptrs_phase_per_slot = (int32_t **)malloc16_clear( fp->nb_antennas_rx*sizeof(int32_t *) );
pdsch->ptrs_re_per_slot = (int32_t **)malloc16_clear( fp->nb_antennas_rx*sizeof(int32_t *) );
pdsch->dl_ch_ptrs_estimates_ext = (int32_t **)malloc16_clear( fp->nb_antennas_rx*sizeof(int32_t *) );
// the allocated memory size is fixed:
AssertFatal( fp->nb_antennas_rx <= 4, "nb_antennas_rx > 4" );//Extend the max number of UE Rx antennas to 4
@@ -86,7 +85,6 @@ void phy_init_nr_ue_PDSCH(NR_UE_PDSCH *const pdsch,
pdsch->rxdataF_uespec_pilots[i] = (int32_t *)malloc16_clear( sizeof(int32_t) * fp->N_RB_DL*12);
pdsch->ptrs_phase_per_slot[i] = (int32_t *)malloc16_clear( sizeof(int32_t) * 14 );
pdsch->ptrs_re_per_slot[i] = (int32_t *)malloc16_clear( sizeof(int32_t) * 14);
pdsch->dl_ch_ptrs_estimates_ext[i] = (int32_t *)malloc16_clear( sizeof(int32_t) * num);
pdsch->rho[i] = (int32_t **)malloc16_clear( NR_MAX_NB_LAYERS*NR_MAX_NB_LAYERS*sizeof(int32_t *) );
for (int j=0; j<NR_MAX_NB_LAYERS; j++) {
@@ -126,7 +124,6 @@ void phy_term_nr_ue__PDSCH(NR_UE_PDSCH* pdsch, const NR_DL_FRAME_PARMS *const fp
free_and_zero(pdsch->rxdataF_uespec_pilots[i]);
free_and_zero(pdsch->ptrs_phase_per_slot[i]);
free_and_zero(pdsch->ptrs_re_per_slot[i]);
free_and_zero(pdsch->dl_ch_ptrs_estimates_ext[i]);
free_and_zero(pdsch->rho[i]);
}
free_and_zero(pdsch->pmi_ext);
@@ -149,7 +146,6 @@ void phy_term_nr_ue__PDSCH(NR_UE_PDSCH* pdsch, const NR_DL_FRAME_PARMS *const fp
free_and_zero(pdsch->dl_ch_magr0);
free_and_zero(pdsch->ptrs_phase_per_slot);
free_and_zero(pdsch->ptrs_re_per_slot);
free_and_zero(pdsch->dl_ch_ptrs_estimates_ext);
}
int init_nr_ue_signal(PHY_VARS_NR_UE *ue, int nb_connected_gNB)
openair1/PHY/MODULATION/nr_modulation.c
+2 -1
View File
@@ -665,8 +665,9 @@ void init_symbol_rotation(NR_DL_FRAME_PARMS *fp) {
void init_timeshift_rotation(NR_DL_FRAME_PARMS *fp)
{
const int sample_offset = fp->nb_prefix_samples / fp->ofdm_offset_divisor;
for (int i = 0; i < fp->ofdm_symbol_size; i++) {
double poff = -i * 2.0 * M_PI * 144.0 / 2048.0 / fp->ofdm_offset_divisor;
double poff = -i * 2.0 * M_PI * sample_offset / fp->ofdm_symbol_size;
double exp_re = cos(poff);
double exp_im = sin(-poff);
fp->timeshift_symbol_rotation[i*2] = (int16_t)round(exp_re * 32767);
openair1/PHY/MODULATION/slot_fep_nr.c
+3 -44
View File
@@ -34,47 +34,6 @@
#define LOG_I(A,B...) printf(A)
#endif*/
dft_size_idx_t get_dft_size_idx(uint16_t ofdm_symbol_size)
{
switch (ofdm_symbol_size) {
case 128:
return DFT_128;
case 256:
return DFT_256;
case 512:
return DFT_512;
case 1024:
return DFT_1024;
case 1536:
return DFT_1536;
case 2048:
return DFT_2048;
case 3072:
return DFT_3072;
case 4096:
return DFT_4096;
case 6144:
return DFT_6144;
case 8192:
return DFT_8192;
default:
printf("unsupported ofdm symbol size \n");
assert(0);
}
return DFT_SIZE_IDXTABLESIZE;
}
int nr_slot_fep(PHY_VARS_NR_UE *ue,
UE_nr_rxtx_proc_t *proc,
unsigned char symbol,
@@ -96,7 +55,7 @@ int nr_slot_fep(PHY_VARS_NR_UE *ue,
nb_prefix_samples0 = frame_parms->nb_prefix_samples;
}
dft_size_idx_t dftsize = get_dft_size_idx(frame_parms->ofdm_symbol_size);
dft_size_idx_t dftsize = get_dft(frame_parms->ofdm_symbol_size);
// This is for misalignment issues
int32_t tmp_dft_in[8192] __attribute__ ((aligned (32)));
@@ -195,7 +154,7 @@ int nr_slot_fep_init_sync(PHY_VARS_NR_UE *ue,
}
unsigned int frame_length_samples = frame_parms->samples_per_frame;
dft_size_idx_t dftsize = get_dft_size_idx(frame_parms->ofdm_symbol_size);
dft_size_idx_t dftsize = get_dft(frame_parms->ofdm_symbol_size);
// This is for misalignment issues
int32_t tmp_dft_in[8192] __attribute__ ((aligned (32)));
@@ -289,7 +248,7 @@ int nr_slot_fep_ul(NR_DL_FRAME_PARMS *frame_parms,
unsigned int nb_prefix_samples = frame_parms->nb_prefix_samples;
unsigned int nb_prefix_samples0 = frame_parms->nb_prefix_samples0;
dft_size_idx_t dftsize = get_dft_size_idx(frame_parms->ofdm_symbol_size);
dft_size_idx_t dftsize = get_dft(frame_parms->ofdm_symbol_size);
// This is for misalignment issues
int32_t tmp_dft_in[8192] __attribute__ ((aligned (32)));
openair1/PHY/NR_ESTIMATION/nr_ul_channel_estimation.c
+15 -1
View File
@@ -665,6 +665,10 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
ch[0] = ch_0 / 4;
ch[1] = ch_1 / 4;
#if NO_INTERP
for (int i=0;i<12;i++) ((int32_t*)ul_ch)[i] = *(int32_t*)ch;
ul_ch+=24;
#else
multadd_real_vector_complex_scalar(filt8_avlip0,
ch,
ul_ch,
@@ -682,6 +686,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
ul_ch,
8);
ul_ch -= 24;
#endif
for (pilot_cnt=4; pilot_cnt<4*(nb_rb_pusch-1); pilot_cnt += 4) {
@@ -716,6 +721,10 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
ch[0] = ch_0 / 4;
ch[1] = ch_1 / 4;
#if NO_INTERP
for (int i=0;i<12;i++) ((int32_t*)ul_ch)[i] = *(int32_t*)ch;
ul_ch+=24;
#else
ul_ch[6] += (ch[0] * 1365)>>15; // 1/12*16384
ul_ch[7] += (ch[1] * 1365)>>15; // 1/12*16384
@@ -737,6 +746,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
ul_ch,
8);
ul_ch -= 16;
#endif
}
// Last PRB
ch_0 = ((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15;
@@ -770,6 +780,10 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
ch[0] = ch_0 / 4;
ch[1] = ch_1 / 4;
#if NO_INTERP
for (int i=0;i<12;i++) ((int32_t*)ul_ch)[i] = *(int32_t*)ch;
ul_ch+=24;
#else
ul_ch[6] += (ch[0] * 1365)>>15; // 1/12*16384
ul_ch[7] += (ch[1] * 1365)>>15; // 1/12*16384
@@ -784,6 +798,7 @@ int nr_pusch_channel_estimation(PHY_VARS_gNB *gNB,
ch,
ul_ch,
8);
#endif
}
#ifdef DEBUG_PUSCH
ul_ch = (int16_t *)&ul_ch_estimates[p*gNB->frame_parms.nb_antennas_rx+aarx][ch_offset];
@@ -890,7 +905,6 @@ void nr_pusch_ptrs_processing(PHY_VARS_gNB *gNB,
/*------------------------------------------------------------------------------------------------------- */
nr_ptrs_cpe_estimation(*K_ptrs,*ptrsReOffset,*dmrsConfigType,*nb_rb,
rel15_ul->rnti,
(int16_t *)&gNB->pusch_vars[ulsch_id]->ul_ch_ptrs_estimates_ext[aarx][symbol*nb_re_pusch],
nr_tti_rx,
symbol,frame_parms->ofdm_symbol_size,
(int16_t*)&gNB->pusch_vars[ulsch_id]->rxdataF_comp[aarx][(symbol * nb_re_pusch)],
openair1/PHY/NR_REFSIG/dmrs_nr.c
-68
View File
@@ -295,74 +295,6 @@ uint16_t get_dmrs_freq_idx_ul(uint16_t n, uint8_t k_prime, uint8_t delta, uint8_
#define CHECK_DMRS_PBCH_SEQUENCE
void generate_dmrs_pbch(uint32_t dmrs_pbch_bitmap[DMRS_PBCH_I_SSB][DMRS_PBCH_N_HF][DMRS_BITMAP_SIZE], uint16_t Nid_cell)
{
uint32_t cinit;
int i_ssb;
int n_hf;
int _i_ssb;
#ifdef CHECK_DMRS_PBCH_SEQUENCE
uint32_t dmrs_bitmap[DMRS_PBCH_I_SSB][DMRS_PBCH_N_HF][DMRS_BITMAP_SIZE];
uint32_t *dmrs_sequence = calloc(CELL_DMRS_LENGTH, sizeof(uint32_t));
if (dmrs_sequence == NULL) {
msg("Fatal error: memory allocation problem \n");
assert(0);
}
else
{
printf("Check of demodulation reference signal of pbch sequence \n");
}
#endif
/* for each slot number */
for (i_ssb = 0; i_ssb<DMRS_PBCH_I_SSB; i_ssb++) {
/* for each ofdm position */
for (n_hf=0; n_hf<DMRS_PBCH_N_HF; n_hf++) {
_i_ssb = i_ssb + 4*n_hf;
cinit = (((_i_ssb + 1)*((Nid_cell>>4) + 1))<<11) + ((_i_ssb + 1)<<6) + (Nid_cell%4);
pseudo_random_sequence_optimised(DMRS_BITMAP_SIZE, &(dmrs_pbch_bitmap[i_ssb][n_hf][0]), cinit);
#ifdef CHECK_DMRS_PBCH_SEQUENCE
/* it allows checking generated with standard generation code */
pseudo_random_sequence(DMRS_BITMAP_SIZE*sizeof(uint32_t), dmrs_sequence, cinit);
int j = 0;
int k = 0;
/* format for getting bitmap from uint32_t */
for (int i=0; i<DMRS_BITMAP_SIZE; i++) {
dmrs_bitmap[i_ssb][n_hf][i] = 0;
/* convert to bitmap */
for (; j < k + 32; j++) {
dmrs_bitmap[i_ssb][n_hf][i] |= (dmrs_sequence[j]<<j);
}
k = j;
}
for (int i=0; i<DMRS_BITMAP_SIZE; i++) {
if (dmrs_pbch_bitmap[i_ssb][n_hf][i] != dmrs_bitmap[i_ssb][n_hf][i]) {
printf("Error in gold sequence computation for ns %d l %d and index %i : 0x%x 0x%x \n", i_ssb, n_hf, i, dmrs_pbch_bitmap[i_ssb][n_hf][i], dmrs_bitmap[i_ssb][n_hf][i]);
assert(0);
}
}
#endif
}
}
#ifdef CHECK_DMRS_PBCH_SEQUENCE
free(dmrs_sequence);
#endif
}
/* return the position of next dmrs symbol in a slot */
int8_t get_next_dmrs_symbol_in_slot(uint16_t ul_dmrs_symb_pos, uint8_t counter, uint8_t end_symbol)
{
openair1/PHY/NR_REFSIG/dmrs_nr.h
-1
View File
@@ -53,7 +53,6 @@
int pseudo_random_sequence(int M_PN, uint32_t *c, uint32_t cinit);
void lte_gold_new(LTE_DL_FRAME_PARMS *frame_parms, uint32_t lte_gold_table[20][2][14], uint16_t Nid_cell);
void generate_dmrs_pbch(uint32_t dmrs_pbch_bitmap[DMRS_PBCH_I_SSB][DMRS_PBCH_N_HF][DMRS_BITMAP_SIZE], uint16_t Nid_cell);
uint16_t get_dmrs_freq_idx_ul(uint16_t n, uint8_t k_prime, uint8_t delta, uint8_t dmrs_type);
uint8_t allowed_xlsch_re_in_dmrs_symbol(uint16_t k,
openair1/PHY/NR_REFSIG/pss_nr.h
-2
View File
@@ -120,8 +120,6 @@ EXTERN time_stats_t generic_time[TIME_LAST];
/************** FUNCTION ******************************************/
idft_size_idx_t get_idft(int ofdm_symbol_size);
dft_size_idx_t get_dft(int ofdm_symbol_size);
void init_context_synchro_nr(NR_DL_FRAME_PARMS *frame_parms_ue);
void free_context_synchro_nr(void);
void init_context_pss_nr(NR_DL_FRAME_PARMS *frame_parms_ue);
openair1/PHY/NR_REFSIG/ptrs_nr.c
+4 -5
View File
@@ -230,7 +230,6 @@ int8_t get_next_estimate_in_slot(uint16_t ptrsSymbPos,uint16_t dmrsSymbPos, ui
* dmrsConfigType: DMRS configuration type
* nb_rb : No. of resource blocks
* rnti : RNTI
* ptrs_ch_p : pointer to ptrs channel structure
* Ns :
* symbol : OFDM symbol
* ofdm_symbol_size: OFDM Symbol Size
@@ -249,7 +248,6 @@ void nr_ptrs_cpe_estimation(uint8_t K_ptrs,
uint8_t dmrsConfigType,
uint16_t nb_rb,
uint16_t rnti,
int16_t *ptrs_ch_p,
unsigned char Ns,
unsigned char symbol,
uint16_t ofdm_symbol_size,
@@ -269,6 +267,7 @@ void nr_ptrs_cpe_estimation(uint8_t K_ptrs,
}
uint16_t sc_per_symbol = (nb_rb + K_ptrs - 1)/K_ptrs;
c16_t ptrs_p[(1 + sc_per_symbol/4)*4];
c16_t ptrs_ch_p[(1 + sc_per_symbol/4)*4];
c16_t dmrs_comp_p[(1 + sc_per_symbol/4)*4];
double abs = 0.0;
double real = 0.0;
@@ -306,13 +305,13 @@ void nr_ptrs_cpe_estimation(uint8_t K_ptrs,
*ptrs_sc = re_cnt;
/*Multiple compensated data with conj of PTRS */
mult_cpx_vector((int16_t*)dmrs_comp_p, (int16_t*)ptrs_p, ptrs_ch_p,(1 + sc_per_symbol/4)*4,15); // 2^15 shifted
mult_cpx_vector((int16_t*)dmrs_comp_p, (int16_t*)ptrs_p, (int16_t*)ptrs_ch_p, (1 + sc_per_symbol/4)*4, 15); // 2^15 shifted
/* loop over all ptrs sub carriers in a symbol */
/* sum the error vector */
for(int i = 0;i < sc_per_symbol; i++) {
real+= ptrs_ch_p[(2*i)];
imag+= ptrs_ch_p[(2*i)+1];
real += ptrs_ch_p[i].r;
imag += ptrs_ch_p[i].i;
}
#ifdef DEBUG_PTRS
alpha = atan(imag/real);
openair1/PHY/NR_REFSIG/ptrs_nr.h
-1
View File
@@ -96,7 +96,6 @@ void nr_ptrs_cpe_estimation(uint8_t K_ptrs,
uint8_t dmrsConfigType,
uint16_t nb_rb,
uint16_t rnti,
int16_t *ptrs_ch_p,
unsigned char Ns,
unsigned char symbol,
uint16_t ofdm_symbol_size,
openair1/PHY/NR_REFSIG/ss_pbch_nr.h
-2
View File
@@ -80,8 +80,6 @@
/* see TS 38211 7.4.1.4 Demodulation reference signals for PBCH */
#define DMRS_PBCH_I_SSB (8) /* maximum index value for SSB/PBCH which can have alength of L=4 or L=8 */
#define DMRS_PBCH_N_HF (2) /* half frame indication - 0 for first part of frame and 1 for second part of frame */
#define DMRS_ALIGNMENT_32_BIT (20) /* it is just for ensuring a 32 bits alignment for storing dmrs pbch into a 32 bits map */
#define DMRS_BITMAP_SIZE ((DMRS_PBCH_NUMBER-DMRS_ALIGNMENT_32_BIT)/32) /* size is divided by 32 (to get bitmap on uint32) DMRS_PBCH_NUMBER should be a multiple of 32 */
#endif /* SS_PBCH_NR_H */
openair1/PHY/NR_TRANSPORT/nr_dlsch.h
-5
View File
@@ -49,11 +49,6 @@ void nr_get_rbg_parms(NR_BWP_PARMS* bwp, uint8_t config_type);
void nr_get_rbg_list(uint32_t bitmap, uint8_t n_rbg, uint8_t* rbg_list);
uint8_t nr_get_Qm(uint8_t Imcs, uint8_t table_idx);
uint32_t nr_get_code_rate(uint8_t Imcs, uint8_t table_idx);
void nr_pdsch_codeword_scrambling(uint8_t *in,
uint32_t size,
uint8_t q,
openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c
+4 -6
View File
@@ -306,12 +306,11 @@ int nr_dlsch_encoding(PHY_VARS_gNB *gNB,
unsigned int crc=1;
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &harq->pdsch_pdu.pdsch_pdu_rel15;
impp.Zc = &harq->Z;
float Coderate = 0.0;
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_gNB_DLSCH_ENCODING, VCD_FUNCTION_IN);
uint32_t A = rel15->TBSize[0]<<3;
unsigned char *a=harq->pdu;
if ( rel15->rnti != SI_RNTI)
trace_NRpdu(DIRECTION_DOWNLINK, a, rel15->TBSize[0], 0, WS_C_RNTI, rel15->rnti, frame, slot,0, 0);
trace_NRpdu(DIRECTION_DOWNLINK, a, rel15->TBSize[0], WS_C_RNTI, rel15->rnti, frame, slot,0, 0);
NR_gNB_SCH_STATS_t *stats=NULL;
int first_free=-1;
@@ -369,10 +368,9 @@ int nr_dlsch_encoding(PHY_VARS_gNB *gNB,
memcpy(harq->b, a, (A / 8) + 3); // using 3 bytes to mimic the case of 24 bit crc
}
if (rel15->targetCodeRate[0]<1000)
Coderate = (float)rel15->targetCodeRate[0] /(float) 1024;
else // to scale for mcs 20 and 26 in table 5.1.3.1-2 which are decimal and input 2* in nr_tbs_tools
Coderate = (float)rel15->targetCodeRate[0] /(float) 2048;
// target_code_rate is in 0.1 units
float Coderate = (float) rel15->targetCodeRate[0] / 10240.0f;
LOG_D(PHY,"DLSCH Coderate %f\n",Coderate);
if ((A <=292) || ((A<=3824) && (Coderate <= 0.6667)) || Coderate <= 0.25)
impp.BG = 2;
openair1/PHY/NR_TRANSPORT/nr_prach.c
+124 -382
View File
@@ -175,11 +175,19 @@ void rx_nr_prach_ru(RU_t *ru,
int msg1_frequencystart = ru->config.prach_config.num_prach_fd_occasions_list[numRA].k1.value;
int sample_offset_slot;
if (!(slot%(fp->slots_per_subframe/2)))
sample_offset_slot = (prachStartSymbol==0?0:fp->ofdm_symbol_size*prachStartSymbol+fp->nb_prefix_samples0+fp->nb_prefix_samples*(prachStartSymbol-1));
else
sample_offset_slot = (prachStartSymbol==0?0:prachStartSymbol*(fp->ofdm_symbol_size+fp->nb_prefix_samples));
//to be checked for mu=0;
if (prachStartSymbol == 0) {
sample_offset_slot = 0;
} else if (fp->slots_per_subframe == 1) {
if (prachStartSymbol <= 7)
sample_offset_slot = (fp->ofdm_symbol_size + fp->nb_prefix_samples) * (prachStartSymbol - 1) + (fp->ofdm_symbol_size + fp->nb_prefix_samples0);
else
sample_offset_slot = (fp->ofdm_symbol_size + fp->nb_prefix_samples) * (prachStartSymbol - 2) + (fp->ofdm_symbol_size + fp->nb_prefix_samples0) * 2;
} else {
if (!(slot%(fp->slots_per_subframe/2)))
sample_offset_slot = (fp->ofdm_symbol_size + fp->nb_prefix_samples) * (prachStartSymbol - 1) + (fp->ofdm_symbol_size + fp->nb_prefix_samples0);
else
sample_offset_slot = (fp->ofdm_symbol_size + fp->nb_prefix_samples) * prachStartSymbol;
}
LOG_D(PHY,"frame %d, slot %d: doing rx_nr_prach_ru for format %d, numRA %d, prachStartSymbol %d, prachOccasion %d\n",frame,slot,prachFormat,numRA,prachStartSymbol,prachOccasion);
@@ -193,89 +201,167 @@ void rx_nr_prach_ru(RU_t *ru,
prach[aa] = (int16_t*)&ru->common.rxdata[aa][fp->get_samples_slot_timestamp(slot2,fp,0)+sample_offset_slot-ru->N_TA_offset];
}
idft_size_idx_t dftsize;
int dftlen=0;
int reps;
int Ncp;
int dftlen;
int mu = fp->numerology_index;
int Ncp = 0;
int16_t *prach2;
if (prach_sequence_length == 0) {
LOG_D(PHY,"PRACH (ru %d) in %d.%d, format %d, msg1_frequencyStart %d\n",
ru->idx,frame,slot2,prachFormat,msg1_frequencystart);
AssertFatal(prachFormat<4,"Illegal prach format %d for length 839\n",prachFormat);
switch (prachFormat) {
case 0:
reps = 1;
Ncp = 3168;
dftlen = 24576;
break;
case 1:
reps = 2;
Ncp = 21024;
dftlen = 24576;
break;
case 2:
reps = 4;
Ncp = 4688;
dftlen = 24576;
break;
case 3:
reps = 4;
Ncp = 3168;
dftlen = 6144;
break;
default:
AssertFatal(1==0, "Illegal prach format %d for length 839\n", prachFormat);
break;
}
}
else {
LOG_D(PHY,"PRACH (ru %d) in %d.%d, format %s, msg1_frequencyStart %d,startSymbol %d\n",
ru->idx,frame,slot,prachfmt[prachFormat],msg1_frequencystart,prachStartSymbol);
switch (prachFormat) {
case 4: //A1
Ncp = 288/(1<<mu);
reps = 2;
Ncp = 288 >> mu;
break;
case 5: //A2
Ncp = 576/(1<<mu);
reps = 4;
Ncp = 576 >> mu;
break;
case 6: //A3
Ncp = 864/(1<<mu);
reps = 6;
Ncp = 864 >> mu;
break;
case 7: //B1
Ncp = 216/(1<<mu);
break;
reps = 2;
Ncp = 216 >> mu;
break;
/*
// B2 and B3 do not exist in FAPI
case 4: //B2
Ncp = 360/(1<<mu);
reps = 4;
Ncp = 360 >> mu;
break;
case 5: //B3
Ncp = 504/(1<<mu);
reps = 6;
Ncp = 504 >> mu;
break;
*/
case 8: //B4
Ncp = 936/(1<<mu);
reps = 12;
Ncp = 936 >> mu;
break;
case 9: //C0
Ncp = 1240/(1<<mu);
reps = 1;
Ncp = 1240 >> mu;
break;
case 10: //C2
Ncp = 2048/(1<<mu);
reps = 4;
Ncp = 2048 >> mu;
break;
default:
AssertFatal(1==0,"unknown prach format %x\n",prachFormat);
break;
}
dftlen = 2048 >> mu;
}
//actually what we should be checking here is how often the current prach crosses a 0.5ms boundary. I am not quite sure for which paramter set this would be the case, so I will ignore it for now and just check if the prach starts on a 0.5ms boundary
if(fp->numerology_index == 0) {
if (prachStartSymbol == 0 || prachStartSymbol == 7)
Ncp += 16;
}
else {
if (slot%(fp->slots_per_subframe/2)==0 && prachStartSymbol == 0)
Ncp += 16;
}
switch(fp->samples_per_subframe) {
case 7680:
// 5 MHz @ 7.68 Ms/s
Ncp >>= 2;
dftlen >>= 2;
break;
case 15360:
// 10, 15 MHz @ 15.36 Ms/s
Ncp >>= 1;
dftlen >>= 1;
break;
case 30720:
// 20, 25, 30 MHz @ 30.72 Ms/s
Ncp = Ncp;
dftlen = dftlen;
break;
case 46080:
// 40 MHz @ 46.08 Ms/s
Ncp = (Ncp*3)/2;
dftlen = (dftlen*3)/2;
break;
case 61440:
// 40, 50, 60 MHz @ 61.44 Ms/s
Ncp <<= 1;
dftlen <<= 1;
break;
case 92160:
// 50, 60, 70, 80, 90 MHz @ 92.16 Ms/s
Ncp *= 3;
dftlen *= 3;
break;
case 122880:
// 70, 80, 90, 100 MHz @ 122.88 Ms/s
Ncp <<= 2;
dftlen <<= 2;
break;
default:
AssertFatal(1==0,"sample rate %f MHz not supported for numerology %d\n", fp->samples_per_subframe / 1000.0, mu);
}
const idft_size_idx_t dftsize = get_dft(dftlen);
// Do forward transform
if (LOG_DEBUGFLAG(PRACH)) {
LOG_D(PHY,"rx_prach: Doing PRACH FFT for nb_rx:%d Ncp:%d\n",ru->nb_rx, Ncp);
LOG_D(PHY, "rx_prach: Doing PRACH FFT for nb_rx:%d Ncp:%d dftlen:%d\n", ru->nb_rx, Ncp, dftlen);
}
// Note: Assumes PUSCH SCS @ 30 kHz, take values for formats 0-2 and adjust for others below
int kbar = 1;
@@ -299,357 +385,13 @@ void rx_nr_prach_ru(RU_t *ru,
k*=K;
k+=kbar;
int reps=1;
for (int aa=0; aa<ru->nb_rx; aa++) {
AssertFatal(prach[aa]!=NULL,"prach[%d] is null\n",aa);
// do DFT
if (mu==1) {
switch(fp->samples_per_subframe) {
case 15360:
// 10, 15 MHz @ 15.36 Ms/s
prach2 = prach[aa] + (1*Ncp); // Ncp is for 30.72 Ms/s, so divide by 2 to bring to 15.36 Ms/s and multiply by 2 for I/Q
if (prach_sequence_length == 0) {
if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) {
dftlen=12288;
dft(DFT_12288,prach2,rxsigF[aa],1);
}
if (prachFormat == 1 || prachFormat == 2) {
dft(DFT_12288,prach2+24576,rxsigF[aa]+24576,1);
reps++;
}
if (prachFormat == 2) {
dft(DFT_12288,prach2+(24576*2),rxsigF[aa]+(24576*2),1);
dft(DFT_12288,prach2+(24576*3),rxsigF[aa]+(24576*3),1);
reps+=2;
}
if (prachFormat == 3) {
dftlen=3072;
for (int i=0;i<4;i++) dft(DFT_3072,prach2+(i*3072*2),rxsigF[aa]+(i*3072*2),1);
reps=4;
}
} else { // 839 sequence
if (prachStartSymbol == 0) prach2+=16; // 8 samples @ 15.36 Ms/s in first symbol of each half subframe (15/30 kHz only)
dftlen=512;
dft(DFT_512,prach2,rxsigF[aa],1);
if (prachFormat != 9/*C0*/) {
dft(DFT_512,prach2+1024,rxsigF[aa]+1024,1);
reps++;
}
if (prachFormat == 5/*A2*/ || prachFormat == 6/*A3*/|| prachFormat == 8/*B4*/ || prachFormat == 10/*C2*/) {
dft(DFT_512,prach2+1024*2,rxsigF[aa]+1024*2,1);
dft(DFT_512,prach2+1024*3,rxsigF[aa]+1024*3,1);
reps+=2;
}
if (prachFormat == 6/*A3*/ || prachFormat == 8/*B4*/) {
dft(DFT_512,prach2+1024*4,rxsigF[aa]+1024*4,1);
dft(DFT_512,prach2+1024*5,rxsigF[aa]+1024*5,1);
reps+=2;
}
if (prachFormat == 8/*B4*/) {
for (int i=6;i<12;i++) dft(DFT_512,prach2+(1024*i),rxsigF[aa]+(1024*i),1);
reps+=6;
}
}
break;
case 30720:
// 20, 25, 30 MHz @ 30.72 Ms/s
prach2 = prach[aa] + (2*Ncp); // Ncp is for 30.72 Ms/s, so just multiply by 2 for I/Q
if (prach_sequence_length == 0) {
if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) {
dftlen=24576;
dft(DFT_24576,prach2,rxsigF[aa],1);
}
if (prachFormat == 1 || prachFormat == 2) {
dft(DFT_24576,prach2+49152,rxsigF[aa]+49152,1);
reps++;
}
if (prachFormat == 2) {
dft(DFT_24576,prach2+(49152*2),rxsigF[aa]+(49152*2),1);
dft(DFT_24576,prach2+(49152*3),rxsigF[aa]+(49152*3),1);
reps+=2;
}
if (prachFormat == 3) {
dftlen=6144;
for (int i=0;i<4;i++) dft(DFT_6144,prach2+(i*6144*2),rxsigF[aa]+(i*6144*2),1);
reps=4;
}
} else { // 839 sequence
if (prachStartSymbol == 0) prach2+=32; // 16 samples @ 30.72 Ms/s in first symbol of each half subframe (15/30 kHz only)
dftlen=1024;
dft(DFT_1024,prach2,rxsigF[aa],1);
if (prachFormat != 9/*C0*/) {
dft(DFT_1024,prach2+2048,rxsigF[aa]+2048,1);
reps++;
}
if (prachFormat == 5/*A2*/ || prachFormat == 6/*A3*/|| prachFormat == 8/*B4*/ || prachFormat == 10/*C2*/) {
dft(DFT_1024,prach2+2048*2,rxsigF[aa]+2048*2,1);
dft(DFT_1024,prach2+2048*3,rxsigF[aa]+2048*3,1);
reps+=2;
}
if (prachFormat == 6/*A3*/ || prachFormat == 8/*B4*/) {
dft(DFT_1024,prach2+2048*4,rxsigF[aa]+2048*4,1);
dft(DFT_1024,prach2+2048*5,rxsigF[aa]+2048*5,1);
reps+=2;
}
if (prachFormat == 8/*B4*/) {
for (int i=6;i<12;i++) dft(DFT_1024,prach2+(2048*i),rxsigF[aa]+(2048*i),1);
reps+=6;
}
}
break;
case 61440:
// 40, 50, 60 MHz @ 61.44 Ms/s
prach2 = prach[aa] + (4*Ncp); // Ncp is for 30.72 Ms/s, so multiply by 2 for I/Q, and 2 to bring to 61.44 Ms/s
if (prach_sequence_length == 0) {
if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) {
dftlen=49152;
dft(DFT_49152,prach2,rxsigF[aa],1);
}
if (prachFormat == 1 || prachFormat == 2) {
dft(DFT_49152,prach2+98304,rxsigF[aa]+98304,1);
reps++;
}
if (prachFormat == 2) {
dft(DFT_49152,prach2+(98304*2),rxsigF[aa]+(98304*2),1);
dft(DFT_49152,prach2+(98304*3),rxsigF[aa]+(98304*3),1);
reps+=2;
}
if (prachFormat == 3) {
dftlen=12288;
for (int i=0;i<4;i++) dft(DFT_12288,prach2+(i*12288*2),rxsigF[aa]+(i*12288*2),1);
reps=4;
}
} else { // 839 sequence
if (prachStartSymbol == 0) prach2+=64; // 32 samples @ 61.44 Ms/s in first symbol of each half subframe (15/30 kHz only)
dftlen=2048;
dft(DFT_2048,prach2,rxsigF[aa],1);
if (prachFormat != 9/*C0*/) {
dft(DFT_2048,prach2+4096,rxsigF[aa]+4096,1);
reps++;
}
if (prachFormat == 5/*A2*/ || prachFormat == 6/*A3*/|| prachFormat == 8/*B4*/ || prachFormat == 10/*C2*/) {
dft(DFT_2048,prach2+4096*2,rxsigF[aa]+4096*2,1);
dft(DFT_2048,prach2+4096*3,rxsigF[aa]+4096*3,1);
reps+=2;
}
if (prachFormat == 6/*A3*/ || prachFormat == 8/*B4*/) {
dft(DFT_2048,prach2+4096*4,rxsigF[aa]+4096*4,1);
dft(DFT_2048,prach2+4096*5,rxsigF[aa]+4096*5,1);
reps+=2;
}
if (prachFormat == 8/*B4*/) {
for (int i=6;i<12;i++) dft(DFT_2048,prach2+(4096*i),rxsigF[aa]+(4096*i),1);
reps+=6;
}
}
break;
case 46080:
// 40 MHz @ 46.08 Ms/s
prach2 = prach[aa] + (3*Ncp); // 46.08 is 1.5 * 30.72, times 2 for I/Q
if (prach_sequence_length == 0) {
if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) {
dftlen=36864;
dft(DFT_36864,prach2,rxsigF[aa],1);
}
if (prachFormat == 1 || prachFormat == 2) {
dft(DFT_36864,prach2+73728,rxsigF[aa]+73728,1);
reps++;
}
if (prachFormat == 2) {
dft(DFT_36864,prach2+(73728*2),rxsigF[aa]+(73728*2),1);
dft(DFT_36864,prach2+(73728*3),rxsigF[aa]+(73728*3),1);
reps+=2;
}
if (prachFormat == 3) {
dftlen=9216;
for (int i=0;i<4;i++) dft(DFT_9216,prach2+(i*9216*2),rxsigF[aa]+(i*9216*2),1);
reps=4;
}
} else { // 839 sequence
if (prachStartSymbol == 0) prach2+=48; // 24 samples @ 46.08 Ms/s in first symbol of each half subframe (15/30 kHz only)
dftlen=1536;
dft(DFT_1536,prach2,rxsigF[aa],1);
if (prachFormat != 9/*C0*/) {
dft(DFT_1536,prach2+3072,rxsigF[aa]+3072,1);
reps++;
}
if (prachFormat == 5/*A2*/ || prachFormat == 6/*A3*/|| prachFormat == 8/*B4*/ || prachFormat == 10/*C2*/) {
dft(DFT_1536,prach2+3072*2,rxsigF[aa]+3072*2,1);
dft(DFT_1536,prach2+3072*3,rxsigF[aa]+3072*3,1);
reps+=2;
}
if (prachFormat == 6/*A3*/ || prachFormat == 8/*B4*/) {
dft(DFT_1536,prach2+3072*4,rxsigF[aa]+3072*4,1);
dft(DFT_1536,prach2+3072*5,rxsigF[aa]+3072*5,1);
reps+=2;
}
if (prachFormat == 8/*B4*/) {
for (int i=6;i<12;i++) dft(DFT_1536,prach2+(3072*i),rxsigF[aa]+(3072*i),1);
reps+=6;
}
}
break;
case 122880:
// 70, 80, 90, 100 MHz @ 122.88 Ms/s
prach2 = prach[aa] + (8*Ncp);
if (prach_sequence_length == 0) {
if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) {
dftlen=98304;
dft(DFT_98304,prach2,rxsigF[aa],1);
}
if (prachFormat == 1 || prachFormat == 2) {
dft(DFT_98304,prach2+196608,rxsigF[aa]+196608,1);
reps++;
}
if (prachFormat == 2) {
dft(DFT_98304,prach2+(196608*2),rxsigF[aa]+(196608*2),1);
dft(DFT_98304,prach2+(196608*3),rxsigF[aa]+(196608*3),1);
reps+=2;
}
if (prachFormat == 3) {
dftlen=24576;
for (int i=0;i<4;i++) dft(DFT_24576,prach2+(i*2*24576),rxsigF[aa]+(i*2*24576),1);
reps=4;
}
} else { // 839 sequence
if (prachStartSymbol == 0) prach2+=128; // 64 samples @ 122.88 Ms/s in first symbol of each half subframe (15/30 kHz only)
dftlen=4096;
dft(DFT_4096,prach2,rxsigF[aa],1);
if (prachFormat != 9/*C0*/) {
dft(DFT_4096,prach2+8192,rxsigF[aa]+8192,1);
reps++;
}
if (prachFormat == 5/*A2*/ || prachFormat == 6/*A3*/|| prachFormat == 8/*B4*/ || prachFormat == 10/*C2*/) {
dft(DFT_4096,prach2+8192*2,rxsigF[aa]+8192*2,1);
dft(DFT_4096,prach2+8192*3,rxsigF[aa]+8192*3,1);
reps+=2;
}
if (prachFormat == 6/*A3*/ || prachFormat == 8/*B4*/) {
dft(DFT_4096,prach2+8192*4,rxsigF[aa]+8192*4,1);
dft(DFT_4096,prach2+8192*5,rxsigF[aa]+8192*5,1);
reps+=2;
}
if (prachFormat == 8/*B4*/) {
for (int i=6;i<12;i++) dft(DFT_4096,prach2+(8192*i),rxsigF[aa]+(8192*i),1);
reps+=6;
}
}
break;
case 92160:
// 80, 90 MHz @ 92.16 Ms/s
prach2 = prach[aa] + (6*Ncp);
if (prach_sequence_length == 0) {
if (prachFormat == 0 || prachFormat == 1 || prachFormat == 2) {
dftlen=73728;
dft(DFT_73728,prach2,rxsigF[aa],1);
}
if (prachFormat == 1 || prachFormat == 2) {
dft(DFT_73728,prach2+147456,rxsigF[aa]+147456,1);
reps++;
}
if (prachFormat == 2) {
dft(DFT_73728,prach2+(147456*2),rxsigF[aa]+(147456*2),1);
dft(DFT_73728,prach2+(147456*3),rxsigF[aa]+(147456*3),1);
reps+=2;
}
if (prachFormat == 3) {
dftlen=18432;
for (int i=0;i<4;i++) dft(DFT_18432,prach2+(i*2*18432),rxsigF[aa]+(i*2*18432),1);
reps=4;
}
} else {
if (prachStartSymbol == 0) prach2+=96; // 64 samples @ 122.88 Ms/s in first symbol of each half subframe (15/30 kHz only)
dftlen=3072;
dft(DFT_3072,prach2,rxsigF[aa],1);
if (prachFormat != 9/*C0*/) {
dft(DFT_3072,prach2+6144,rxsigF[aa]+6144,1);
reps++;
}
if (prachFormat == 5/*A2*/ || prachFormat == 6/*A3*/|| prachFormat == 8/*B4*/ || prachFormat == 10/*C2*/) {
dft(DFT_3072,prach2+6144*2,rxsigF[aa]+6144*2,1);
dft(DFT_3072,prach2+6144*3,rxsigF[aa]+6144*3,1);
reps+=2;
}
if (prachFormat == 6/*A3*/ || prachFormat == 8/*B4*/) {
dft(DFT_3072,prach2+6144*4,rxsigF[aa]+6144*4,1);
dft(DFT_3072,prach2+6144*5,rxsigF[aa]+6144*5,1);
reps+=2;
}
if (prachFormat == 8/*B4*/) {
for (int i=6;i<12;i++) dft(DFT_3072,prach2+(6144*i),rxsigF[aa]+(6144*i),1);
reps+=6;
}
}
break;
default:
AssertFatal(1==0,"sample_rate %f MHz not support for NR PRACH yet\n", fp->samples_per_subframe / 1000.0);
}
}
else if (mu==3) {
if (fp->threequarter_fs) {
AssertFatal(1==0,"3/4 sampling not supported for numerology %d\n",mu);
}
if (prach_sequence_length == 0) {
AssertFatal(1==0,"long prach not supported for numerology %d\n",mu);
}
if (fp->N_RB_UL == 32) {
prach2 = prach[aa] + (Ncp<<2); // Ncp is for 30.72 Ms/s, so multiply by 2 for I/Q, and 2 for 61.44Msps
if (slot%(fp->slots_per_subframe/2)==0 && prachStartSymbol == 0)
prach2+=64; // 32 samples @ 61.44 Ms/s in first symbol of each half subframe
dftlen=512;
dftsize = DFT_512;
}
else if (fp->N_RB_UL == 66) {
prach2 = prach[aa] + (Ncp<<3); // Ncp is for 30.72 Ms/s, so multiply by 4 for I/Q, and 2 for 122.88Msps
if (slot%(fp->slots_per_subframe/2)==0 && prachStartSymbol == 0)
prach2+=128; // 64 samples @ 122.88 Ms/s in first symbol of each half subframe
dftlen=1024;
dftsize = DFT_1024;
}
else {
AssertFatal(1==0,"N_RB_UL %d not support for numerology %d\n",fp->N_RB_UL,mu);
}
dft(dftsize,prach2,rxsigF[aa],1);
if (prachFormat != 9/*C0*/) {
dft(dftsize,prach2+dftlen*2,rxsigF[aa]+dftlen*2,1);
reps++;
}
if (prachFormat == 5/*A2*/ || prachFormat == 6/*A3*/|| prachFormat == 8/*B4*/ || prachFormat == 10/*C2*/) {
dft(dftsize,prach2+dftlen*4,rxsigF[aa]+dftlen*4,1);
dft(dftsize,prach2+dftlen*6,rxsigF[aa]+dftlen*6,1);
reps+=2;
}
if (prachFormat == 6/*A3*/ || prachFormat == 8/*B4*/) {
dft(dftsize,prach2+dftlen*8,rxsigF[aa]+dftlen*8,1);
dft(dftsize,prach2+dftlen*10,rxsigF[aa]+dftlen*10,1);
reps+=2;
}
if (prachFormat == 8/*B4*/) {
for (int i=6;i<12;i++)
dft(dftsize,prach2+(dftlen*2*i),rxsigF[aa]+(dftlen*2*i),1);
reps+=6;
}
}
else {
AssertFatal(1==0,"Numerology not supported\n");
}
int16_t *prach2 = prach[aa] + (2*Ncp); // times 2 for complex samples
for (int i = 0; i < reps; i++)
dft(dftsize, prach2 + 2*dftlen*i, rxsigF[aa] + 2*dftlen*i, 1);
//LOG_M("ru_rxsigF_tmp.m","rxsFtmp", rxsigF[aa], dftlen*2*reps, 1, 1);
openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h
-8
View File
@@ -60,14 +60,6 @@ uint32_t nr_get_G(uint16_t nb_rb, uint16_t nb_symb_sch, uint8_t nb_re_dmrs, uint
uint32_t nr_get_E(uint32_t G, uint8_t C, uint8_t Qm, uint8_t Nl, uint8_t r);
uint8_t nr_get_Qm_ul(uint8_t Imcs, uint8_t table_idx);
uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx);
uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx);
uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx);
void compute_nr_prach_seq(uint8_t short_sequence,
uint8_t num_sequences,
uint8_t rootSequenceIndex,
openair1/PHY/NR_TRANSPORT/nr_ulsch_decoding.c
+5 -10
View File
@@ -407,13 +407,10 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB,
phy_vars_gNB->nbDecode = 0;
harq_process->processedSegments = 0;
double Coderate = 0.0;
// ------------------------------------------------------------------
uint16_t nb_rb = pusch_pdu->rb_size;
uint8_t Qm = pusch_pdu->qam_mod_order;
uint16_t R = pusch_pdu->target_code_rate;
uint8_t mcs = pusch_pdu->mcs_index;
uint8_t n_layers = pusch_pdu->nrOfLayers;
// ------------------------------------------------------------------
@@ -442,14 +439,12 @@ uint32_t nr_ulsch_decoding(PHY_VARS_gNB *phy_vars_gNB,
A = (harq_process->TBS)<<3;
LOG_D(PHY,"ULSCH Decoding, harq_pid %d TBS %d G %d mcs %d Nl %d nb_rb %d, Qm %d, Coderate %d RV %d round %d\n",
harq_pid, A, G, mcs, n_layers, nb_rb, Qm, R, pusch_pdu->pusch_data.rv_index, harq_process->round);
// target_code_rate is in 0.1 units
float Coderate = (float) pusch_pdu->target_code_rate / 10240.0f;
LOG_D(PHY,"ULSCH Decoding, harq_pid %d TBS %d G %d mcs %d Nl %d nb_rb %d, Qm %d, Coderate %f RV %d round %d\n",
harq_pid, A, G, mcs, n_layers, nb_rb, Qm, Coderate, pusch_pdu->pusch_data.rv_index, harq_process->round);
if (R<1024)
Coderate = (float) R /(float) 1024;
else
Coderate = (float) R /(float) 2048;
if ((A <=292) || ((A<=3824) && (Coderate <= 0.6667)) || Coderate <= 0.25){
p_decParams->BG = 2;
kc = 52;
openair1/PHY/NR_TRANSPORT/pucch_rx.c
+1 -1
View File
@@ -190,7 +190,7 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB,
pucch_pdu->bit_len_harq,pucch_pdu->sr_flag);
NR_gNB_UCI_STATS_t *uci_stats=NULL;
NR_gNB_UCI_STATS_t *first_uci_stats=NULL;
NR_gNB_UCI_STATS_t *first_uci_stats = gNB->uci_stats;
for (int i=0;i<NUMBER_OF_NR_UCI_STATS_MAX;i++)
if (gNB->uci_stats[i].rnti == pucch_pdu->rnti) {
uci_stats = &gNB->uci_stats[i];
openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c
+33 -2
View File
@@ -34,6 +34,7 @@
//#define DEBUG_PDSCH
//#define DEBUG_PDCCH
#define NO_INTERP 1
int nr_pbch_dmrs_correlation(PHY_VARS_NR_UE *ue,
UE_nr_rxtx_proc_t *proc,
@@ -692,7 +693,7 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
k = bwp_start_subcarrier;
int re_offset = k;
#ifdef DEBUG_CH
#ifdef DEBUG_PDSCH
printf("PDSCH Channel Estimation : ThreadId %d, gNB_id %d ch_offset %d, symbol_offset %d OFDM size %d, Ncp=%d, Ns=%d, k=%d symbol %d\n",proc->thread_id, gNB_id,ch_offset,symbol_offset,ue->frame_parms.ofdm_symbol_size,
ue->frame_parms.Ncp,Ns,k, symbol);
#endif
@@ -1244,6 +1245,10 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
ch[0] = ch_0 / 6;
ch[1] = ch_1 / 6;
#if NO_INTERP
for (int i=0;i<12;i++) ((int32_t*)dl_ch)[i] = *(int32_t*)ch;
dl_ch+=24;
#else
multadd_real_vector_complex_scalar(filt8_avlip0,
ch,
dl_ch,
@@ -1261,6 +1266,7 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
dl_ch,
8);
dl_ch -= 24;
#endif
for (pilot_cnt=6; pilot_cnt<6*(nb_rb_pdsch-1); pilot_cnt += 6) {
@@ -1308,6 +1314,11 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
ch[0] = ch_0 / 6;
ch[1] = ch_1 / 6;
#if NO_INTERP
for (int i=0;i<12;i++) ((int32_t*)dl_ch)[i] = *(int32_t*)ch;
dl_ch+=24;
#else
dl_ch[6] += (ch[0] * 1365)>>15; // 1/12*16384
dl_ch[7] += (ch[1] * 1365)>>15; // 1/12*16384
@@ -1329,6 +1340,7 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
dl_ch,
8);
dl_ch -= 16;
#endif
}
ch_0 = ((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15;
ch_1 = ((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15;
@@ -1375,6 +1387,10 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
ch[0] = ch_0 / 6;
ch[1] = ch_1 / 6;
#if NO_INTERP
for (int i=0;i<12;i++) ((int32_t*)dl_ch)[i] = *(int32_t*)ch;
dl_ch+=24;
#else
dl_ch[6] += (ch[0] * 1365)>>15; // 1/12*16384
dl_ch[7] += (ch[1] * 1365)>>15; // 1/12*16384
@@ -1389,6 +1405,7 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
ch,
dl_ch,
8);
#endif
}
else { // this is case without frequency-domain linear interpolation, just take average of LS channel estimates of 4 DMRS REs and use a common value for the whole PRB
int32_t ch_0, ch_1;
@@ -1424,6 +1441,10 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
ch[0] = ch_0 / 4;
ch[1] = ch_1 / 4;
#if NO_INTERP
for (int i=0;i<12;i++) ((int32_t*)dl_ch)[i] = *(int32_t*)ch;
dl_ch+=24;
#else
multadd_real_vector_complex_scalar(filt8_avlip0,
ch,
dl_ch,
@@ -1441,6 +1462,7 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
dl_ch,
8);
dl_ch -= 24;
#endif
for (pilot_cnt=4; pilot_cnt<4*(nb_rb_pdsch-1); pilot_cnt += 4) {
int32_t ch_0, ch_1;
@@ -1476,6 +1498,10 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
ch[0] = ch_0 / 4;
ch[1] = ch_1 / 4;
#if NO_INTERP
for (int i=0;i<12;i++) ((int32_t*)dl_ch)[i] = *(int32_t*)ch;
dl_ch+=24;
#else
dl_ch[6] += (ch[0] * 1365)>>15; // 1/12*16384
dl_ch[7] += (ch[1] * 1365)>>15; // 1/12*16384
@@ -1497,6 +1523,7 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
dl_ch,
8);
dl_ch -= 16;
#endif
}
ch_0 = ((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15;
@@ -1530,6 +1557,10 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
ch[0] = ch_0 / 4;
ch[1] = ch_1 / 4;
#if NO_INTERP
for (int i=0;i<12;i++) ((int32_t*)dl_ch)[i] = *(int32_t*)ch;
dl_ch+=24;
#else
dl_ch[6] += (ch[0] * 1365)>>15; // 1/12*16384
dl_ch[7] += (ch[1] * 1365)>>15; // 1/12*16384
@@ -1544,6 +1575,7 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
ch,
dl_ch,
8);
#endif
}
#ifdef DEBUG_PDSCH
dl_ch = (int16_t *)&dl_ch_estimates[p*ue->frame_parms.nb_antennas_rx+aarx][ch_offset];
@@ -1673,7 +1705,6 @@ void nr_pdsch_ptrs_processing(PHY_VARS_NR_UE *ue,
/*------------------------------------------------------------------------------------------------------- */
nr_ptrs_cpe_estimation(*K_ptrs,*ptrsReOffset,*dmrsConfigType,*nb_rb,
rnti,
(int16_t *)&pdsch_vars[gNB_id]->dl_ch_ptrs_estimates_ext[aarx][symbol*nb_re_pdsch],
nr_slot_rx,
symbol,frame_parms->ofdm_symbol_size,
(int16_t*)&pdsch_vars[gNB_id]->rxdataF_comp0[aarx][(symbol * nb_re_pdsch)],
openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c
+6 -11
View File
@@ -430,8 +430,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
uint16_t nb_symb_sch,
uint8_t nr_slot_rx,
uint8_t harq_pid,
uint8_t is_crnti,
uint8_t llr8_flag) {
uint8_t is_crnti) {
uint32_t A,E;
uint32_t G;
uint32_t ret,offset;
@@ -449,7 +448,6 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
LOG_D(PHY,"Round %d RV idx %d\n",harq_process->DLround,harq_process->rvidx);
uint8_t kc;
uint16_t nb_rb;// = 30;
double Coderate;// = 0.0;
uint8_t dmrs_Type = harq_process->dmrsConfigType;
AssertFatal(dmrs_Type == 0 || dmrs_Type == 1, "Illegal dmrs_type %d\n", dmrs_Type);
uint8_t nb_re_dmrs;
@@ -499,21 +497,18 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
*/
nb_rb = harq_process->nb_rb;
harq_process->trials[harq_process->DLround]++;
uint16_t nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs
harq_process->TBS = nr_compute_tbs(harq_process->Qm,harq_process->R,nb_rb,nb_symb_sch,nb_re_dmrs*dmrs_length, nb_rb_oh, 0, harq_process->Nl);
A = harq_process->TBS;
ret = dlsch->max_ldpc_iterations + 1;
dlsch->last_iteration_cnt = ret;
harq_process->G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, dmrs_length, harq_process->Qm,harq_process->Nl);
G = harq_process->G;
LOG_D(PHY,"%d.%d DLSCH Decoding, harq_pid %d TBS %d (%d) G %d nb_re_dmrs %d length dmrs %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",
frame,nr_slot_rx,harq_pid,A,A/8,G, nb_re_dmrs, dmrs_length, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb);
// target_code_rate is in 0.1 units
float Coderate = (float) harq_process->R / 10240.0f;
if ((harq_process->R)<1024)
Coderate = (float) (harq_process->R) /(float) 1024;
else
Coderate = (float) (harq_process->R) /(float) 2048;
LOG_D(PHY,"%d.%d DLSCH Decoding, harq_pid %d TBS %d (%d) G %d nb_re_dmrs %d length dmrs %d mcs %d Nl %d nb_symb_sch %d nb_rb %d Qm %d Coderate %f\n",
frame,nr_slot_rx,harq_pid,A,A/8,G, nb_re_dmrs, dmrs_length, harq_process->mcs, harq_process->Nl, nb_symb_sch, nb_rb, harq_process->Qm, Coderate);
if ((A <=292) || ((A <= NR_MAX_PDSCH_TBS) && (Coderate <= 0.6667)) || Coderate <= 0.25) {
p_decParams->BG = 2;
openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c
+1 -8
View File
@@ -260,13 +260,6 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
return -1;
}
dlsch0_harq->Qm = nr_get_Qm_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table);
dlsch0_harq->R = nr_get_code_rate_dl(dlsch[0]->harq_processes[harq_pid]->mcs, dlsch[0]->harq_processes[harq_pid]->mcs_table);
if (dlsch0_harq->Qm == 0 || dlsch0_harq->R == 0) {
LOG_W(MAC, "Invalid code rate or Mod order, likely due to unexpected DL DCI.\n");
return -1;
}
#ifdef DEBUG_HARQ
printf("[DEMOD] MIMO mode = %d\n", dlsch0_harq->mimo_mode);
printf("[DEMOD] cw for TB0 = %d, cw for TB1 = %d\n", codeword_TB0, codeword_TB1);
@@ -2600,7 +2593,7 @@ static int nr_dlsch_llr(NR_UE_PDSCH **pdsch_vars,
}
if (dlsch1_harq) {
switch (nr_get_Qm_dl(dlsch1_harq->mcs,dlsch1_harq->mcs_table)) {
switch (dlsch1_harq->Qm) {
case 2 :
if (rx_type==rx_standard) {
nr_dlsch_qpsk_llr(frame_parms,
openair1/PHY/NR_UE_TRANSPORT/nr_prach.c
+223 -857
View File
File diff suppressed because it is too large Load Diff
openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h
+1 -2
View File
@@ -1013,8 +1013,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
uint16_t nb_symb_sch,
uint8_t nr_slot_rx,
uint8_t harq_pid,
uint8_t is_crnti,
uint8_t llr8_flag);
uint8_t is_crnti);
int nr_ulsch_encoding(PHY_VARS_NR_UE *ue,
NR_UE_ULSCH_t *ulsch,
openair1/PHY/NR_UE_TRANSPORT/nr_ue_rf_helpers.c
+4 -3
View File
@@ -67,7 +67,7 @@ void nr_rf_card_config_gain(openair0_config_t *openair0_cfg,
openair0_cfg->autocal[i] = 1;
if (i < openair0_cfg->rx_num_channels) {
LOG_I(PHY, "HW: Configuring channel %d (rf_chain %d): setting tx_gain %f, rx_gain %f\n",
LOG_I(PHY, "HW: Configuring channel %d (rf_chain %d): setting tx_gain %.0f, rx_gain %.0f\n",
i,
rf_chain,
openair0_cfg->tx_gain[i],
@@ -103,11 +103,12 @@ void nr_rf_card_config_freq(openair0_config_t *openair0_cfg,
openair0_cfg->autocal[i] = 1;
if (i < openair0_cfg->rx_num_channels) {
LOG_I(PHY, "HW: Configuring channel %d (rf_chain %d): setting tx_freq %f Hz, rx_freq %f Hz\n",
LOG_I(PHY, "HW: Configuring channel %d (rf_chain %d): setting tx_freq %.0f Hz, rx_freq %.0f Hz, tune_offset %.0f\n",
i,
rf_chain,
openair0_cfg->tx_freq[i],
openair0_cfg->rx_freq[i]);
openair0_cfg->rx_freq[i],
openair0_cfg->tune_offset);
}
}
openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_coding.c
+5 -10
View File
@@ -192,14 +192,14 @@ int nr_ulsch_encoding(PHY_VARS_NR_UE *ue,
unsigned int crc = 1;
NR_UL_UE_HARQ_t *harq_process = ulsch->harq_processes[harq_pid];
uint16_t nb_rb = harq_process->pusch_pdu.rb_size;
uint32_t A = harq_process->pusch_pdu.pusch_data.tb_size*8;
uint32_t A = harq_process->pusch_pdu.pusch_data.tb_size<<3;
uint32_t *pz = &harq_process->Z;
uint8_t mod_order = nr_get_Qm_ul(harq_process->pusch_pdu.mcs_index, harq_process->pusch_pdu.mcs_table);
uint16_t R = nr_get_code_rate_ul(harq_process->pusch_pdu.mcs_index, harq_process->pusch_pdu.mcs_table);
uint8_t mod_order = harq_process->pusch_pdu.qam_mod_order;
uint16_t Kr=0;
uint32_t r_offset=0;
uint32_t F=0;
float Coderate = 0.0;
// target_code_rate is in 0.1 units
float Coderate = (float) harq_process->pusch_pdu.target_code_rate / 10240.0f;
///////////
/////////////////////////////////////////////////////////////////////////////////////////
@@ -207,7 +207,7 @@ int nr_ulsch_encoding(PHY_VARS_NR_UE *ue,
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_NR_UE_ULSCH_ENCODING, VCD_FUNCTION_IN);
LOG_D(NR_PHY, "ulsch coding nb_rb %d, Nl = %d\n", nb_rb, harq_process->pusch_pdu.nrOfLayers);
LOG_D(NR_PHY, "ulsch coding A %d G %d mod_order %d\n", A, G, mod_order);
LOG_D(NR_PHY, "ulsch coding A %d G %d mod_order %d Coderate %f\n", A, G, mod_order, Coderate);
LOG_D(NR_PHY, "harq_pid %d harq_process->ndi %d, pusch_data.new_data_indicator %d\n",
harq_pid,harq_process->ndi,harq_process->pusch_pdu.pusch_data.new_data_indicator);
@@ -264,11 +264,6 @@ int nr_ulsch_encoding(PHY_VARS_NR_UE *ue,
///////////////////////// b---->| block segmentation |---->c /////////////////////////
///////////
if (R<1024)
Coderate = (float) R /(float) 1024;
else
Coderate = (float) R /(float) 2048;
if ((A <=292) || ((A<=3824) && (Coderate <= 0.6667)) || Coderate <= 0.25){
harq_process->BG = 2;
}
openair1/PHY/NR_UE_TRANSPORT/nr_ulsch_ue.c
+1 -1
View File
@@ -171,7 +171,7 @@ void nr_ue_ulsch_procedures(PHY_VARS_NR_UE *UE,
trace_NRpdu(DIRECTION_UPLINK,
harq_process_ul_ue->a,
harq_process_ul_ue->pusch_pdu.pusch_data.tb_size,
0, WS_C_RNTI, rnti, frame, slot, 0, 0);
WS_C_RNTI, rnti, frame, slot, 0, 0);
if (nr_ulsch_encoding(UE, ulsch_ue, frame_parms, harq_pid, G) == -1)
return;
openair1/PHY/NR_UE_TRANSPORT/pss_nr.c
-118
View File
@@ -48,126 +48,8 @@
#include "PHY/NR_REFSIG/sss_nr.h"
#include "PHY/NR_UE_TRANSPORT/cic_filter_nr.h"
/*******************************************************************
*
* NAME : get_idft
*
* PARAMETERS : size of ofdm symbol
*
* RETURN : index pointing to the dft func in the dft library
*
* DESCRIPTION : get idft function depending of ofdm size
*
*********************************************************************/
//#define DBG_PSS_NR
idft_size_idx_t get_idft(int ofdm_symbol_size)
{
switch (ofdm_symbol_size) {
case 128:
return IDFT_128;
break;
case 256:
return IDFT_256;
break;
case 512:
return IDFT_512;
break;
case 1024:
return IDFT_1024;
break;
case 1536:
return IDFT_1536;
break;
case 2048:
return IDFT_2048;
break;
case 3072:
return IDFT_3072;
break;
case 4096:
return IDFT_4096;
break;
case 8192:
return IDFT_8192;
break;
default:
printf("function get_idft : unsupported ofdm symbol size \n");
assert(0);
break;
}
return IDFT_SIZE_IDXTABLESIZE; // never reached and will trigger assertion in idft function
}
/*******************************************************************
*
* NAME : get_dft
*
* PARAMETERS : size of ofdm symbol
*
* RETURN : function for discrete fourier transform
*
* DESCRIPTION : get dft function depending of ofdm size
*
*********************************************************************/
dft_size_idx_t get_dft(int ofdm_symbol_size)
{
switch (ofdm_symbol_size) {
case 128:
return DFT_128;
break;
case 256:
return DFT_256;
break;
case 512:
return DFT_512;
break;
case 1024:
return DFT_1024;
break;
case 1536:
return DFT_1536;
break;
case 2048:
return DFT_2048;
break;
case 4096:
return DFT_4096;
break;
case 8192:
return DFT_8192;
break;
default:
printf("function get_dft : unsupported ofdm symbol size \n");
assert(0);
break;
}
return DFT_SIZE_IDXTABLESIZE; // never reached and will trigger assertion in idft function;
}
/*******************************************************************
*
* NAME : generate_pss_nr
openair1/PHY/TOOLS/tools_defs.h
+119
View File
@@ -33,7 +33,9 @@
extern "C" {
#endif
#include <stdio.h>
#include <stdint.h>
#include <assert.h>
#include "PHY/sse_intrin.h"
#define CEILIDIV(a,b) ((a+b-1)/b)
@@ -315,6 +317,65 @@ typedef enum dft_size_idx {
#define SZ_iENUM(Sz) IDFT_ ## Sz,
/*******************************************************************
*
* NAME : get_dft
*
* PARAMETERS : size of ofdm symbol
*
* RETURN : function for discrete fourier transform
*
* DESCRIPTION : get dft function depending of ofdm size
*
*********************************************************************/
static inline
dft_size_idx_t get_dft(int ofdm_symbol_size)
{
switch (ofdm_symbol_size) {
case 128:
return DFT_128;
case 256:
return DFT_256;
case 512:
return DFT_512;
case 1024:
return DFT_1024;
case 1536:
return DFT_1536;
case 2048:
return DFT_2048;
case 3072:
return DFT_3072;
case 4096:
return DFT_4096;
case 6144:
return DFT_6144;
case 8192:
return DFT_8192;
case 9216:
return DFT_9216;
case 12288:
return DFT_12288;
case 18432:
return DFT_18432;
case 24576:
return DFT_24576;
case 36864:
return DFT_36864;
case 49152:
return DFT_49152;
case 73728:
return DFT_73728;
case 98304:
return DFT_98304;
default:
printf("function get_dft : unsupported ofdm symbol size \n");
assert(0);
break;
}
return DFT_SIZE_IDXTABLESIZE; // never reached and will trigger assertion in idft function;
}
typedef enum idft_size_idx {
FOREACH_IDFTSZ(SZ_iENUM)
IDFT_SIZE_IDXTABLESIZE
@@ -340,6 +401,64 @@ struct {
#endif
/*******************************************************************
*
* NAME : get_idft
*
* PARAMETERS : size of ofdm symbol
*
* RETURN : index pointing to the dft func in the dft library
*
* DESCRIPTION : get idft function depending of ofdm size
*
*********************************************************************/
static inline
idft_size_idx_t get_idft(int ofdm_symbol_size)
{
switch (ofdm_symbol_size) {
case 128:
return IDFT_128;
case 256:
return IDFT_256;
case 512:
return IDFT_512;
case 1024:
return IDFT_1024;
case 1536:
return IDFT_1536;
case 2048:
return IDFT_2048;
case 3072:
return IDFT_3072;
case 4096:
return IDFT_4096;
case 6144:
return IDFT_6144;
case 8192:
return IDFT_8192;
case 9216:
return IDFT_9216;
case 12288:
return IDFT_12288;
case 18432:
return IDFT_18432;
case 24576:
return IDFT_24576;
case 36864:
return IDFT_36864;
case 49152:
return IDFT_49152;
case 73728:
return IDFT_73728;
case 98304:
return IDFT_98304;
default:
printf("function get_idft : unsupported ofdm symbol size \n");
assert(0);
break;
}
return IDFT_SIZE_IDXTABLESIZE; // never reached and will trigger assertion in idft function
}
/*!\fn int32_t rotate_cpx_vector(int16_t *x,int16_t *alpha,int16_t *y,uint32_t N,uint16_t output_shift)
openair1/PHY/defs_gNB.h
-12
View File
@@ -428,10 +428,6 @@ typedef struct {
/// - first index: rx antenna id [0..nb_antennas_rx[
/// - second index: ? [0..2*ofdm_symbol_size[
int32_t **rxdataF_ext;
/// \brief Holds the received data in the frequency domain for the allocated RBs in normal format.
/// - first index: rx antenna id [0..nb_antennas_rx[
/// - second index (definition from phy_init_lte_eNB()): ? [0..12*N_RB_UL*frame_parms->symbols_per_tti[
int32_t **rxdataF_ext2;
/// \brief Hold the channel estimates in time domain based on DRS.
/// - first index: rx antenna id [0..nb_antennas_rx[
/// - second index: ? [0..4*ofdm_symbol_size[
@@ -444,14 +440,6 @@ typedef struct {
/// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
/// - second index: ? [0..12*N_RB_UL*frame_parms->symbols_per_tti[
int32_t **ul_ch_estimates_ext;
/// \brief Hold the PTRS phase estimates in frequency domain.
/// - first index: rx antenna id [0..nb_antennas_rx[
/// - second index: ? [0..12*N_RB_UL*frame_parms->symbols_per_tti[
int32_t **ul_ch_ptrs_estimates;
/// \brief Uplink phase estimates extracted in PRBS.
/// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
/// - second index: ? [0..12*N_RB_UL*frame_parms->symbols_per_tti[
int32_t **ul_ch_ptrs_estimates_ext;
/// \brief Holds the compensated signal.
/// - first index: rx antenna id [0..nb_antennas_rx[
/// - second index: ? [0..12*N_RB_UL*frame_parms->symbols_per_tti[
openair1/PHY/defs_nr_UE.h
-4
View File
@@ -279,10 +279,6 @@ typedef struct {
/// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
/// - second index: ? [0..168*N_RB_DL[
int32_t **dl_ch_estimates_ext;
/// \brief Downlink channel estimates extracted in PRBS.
/// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
/// - second index: ? [0..168*N_RB_DL[
int32_t **dl_ch_ptrs_estimates_ext;
/// \brief Downlink beamforming channel estimates in frequency domain.
/// - first index: ? [0..7] (hard coded) FIXME! accessed via \c nb_antennas_rx
/// - second index: samples? [0..symbols_per_tti*(ofdm_symbol_size+LTE_CE_FILTER_LENGTH)[
openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
+3
View File
@@ -315,6 +315,9 @@ void configure_dlsch(NR_UE_DLSCH_t *dlsch0,
dlsch0_harq->mcs = dlsch_config_pdu->mcs;
dlsch0_harq->rvidx = dlsch_config_pdu->rv;
dlsch0->g_pucch = dlsch_config_pdu->accumulated_delta_PUCCH;
dlsch0_harq->R = dlsch_config_pdu->targetCodeRate;
dlsch0_harq->Qm = dlsch_config_pdu->qamModOrder;
dlsch0_harq->TBS = dlsch_config_pdu->TBS;
dlsch0_harq->tbslbrm = dlsch_config_pdu->tbslbrm;
dlsch0_harq->nscid = dlsch_config_pdu->nscid;
dlsch0_harq->dlDmrsScramblingId = dlsch_config_pdu->dlDmrsScramblingId;
openair1/SCHED_NR_UE/phy_procedures_nr_ue.c
+2 -5
View File
@@ -134,7 +134,6 @@ void nr_fill_rx_indication(fapi_nr_rx_indication_t *rx_ind,
trace_NRpdu(DIRECTION_DOWNLINK,
dlsch0->harq_processes[dlsch0->current_harq_pid]->b,
dlsch0->harq_processes[dlsch0->current_harq_pid]->TBS / 8,
pdu_type,
WS_C_RNTI,
dlsch0->rnti,
proc->frame_rx,
@@ -802,8 +801,7 @@ bool nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
nb_symb_sch,
nr_slot_rx,
harq_pid,
pdsch==PDSCH?1:0,
dlsch0->harq_processes[harq_pid]->TBS>256?1:0);
pdsch==PDSCH);
LOG_T(PHY,"dlsch decoding, ret = %d\n", ret);
@@ -879,8 +877,7 @@ bool nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
nb_symb_sch,
nr_slot_rx,
harq_pid,
pdsch==PDSCH?1:0,//proc->decoder_switch,
dlsch1->harq_processes[harq_pid]->TBS>256?1:0);
pdsch==PDSCH);//proc->decoder_switch
LOG_T(PHY,"CW dlsch decoding, ret1 = %d\n", ret1);
stop_meas(&ue->dlsch_decoding_stats[proc->thread_id]);
openair1/SIMULATION/NR_PHY/dlschsim.c
+9 -10
View File
@@ -47,6 +47,7 @@
#include "openair1/SIMULATION/RF/rf.h"
#include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h"
#include "openair1/SIMULATION/NR_PHY/nr_dummy_functions.c"
#include "openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h"
//#define DEBUG_NR_DLSCHSIM
@@ -430,13 +431,10 @@ int main(int argc, char **argv)
NR_gNB_DLSCH_t *dlsch = msgDataTx.dlsch[0][0];
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &dlsch->harq_process.pdsch_pdu.pdsch_pdu_rel15;
//time_stats_t *rm_stats, *te_stats, *i_stats;
uint8_t is_crnti = 0, llr8_flag = 0;
uint8_t is_crnti = 0;
unsigned int TBS = 8424;
unsigned int available_bits;
uint8_t nb_re_dmrs = 6; // No data in dmrs symbol
uint16_t length_dmrs = 1;
unsigned char mod_order;
uint16_t rate;
uint8_t Nl = 1;
uint8_t rvidx = 0;
dlsch->rnti = 1;
@@ -444,9 +442,9 @@ int main(int argc, char **argv)
dlsch->harq_processes[0]->rvidx = rvidx;*/
//printf("dlschsim harqid %d nb_rb %d, mscs %d\n",dlsch->harq_ids[subframe],
// dlsch->harq_processes[0]->nb_rb,dlsch->harq_processes[0]->mcs,dlsch->harq_processes[0]->Nl);
mod_order = nr_get_Qm_dl(Imcs, mcs_table);
rate = nr_get_code_rate_dl(Imcs, mcs_table);
available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, 1);
unsigned char mod_order = nr_get_Qm_dl(Imcs, mcs_table);
uint16_t rate = nr_get_code_rate_dl(Imcs, mcs_table);
unsigned int available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, 1);
TBS = nr_compute_tbs(mod_order,rate, nb_rb, nb_symb_sch, nb_re_dmrs*length_dmrs, 0, 0, Nl);
printf("available bits %u TBS %u mod_order %d\n", available_bits, TBS, mod_order);
//dlsch->harq_ids[subframe]= 0;
@@ -478,6 +476,7 @@ int main(int argc, char **argv)
harq_process->Qm = mod_order;
harq_process->rvidx = rvidx;
harq_process->R = rate;
harq_process->TBS = TBS;
harq_process->dmrsConfigType = NFAPI_NR_DMRS_TYPE1;
harq_process->dlDmrsSymbPos = 4;
harq_process->n_dmrs_cdm_groups = 1;
@@ -498,8 +497,8 @@ int main(int argc, char **argv)
//printf("crc32: [0]->0x%08x\n",crc24c(test_input, 32));
// generate signal
unsigned char output[rel15->rbSize * NR_SYMBOLS_PER_SLOT * NR_NB_SC_PER_RB * 8 * NR_MAX_NB_LAYERS] __attribute__((aligned(32)));
bzero(output,rel15->rbSize * NR_SYMBOLS_PER_SLOT * NR_NB_SC_PER_RB * 8 * NR_MAX_NB_LAYERS);
unsigned char output[rel15->rbSize * NR_SYMBOLS_PER_SLOT * NR_NB_SC_PER_RB * 8 * NR_MAX_NB_LAYERS] __attribute__((aligned(32)));
bzero(output,rel15->rbSize * NR_SYMBOLS_PER_SLOT * NR_NB_SC_PER_RB * 8 * NR_MAX_NB_LAYERS);
if (input_fd == NULL) {
nr_dlsch_encoding(gNB, frame, slot, &dlsch->harq_process, frame_parms,output,NULL,NULL,NULL,NULL,NULL,NULL,NULL);
}
@@ -551,7 +550,7 @@ int main(int argc, char **argv)
ret = nr_dlsch_decoding(UE, &proc, 0, channel_output_fixed, &UE->frame_parms,
dlsch0_ue, dlsch0_ue->harq_processes[0], frame, nb_symb_sch,
slot,harq_pid, is_crnti, llr8_flag);
slot,harq_pid, is_crnti);
vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_DECODING0, VCD_FUNCTION_OUT);
openair1/SIMULATION/NR_PHY/dlsim.c
+20 -14
View File
@@ -96,7 +96,6 @@ uint16_t sl_ahead=0;
uint64_t downlink_frequency[MAX_NUM_CCs][4];
THREAD_STRUCT thread_struct;
nfapi_ue_release_request_body_t release_rntis;
uint32_t N_RB_DL = 106;
//Fixme: Uniq dirty DU instance, by global var, datamodel need better management
instance_t DUuniqInstance=0;
instance_t CUuniqInstance=0;
@@ -270,9 +269,9 @@ int g_mcsIndex = -1, g_mcsTableIdx = 0, g_rbStart = -1, g_rbSize = -1, g_nrOfLay
void nr_dlsim_preprocessor(module_id_t module_id,
frame_t frame,
sub_frame_t slot) {
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
AssertFatal(UE_info->num_UEs == 1, "can have only a single UE\n");
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[0];
NR_UE_info_t *UE_info = RC.nrmac[module_id]->UE_info.list[0];
AssertFatal(RC.nrmac[module_id]->UE_info.list[1]==NULL, "can have only a single UE\n");
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl;
NR_ServingCellConfigCommon_t *scc = RC.nrmac[0]->common_channels[0].ServingCellConfigCommon;
/* manually set free CCE to 0 */
@@ -282,14 +281,14 @@ void nr_dlsim_preprocessor(module_id_t module_id,
find_aggregation_candidates(&sched_ctrl->aggregation_level,
&nr_of_candidates,
sched_ctrl->search_space,4);
sched_ctrl->coreset = get_coreset(module_id, scc, sched_ctrl->active_bwp->bwp_Dedicated, sched_ctrl->search_space, target_ss);
sched_ctrl->coreset = get_coreset(RC.nrmac[module_id], scc, sched_ctrl->active_bwp->bwp_Dedicated, sched_ctrl->search_space, target_ss);
sched_ctrl->cce_index = 0;
NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
nr_set_pdsch_semi_static(NULL,
scc,
UE_info->CellGroup[0],
UE_info->CellGroup,
sched_ctrl->active_bwp,
NULL,
/* tda = */ 0,
@@ -658,7 +657,7 @@ int main(int argc, char **argv)
default:
case 'h':
printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId\n",
printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId\n",
argv[0]);
printf("-h This message\n");
printf("-L <log level, 0(errors), 1(warning), 2(analysis), 3(info), 4(debug), 5(trace)>\n");
@@ -667,7 +666,7 @@ int main(int argc, char **argv)
printf("-n Number of frames to simulate\n");
printf("-s Starting SNR, runs from SNR0 to SNR0 + 5 dB. If n_frames is 1 then just SNR is simulated\n");
printf("-S Ending SNR, runs from SNR0 to SNR1\n");
printf("-t Delay spread for multipath channel\n");
//printf("-t Delay spread for multipath channel\n");
printf("-g [A,B,C,D,E,F,G,R] Use 3GPP SCM (A,B,C,D) or 36-101 (E-EPA,F-EVA,G-ETU) models or R for MIMO model (ignores delay spread and Ricean factor)\n");
printf("-y Number of TX antennas used in gNB\n");
printf("-z Number of RX antennas used in UE\n");
@@ -837,8 +836,7 @@ int main(int argc, char **argv)
gNB_mac->pre_processor_dl = nr_dlsim_preprocessor;
phy_init_nr_gNB(gNB,0,1);
N_RB_DL = gNB->frame_parms.N_RB_DL;
NR_UE_info_t *UE_info = &RC.nrmac[0]->UE_info;
UE_info->num_UEs=1;
NR_UE_info_t *UE_info = RC.nrmac[0]->UE_info.list[0];
// stub to configure frame_parms
// nr_phy_config_request_sim(gNB,N_RB_DL,N_RB_DL,mu,Nid_cell,SSB_positions);
@@ -853,10 +851,14 @@ int main(int argc, char **argv)
double fs,bw;
if (mu == 1 && N_RB_DL == 217) {
if (mu == 0 && N_RB_DL == 25) {
fs = 7.68e6;
bw = 5e6;
}
else if (mu == 1 && N_RB_DL == 217) {
fs = 122.88e6;
bw = 80e6;
}
}
else if (mu == 1 && N_RB_DL == 245) {
fs = 122.88e6;
bw = 90e6;
@@ -877,6 +879,10 @@ int main(int argc, char **argv)
fs = 61.44e6;
bw = 60e6;
}
else if (mu == 1 && N_RB_DL == 24) {
fs = 15.36e6;
bw = 10e6;
}
else if (mu == 3 && N_RB_DL == 66) {
fs = 122.88e6;
bw = 100e6;
@@ -1098,10 +1104,10 @@ int main(int argc, char **argv)
clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot);
UE_info->UE_sched_ctrl[0].harq_processes[harq_pid].ndi = !(trial&1);
UE_info->UE_sched_ctrl.harq_processes[harq_pid].ndi = !(trial&1);
UE_info->UE_sched_ctrl[0].harq_processes[harq_pid].round = round;
UE_info->UE_sched_ctrl.harq_processes[harq_pid].round = round;
for (int i=0; i<MAX_NUM_CORESET; i++)
gNB_mac->pdcch_cand[i] = 0;
openair1/SIMULATION/NR_PHY/prachsim.c
+12 -13
View File
@@ -240,7 +240,7 @@ int main(int argc, char **argv){
int i, l, aa, aarx, **txdata, trial, n_frames = 1, prach_start, rx_prach_start; //, ntrials=1;
int N_RB_UL = 106, delay = 0, NCS_config = 13, rootSequenceIndex = 1, threequarter_fs = 0, mu = 1, fd_occasion = 0, loglvl = OAILOG_INFO, numRA = 0, prachStartSymbol = 0;
uint8_t snr1set = 0, ue_speed1set = 0, transmission_mode = 1, n_tx = 1, n_rx = 1, awgn_flag = 0, msg1_frequencystart = 0, num_prach_fd_occasions = 1, prach_format=0;
uint8_t frame = 1, slot=19, slot_gNB=19, config_index = 98, prach_sequence_length = 1, restrictedSetConfig = 0, N_dur, N_t_slot, start_symbol;
uint8_t config_index = 98, prach_sequence_length = 1, restrictedSetConfig = 0, N_dur, N_t_slot, start_symbol;
uint16_t Nid_cell = 0, preamble_tx = 0, preamble_delay, format, format0, format1;
uint32_t tx_lev = 10000, prach_errors = 0; //,tx_lev_dB;
uint64_t SSB_positions = 0x01;
@@ -536,7 +536,7 @@ int main(int argc, char **argv){
frame_parms->N_RB_UL = N_RB_UL;
frame_parms->threequarter_fs = threequarter_fs;
frame_parms->frame_type = TDD;
frame_parms->freq_range = (mu==1 ? nr_FR1 : nr_FR2);
frame_parms->freq_range = (mu != 3 ? nr_FR1 : nr_FR2);
frame_parms->numerology_index = mu;
nr_phy_config_request_sim(gNB, N_RB_UL, N_RB_UL, mu, Nid_cell, SSB_positions);
@@ -546,9 +546,11 @@ int main(int argc, char **argv){
frame_parms->numerology_index,
frame_parms->N_RB_UL*(180e3)*(1 << frame_parms->numerology_index));
uint8_t subframe = slot/frame_parms->slots_per_subframe;
uint8_t frame = 1;
uint8_t subframe = 9;
uint8_t slot = 10 * frame_parms->slots_per_subframe - 1;
if (config_index<67 && mu==1) { prach_sequence_length=0; slot = subframe*2; slot_gNB = 1+(subframe*2); }
if (config_index<67 && mu != 3) { prach_sequence_length=0; slot = subframe * frame_parms->slots_per_subframe; }
uint16_t N_ZC = prach_sequence_length == 0 ? 839 : 139;
printf("Config_index %d, prach_sequence_length %d\n",config_index,prach_sequence_length);
@@ -569,9 +571,11 @@ int main(int argc, char **argv){
ru->gNB_list[0] = gNB;
gNB->gNB_config.carrier_config.num_tx_ant.value = 1;
gNB->gNB_config.carrier_config.num_rx_ant.value = 1;
if (mu==1)
if (mu == 0)
gNB->gNB_config.tdd_table.tdd_period.value = 7;
else if (mu == 1)
gNB->gNB_config.tdd_table.tdd_period.value = 6;
else if (mu==3)
else if (mu == 3)
gNB->gNB_config.tdd_table.tdd_period.value = 3;
else {
printf("unsupported numerology %d\n",mu);
@@ -585,7 +589,7 @@ int main(int argc, char **argv){
int ret = get_nr_prach_info_from_index(config_index,
(int)frame,
(int)slot_gNB,
(int)slot,
absoluteFrequencyPointA,
mu,
frame_parms->frame_type,
@@ -717,12 +721,7 @@ int main(int argc, char **argv){
bw = N_RB_UL*(180e3)*(1 << frame_parms->numerology_index);
AssertFatal(bw<=122.88e6,"Illegal channel bandwidth %f (mu %d,N_RB_UL %d)\n", bw, frame_parms->numerology_index, N_RB_UL);
if (bw <= 30.72e6)
fs = 30.72e6;
else if (bw <= 61.44e6)
fs = 61.44e6;
else if (bw <= 122.88e6)
fs = 122.88e6;
fs = frame_parms->samples_per_subframe * 1e3;
LOG_I(PHY,"Running with bandwidth %f Hz, fs %f samp/s, FRAME_LENGTH_COMPLEX_SAMPLES %d\n",bw,fs,FRAME_LENGTH_COMPLEX_SAMPLES);
openair1/SIMULATION/NR_PHY/ulschsim.c
+5 -2
View File
@@ -47,6 +47,7 @@
#include "openair1/SIMULATION/NR_PHY/nr_unitary_defs.h"
#include "openair1/SIMULATION/NR_PHY/nr_dummy_functions.c"
#include "common/utils/threadPool/thread-pool.h"
#include "openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h"
//#define DEBUG_NR_ULSCHSIM
@@ -461,7 +462,7 @@ int main(int argc, char **argv)
rel15_ul->pusch_data.rv_index = rvidx;
rel15_ul->nrOfLayers = Nl;
rel15_ul->target_code_rate = code_rate;
rel15_ul->pusch_data.tb_size = TBS/8;
rel15_ul->pusch_data.tb_size = TBS>>3;
///////////////////////////////////////////////////
double modulated_input[16 * 68 * 384]; // [hna] 16 segments, 68*Zc
@@ -488,7 +489,9 @@ int main(int argc, char **argv)
harq_process_ul_ue->pusch_pdu.nr_of_symbols = nb_symb_sch;
harq_process_ul_ue->num_of_mod_symbols = N_RE_prime*nb_rb*nb_codewords;
harq_process_ul_ue->pusch_pdu.pusch_data.rv_index = rvidx;
harq_process_ul_ue->pusch_pdu.pusch_data.tb_size = TBS/8;
harq_process_ul_ue->pusch_pdu.pusch_data.tb_size = TBS>>3;
harq_process_ul_ue->pusch_pdu.target_code_rate = code_rate;
harq_process_ul_ue->pusch_pdu.qam_mod_order = mod_order;
unsigned char *test_input = harq_process_ul_ue->a;
///////////
openair1/SIMULATION/NR_PHY/ulsim.c
+45 -21
View File
@@ -91,7 +91,6 @@ double cpuf;
uint64_t downlink_frequency[MAX_NUM_CCs][4];
THREAD_STRUCT thread_struct;
nfapi_ue_release_request_body_t release_rntis;
uint32_t N_RB_DL = 106;
//Fixme: Uniq dirty DU instance, by global var, datamodel need better management
instance_t DUuniqInstance=0;
@@ -306,7 +305,6 @@ int main(int argc, char **argv)
int32_t txlev_sum = 0, atxlev[4];
int start_rb = 0;
int UE_id =0; // [hna] only works for UE_id = 0 because NUMBER_OF_NR_UE_MAX is set to 1 (phy_init_nr_gNB causes segmentation fault)
float target_error_rate = 0.01;
int print_perf = 0;
cpuf = get_cpu_freq_GHz();
int msg3_flag = 0;
@@ -314,7 +312,7 @@ int main(int argc, char **argv)
float roundStats[100];
double effRate[100];
double effTP[100];
//float eff_tp_check = 0.7;
float eff_tp_check = 0.7;
uint8_t snrRun;
int prb_inter = 0;
@@ -322,8 +320,8 @@ int main(int argc, char **argv)
int modify_dmrs = 0;
/* L_PTRS = ptrs_arg[0], K_PTRS = ptrs_arg[1] */
int ptrs_arg[2] = {-1,-1};// Invalid values
/* DMRS TYPE = dmrs_arg[0], Add Pos = dmrs_arg[1] */
int dmrs_arg[2] = {-1,-1};// Invalid values
/* mapping type = dmrs_arg[0], Add Pos = dmrs_arg[1], dmrs config type = dmrs_arg[2] */
int dmrs_arg[3] = {-1,-1,-1};// Invalid values
uint16_t ptrsSymPos = 0;
uint16_t ptrsSymbPerSlot = 0;
uint16_t ptrsRePerSymb = 0;
@@ -350,7 +348,7 @@ int main(int argc, char **argv)
/* initialize the sin-cos table */
InitSinLUT();
while ((c = getopt(argc, argv, "a:b:c:d:ef:g:h:i:kl:m:n:p:r:s:u:w:y:z:F:G:H:M:N:PR:S:T:U:L:Z:W:")) != -1) {
while ((c = getopt(argc, argv, "a:b:c:d:ef:g:h:ikl:m:n:p:r:s:t:u:w:y:z:F:G:H:M:N:PR:S:T:U:L:Z:W:")) != -1) {
printf("handling optarg %c\n",c);
switch (c) {
@@ -488,11 +486,10 @@ int main(int argc, char **argv)
start_rb = atoi(optarg);
break;
/*
case 't':
eff_tp_check = (float)atoi(optarg)/100;
break;
*/
/*
case 'r':
ricean_factor = pow(10,-.1*atof(optarg));
@@ -594,7 +591,7 @@ int main(int argc, char **argv)
default:
case 'h':
printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId -Z Enable SC-FDMA in Uplink \n", argv[0]);
printf("%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId -Z Enable SC-FDMA in Uplink \n", argv[0]);
//printf("-d Use TDD\n");
printf("-d Introduce delay in terms of number of samples\n");
printf("-f Number of frames to simulate\n");
@@ -606,7 +603,7 @@ int main(int argc, char **argv)
printf("-m MCS value\n");
printf("-n Number of trials to simulate\n");
printf("-p Use extended prefix mode\n");
printf("-t Delay spread for multipath channel\n");
//printf("-t Delay spread for multipath channel\n");
printf("-u Set the numerology\n");
printf("-w Start PRB for PUSCH\n");
//printf("-x Transmission mode (1,2,6 for the moment)\n");
@@ -649,16 +646,37 @@ int main(int argc, char **argv)
double sampling_frequency;
double bandwidth;
if (N_RB_UL >= 217) sampling_frequency = 122.88;
else if (N_RB_UL >= 106) sampling_frequency = 61.44;
else if (N_RB_UL >= 32) sampling_frequency = 32.72;
else { printf("Need at least 106 PRBs\b"); exit(-1); }
if (N_RB_UL == 273) bandwidth = 100;
else if (N_RB_UL == 217) bandwidth = 80;
else if (N_RB_UL == 106) bandwidth = 40;
else if (N_RB_UL == 32) bandwidth = 50;
else { printf("Add N_RB_UL %d\n",N_RB_UL); exit(-1); }
if (mu == 0 && N_RB_UL == 25 ) {
sampling_frequency = 7.68;
bandwidth = 5;
}
else if (mu == 1 && N_RB_UL == 273) {
sampling_frequency = 122.88;
bandwidth = 100;
}
else if (mu == 1 && N_RB_UL == 217) {
sampling_frequency = 122.88;
bandwidth = 80;
}
else if (mu == 1 && N_RB_UL == 106) {
sampling_frequency = 61.44;
bandwidth = 40;
}
else if (mu == 1 && N_RB_UL == 24) {
sampling_frequency = 15.36;
bandwidth = 10;
}
else if (mu == 3 && N_RB_UL == 32) {
sampling_frequency = 61.44;
bandwidth = 50;
}
else {
printf("Add N_RB_UL %d\n",N_RB_UL);
exit(-1);
}
LOG_I( PHY,"++++++++++++++++++++++++++++++++++++++++++++++%i+++++++++++++++++++++++++++++++++++++++++",loglvl);
if (openair0_cfg[0].threequarter_fs == 1) sampling_frequency*=.75;
UE2gNB = new_channel_desc_scm(n_tx, n_rx, channel_model,
@@ -872,8 +890,12 @@ int main(int argc, char **argv)
/* Additional DMRS positions */
if(dmrs_arg[1] >= 0 && dmrs_arg[1] <=3 )
add_pos = dmrs_arg[1];
/* DMRS Conf Type 1 or 2 */
if(dmrs_arg[2] == 1)
dmrs_config_type = pusch_dmrs_type1;
else if(dmrs_arg[2] == 2)
dmrs_config_type = pusch_dmrs_type2;
}
printf("NOTE: DMRS config is modified with Mapping Type %d , Additional Position %d \n", mapping_type, add_pos );
uint8_t length_dmrs = pusch_len1;
uint16_t l_prime_mask = get_l_prime(nb_symb_sch, mapping_type, add_pos, length_dmrs, start_symbol, NR_MIB__dmrs_TypeA_Position_pos2);
@@ -892,6 +914,7 @@ int main(int argc, char **argv)
AssertFatal(index >= 0, "Num RBs not configured according to 3GPP 38.211 section 6.3.1.4. For PUSCH with transform precoding, num RBs cannot be multiple of any other primenumber other than 2,3,5\n");
dmrs_config_type = pusch_dmrs_type1;
nb_re_dmrs = 6;
printf("[ULSIM]: TRANSFORM PRECODING ENABLED. Num RBs: %d, index for DMRS_SEQ: %d\n", nb_rb, index);
}
@@ -1165,6 +1188,7 @@ int main(int argc, char **argv)
ul_config.ul_config_list[0].pusch_config_pdu.nrOfLayers = precod_nbr_layers;
ul_config.ul_config_list[0].pusch_config_pdu.dmrs_ports = ((1<<precod_nbr_layers)-1);
ul_config.ul_config_list[0].pusch_config_pdu.absolute_delta_PUSCH = 0;
ul_config.ul_config_list[0].pusch_config_pdu.target_code_rate = code_rate;
ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.tb_size = TBS/8;
ul_config.ul_config_list[0].pusch_config_pdu.pusch_data.new_data_indicator = trial & 0x1;
@@ -1559,7 +1583,7 @@ int main(int argc, char **argv)
if(n_trials==1)
break;
if ((float)n_errors[0][snrRun]/(float)n_trials <= target_error_rate) {
if (effRate[snrRun] > (eff_tp_check*TBS)) {
printf("*************\n");
printf("PUSCH test OK\n");
printf("*************\n");
openair2/F1AP/f1ap_du_ue_context_management.c
+4 -5
View File
@@ -683,15 +683,15 @@ int DU_handle_UE_CONTEXT_RELEASE_COMMAND(instance_t instance,
"RNTI obtained through DU ID (%x) is different from CU ID (%x)\n",
rnti, ctxt.rnti);
int UE_out_of_sync = 0;
if (RC.nrrrc && RC.nrrrc[instance]->node_type == ngran_gNB_DU) {
for (int n = 0; n < MAX_MOBILES_PER_GNB; ++n) {
if (RC.nrmac[instance]->UE_info.active[n] == TRUE
&& rnti == RC.nrmac[instance]->UE_info.rnti[n]) {
UE_iterator(RC.nrmac[instance]->UE_info.list, UE) {
if (UE->rnti == rnti) {
UE_out_of_sync = 0;
break;
}
}
if (!UE)
LOG_E(F1AP,"Not found rnti: %x\n", rnti);
} else {
for (int n = 0; n < MAX_MOBILES_PER_ENB; ++n) {
if (RC.mac[instance]->UE_info.active[n] == TRUE
@@ -701,7 +701,6 @@ int DU_handle_UE_CONTEXT_RELEASE_COMMAND(instance_t instance,
}
}
}
/* We don't need the Cause */
/* Optional RRC Container: if present, send to UE */
F1AP_FIND_PROTOCOLIE_BY_ID(F1AP_UEContextReleaseCommandIEs_t, ie, container,
openair2/GNB_APP/MACRLC_nr_paramdef.h
+15 -7
View File
@@ -62,12 +62,15 @@
#define CONFIG_STRING_MACRLC_PUSCHFAILURETHRES "pusch_FailureThres"
#define CONFIG_STRING_MACRLC_DL_BLER_TARGET_UPPER "dl_bler_target_upper"
#define CONFIG_STRING_MACRLC_DL_BLER_TARGET_LOWER "dl_bler_target_lower"
#define CONFIG_STRING_MACRLC_DL_RD2_BLER_THRESHOLD "dl_rd2_bler_threshold"
#define CONFIG_STRING_MACRLC_DL_MAX_MCS "dl_max_mcs"
#define CONFIG_STRING_MACRLC_UL_BLER_TARGET_UPPER "ul_bler_target_upper"
#define CONFIG_STRING_MACRLC_UL_BLER_TARGET_LOWER "ul_bler_target_lower"
#define CONFIG_STRING_MACRLC_UL_MAX_MCS "ul_max_mcs"
#define CONFIG_STRING_MACRLC_HARQ_ROUND_MAX "harq_round_max"
#define CONFIG_STRING_MACRLC_MIN_GRANT_PRB "min_grant_prb"
#define CONFIG_STRING_MACRLC_MIN_GRANT_MCS "min_grant_mcs"
/*-------------------------------------------------------------------------------------------------------------------------------------------------------*/
/* MacRLC configuration parameters */
/* optname helpstr paramflags XXXptr defXXXval type numelt */
@@ -97,8 +100,10 @@
{CONFIG_STRING_MACRLC_PUSCHFAILURETHRES, NULL, 0, iptr:NULL, defintval:10, TYPE_INT, 0}, \
{CONFIG_STRING_MACRLC_DL_BLER_TARGET_UPPER, "Upper threshold of BLER to decrease DL MCS", 0, dblptr:NULL, defdblval:0.15, TYPE_DOUBLE, 0}, \
{CONFIG_STRING_MACRLC_DL_BLER_TARGET_LOWER, "Lower threshold of BLER to increase DL MCS", 0, dblptr:NULL, defdblval:0.05, TYPE_DOUBLE, 0}, \
{CONFIG_STRING_MACRLC_DL_RD2_BLER_THRESHOLD, "Threshold of RD2/RETX2 BLER to decrease DL MCS", 0, dblptr:NULL, defdblval:0.01, TYPE_DOUBLE, 0}, \
{CONFIG_STRING_MACRLC_DL_MAX_MCS, "Maximum DL MCS that should be used", 0, u8ptr:NULL, defintval:28, TYPE_UINT8, 0}, \
{CONFIG_STRING_MACRLC_UL_BLER_TARGET_UPPER, "Upper threshold of BLER to decrease UL MCS", 0, dblptr:NULL, defdblval:0.15, TYPE_DOUBLE, 0}, \
{CONFIG_STRING_MACRLC_UL_BLER_TARGET_LOWER, "Lower threshold of BLER to increase UL MCS", 0, dblptr:NULL, defdblval:0.05, TYPE_DOUBLE, 0}, \
{CONFIG_STRING_MACRLC_UL_MAX_MCS, "Maximum UL MCS that should be used", 0, u8ptr:NULL, defintval:9, TYPE_UINT8, 0}, \
{CONFIG_STRING_MACRLC_HARQ_ROUND_MAX, "Maximum number of HARQ rounds", 0, u8ptr:NULL, defintval:4, TYPE_UINT8, 0}, \
{CONFIG_STRING_MACRLC_MIN_GRANT_PRB, "Minimal Periodic ULSCH Grant PRBs", 0, u8ptr:NULL, defintval:5, TYPE_UINT8, 0}, \
{CONFIG_STRING_MACRLC_MIN_GRANT_MCS, "Minimal Periodic ULSCH Grant MCS", 0, u8ptr:NULL, defintval:9, TYPE_UINT8, 0} \
@@ -127,10 +132,13 @@
#define MACRLC_PUSCHFAILURETHRES_IDX 21
#define MACRLC_DL_BLER_TARGET_UPPER_IDX 22
#define MACRLC_DL_BLER_TARGET_LOWER_IDX 23
#define MACRLC_DL_RD2_BLER_THRESHOLD_IDX 24
#define MACRLC_DL_MAX_MCS_IDX 25
#define MACRLC_HARQ_ROUND_MAX_IDX 26
#define MACRLC_MIN_GRANT_PRB_IDX 27
#define MACRLC_MIN_GRANT_MCS_IDX 28
#define MACRLC_DL_MAX_MCS_IDX 24
#define MACRLC_UL_BLER_TARGET_UPPER_IDX 25
#define MACRLC_UL_BLER_TARGET_LOWER_IDX 26
#define MACRLC_UL_MAX_MCS_IDX 27
#define MACRLC_HARQ_ROUND_MAX_IDX 28
#define MACRLC_MIN_GRANT_PRB_IDX 29
#define MACRLC_MIN_GRANT_MCS_IDX 30
/*---------------------------------------------------------------------------------------------------------------------------------------------------------*/
#endif
openair2/GNB_APP/gnb_config.c
+28 -16
View File
@@ -213,15 +213,20 @@ void fill_scc_sim(NR_ServingCellConfigCommon_t *scc,uint64_t *ssb_bitmap,int N_R
// *scc->n_TimingAdvanceOffset=NR_ServingCellConfigCommon__n_TimingAdvanceOffset_n0;
*scc->ssb_periodicityServingCell=NR_ServingCellConfigCommon__ssb_periodicityServingCell_ms20;
scc->dmrs_TypeA_Position=NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos2;
*scc->ssbSubcarrierSpacing=NR_SubcarrierSpacing_kHz30;
*scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB=641032;
*scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0]=78;
scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA=640000;
*scc->ssbSubcarrierSpacing=mu_dl;
if (mu_dl == 0) {
*scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB=520432;
*scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0]=38;
scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA=520000;
} else {
*scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencySSB=641032;
*scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0]=78;
scc->downlinkConfigCommon->frequencyInfoDL->absoluteFrequencyPointA=640000;
}
scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->offsetToCarrier=0;
scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing=NR_SubcarrierSpacing_kHz30;
scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing=mu_dl;
scc->downlinkConfigCommon->frequencyInfoDL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth=N_RB_DL;
scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth=13036;
scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth=275*(N_RB_DL-1);
scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.subcarrierSpacing=mu_dl;//NR_SubcarrierSpacing_kHz30;
*scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->controlResourceSetZero=12;
*scc->downlinkConfigCommon->initialDownlinkBWP->pdcch_ConfigCommon->choice.setup->searchSpaceZero=0;
@@ -235,13 +240,13 @@ void fill_scc_sim(NR_ServingCellConfigCommon_t *scc,uint64_t *ssb_bitmap,int N_R
timedomainresourceallocation1->startSymbolAndLength=57;
ASN_SEQUENCE_ADD(&scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list,
timedomainresourceallocation1);
*scc->uplinkConfigCommon->frequencyInfoUL->frequencyBandList->list.array[0]=78;
*scc->uplinkConfigCommon->frequencyInfoUL->frequencyBandList->list.array[0]=mu_ul?78:38;
*scc->uplinkConfigCommon->frequencyInfoUL->absoluteFrequencyPointA=-1;
scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->offsetToCarrier=0;
scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing=NR_SubcarrierSpacing_kHz30;
scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->subcarrierSpacing=mu_ul;
scc->uplinkConfigCommon->frequencyInfoUL->scs_SpecificCarrierList.list.array[0]->carrierBandwidth=N_RB_UL;
*scc->uplinkConfigCommon->frequencyInfoUL->p_Max=20;
scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth=13036;
scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth=275*(N_RB_UL-1);
scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.subcarrierSpacing=mu_ul;//NR_SubcarrierSpacing_kHz30;
scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.prach_ConfigurationIndex=98;
scc->uplinkConfigCommon->initialUplinkBWP->rach_ConfigCommon->choice.setup->rach_ConfigGeneric.msg1_FDM=NR_RACH_ConfigGeneric__msg1_FDM_one;
@@ -277,8 +282,11 @@ void fill_scc_sim(NR_ServingCellConfigCommon_t *scc,uint64_t *ssb_bitmap,int N_R
*scc->uplinkConfigCommon->initialUplinkBWP->pucch_ConfigCommon->choice.setup->p0_nominal=-90;
scc->ssb_PositionsInBurst->present=NR_ServingCellConfigCommon__ssb_PositionsInBurst_PR_mediumBitmap;
*ssb_bitmap=0xff;
scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing=NR_SubcarrierSpacing_kHz30;
scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity=NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms5;
scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing=mu_dl;
if (mu_dl == 0)
scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity=NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms10;
else
scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity=NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms5;
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots=7;
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols=6;
scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSlots=2;
@@ -873,10 +881,14 @@ void RCconfig_nr_macrlc() {
AssertFatal(1==0,"MACRLC %d: %s unknown southbound midhaul\n",j,*(MacRLC_ParamList.paramarray[j][MACRLC_TRANSPORT_S_PREFERENCE_IDX].strptr));
}
RC.nrmac[j]->ulsch_max_frame_inactivity = *(MacRLC_ParamList.paramarray[j][MACRLC_ULSCH_MAX_FRAME_INACTIVITY].uptr);
RC.nrmac[j]->dl_bler_target_upper = *(MacRLC_ParamList.paramarray[j][MACRLC_DL_BLER_TARGET_UPPER_IDX].dblptr);
RC.nrmac[j]->dl_bler_target_lower = *(MacRLC_ParamList.paramarray[j][MACRLC_DL_BLER_TARGET_LOWER_IDX].dblptr);
RC.nrmac[j]->dl_rd2_bler_threshold = *(MacRLC_ParamList.paramarray[j][MACRLC_DL_RD2_BLER_THRESHOLD_IDX].dblptr);
RC.nrmac[j]->dl_max_mcs = *(MacRLC_ParamList.paramarray[j][MACRLC_DL_MAX_MCS_IDX].u8ptr);
NR_bler_options_t *dl_bler_options = &RC.nrmac[j]->dl_bler;
dl_bler_options->upper = *(MacRLC_ParamList.paramarray[j][MACRLC_DL_BLER_TARGET_UPPER_IDX].dblptr);
dl_bler_options->lower = *(MacRLC_ParamList.paramarray[j][MACRLC_DL_BLER_TARGET_LOWER_IDX].dblptr);
dl_bler_options->max_mcs = *(MacRLC_ParamList.paramarray[j][MACRLC_DL_MAX_MCS_IDX].u8ptr);
NR_bler_options_t *ul_bler_options = &RC.nrmac[j]->ul_bler;
ul_bler_options->upper = *(MacRLC_ParamList.paramarray[j][MACRLC_UL_BLER_TARGET_UPPER_IDX].dblptr);
ul_bler_options->lower = *(MacRLC_ParamList.paramarray[j][MACRLC_UL_BLER_TARGET_LOWER_IDX].dblptr);
ul_bler_options->max_mcs = *(MacRLC_ParamList.paramarray[j][MACRLC_UL_MAX_MCS_IDX].u8ptr);
RC.nrmac[j]->harq_round_max = *(MacRLC_ParamList.paramarray[j][MACRLC_HARQ_ROUND_MAX_IDX].u8ptr);
RC.nrmac[j]->min_grant_prb = *(MacRLC_ParamList.paramarray[j][MACRLC_MIN_GRANT_PRB_IDX].u8ptr);
RC.nrmac[j]->min_grant_mcs = *(MacRLC_ParamList.paramarray[j][MACRLC_MIN_GRANT_MCS_IDX].u8ptr);
openair2/LAYER2/NR_MAC_COMMON/nr_compute_tbs_common.c
+4 -5
View File
@@ -49,16 +49,15 @@ uint32_t nr_compute_tbs(uint16_t Qm,
uint16_t nbp_re, nb_re;
uint32_t nr_tbs=0;
uint32_t Ninfo, Np_info, C;
uint8_t n, scale;
uint8_t n;
LOG_D(NR_MAC, "In %s: nb_symb_sch %d, nb_dmrs_prb %d, nb_rb %d, nb_rb_oh %d, tb_scaling %d Nl %d\n", __FUNCTION__, nb_symb_sch, nb_dmrs_prb, nb_rb, nb_rb_oh, tb_scaling, Nl);
nbp_re = NR_NB_SC_PER_RB * nb_symb_sch - nb_dmrs_prb - nb_rb_oh;
nb_re = min(156, nbp_re) * nb_rb;
scale = (R>1024)?11:10;
// Intermediate number of information bits
Ninfo = ((nb_re * R * Qm * Nl)>>scale)>>tb_scaling;
// R is tabulated as 10 times the actual code rate
Ninfo = ((nb_re * R * Qm * Nl / 10)>>10)>>tb_scaling;
if (Ninfo <=3824) {
n = max(3, floor(log2(Ninfo)) - 6);
@@ -73,7 +72,7 @@ uint32_t nr_compute_tbs(uint16_t Qm,
n = log2(Ninfo-24)-5;
Np_info = max(3840, (ROUNDIDIV((Ninfo-24),(1<<n)))<<n);
if (R <= 256) {
if (R <= 2560) {
C = CEILIDIV((Np_info+24),3816);
nr_tbs = (C<<3)*CEILIDIV((Np_info+24),(C<<3)) - 24;
} else {
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
+15 -17
View File
@@ -1686,7 +1686,7 @@ int get_nr_prach_info_from_index(uint8_t index,
}
if ( (s_map>>subframe)&0x01 ) {
*N_RA_slot = table_6_3_3_2_3_prachConfig_Index[index][6]; // Number of RACH slots within a subframe
if (mu == 1) {
if (mu == 1 && index >= 67) {
if ( (*N_RA_slot <= 1) && (slot%2 == 0) )
return 0; // no prach in even slots @ 30kHz for 1 prach per subframe
}
@@ -2095,17 +2095,15 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu,
uint16_t N_RE_prime = NR_NB_SC_PER_RB*N_sh_symb - N_PRB_DMRS*dmrs_length - N_PRB_oh;
LOG_D(MAC, "N_RE_prime %d for %d symbols %d DMRS per PRB and %d overhead\n", N_RE_prime, N_sh_symb, N_PRB_DMRS, N_PRB_oh);
uint16_t R;
uint32_t TBS=0;
uint8_t table_idx, Qm;
/*uint8_t mcs_table = config.pdsch_config.mcs_table.value;
uint8_t ss_type = params_rel15.search_space_type;
uint8_t dci_format = params_rel15.dci_format;
get_table_idx(mcs_table, dci_format, rnti_type, ss_type);*/
table_idx = 0;
R = nr_get_code_rate_dl(Imcs, table_idx);
Qm = nr_get_Qm_dl(Imcs, table_idx);
uint8_t table_idx = 0;
uint16_t R = nr_get_code_rate_dl(Imcs, table_idx);
uint8_t Qm = nr_get_Qm_dl(Imcs, table_idx);
TBS = nr_compute_tbs(Qm,
R,
@@ -2126,25 +2124,25 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu,
TBS, N_PRB_DMRS, N_sh_symb, N_PRB_oh, R, Qm, table_idx,N_RE_prime*pdsch_rel15->rbSize*pdsch_rel15->NrOfCodewords );
}
// the following tables contain 10 times the value reported in 214 (in line with SCF specification and to avoid fractional values)
//Table 5.1.3.1-1 of 38.214
uint16_t Table_51311[29][2] = {{2,120},{2,157},{2,193},{2,251},{2,308},{2,379},{2,449},{2,526},{2,602},{2,679},{4,340},{4,378},{4,434},{4,490},{4,553},{4,616},
{4,658},{6,438},{6,466},{6,517},{6,567},{6,616},{6,666},{6,719},{6,772},{6,822},{6,873}, {6,910}, {6,948}};
uint16_t Table_51311[29][2] = {{2,1200},{2,1570},{2,1930},{2,2510},{2,3080},{2,3790},{2,4490},{2,5260},{2,6020},{2,6790},{4,3400},{4,3780},{4,4340},{4,4900},{4,5530},{4,6160},
{4,6580},{6,4380},{6,4660},{6,5170},{6,5670},{6,6160},{6,6660},{6,7190},{6,7720},{6,8220},{6,8730}, {6,9100}, {6,9480}};
//Table 5.1.3.1-2 of 38.214
// Imcs values 20 and 26 have been multiplied by 2 to avoid the floating point
uint16_t Table_51312[28][2] = {{2,120},{2,193},{2,308},{2,449},{2,602},{4,378},{4,434},{4,490},{4,553},{4,616},{4,658},{6,466},{6,517},{6,567},{6,616},{6,666},
{6,719},{6,772},{6,822},{6,873},{8,1365},{8,711},{8,754},{8,797},{8,841},{8,885},{8,1833},{8,948}};
uint16_t Table_51312[28][2] = {{2,1200},{2,1930},{2,3080},{2,4490},{2,6020},{4,3780},{4,4340},{4,4900},{4,5530},{4,6160},{4,6580},{6,4660},{6,5170},{6,5670},{6,6160},{6,6660},
{6,7190},{6,7720},{6,8220},{6,8730},{8,6825},{8,7110},{8,7540},{8,7970},{8,8410},{8,8850},{8,9165},{8,9480}};
//Table 5.1.3.1-3 of 38.214
uint16_t Table_51313[29][2] = {{2,30},{2,40},{2,50},{2,64},{2,78},{2,99},{2,120},{2,157},{2,193},{2,251},{2,308},{2,379},{2,449},{2,526},{2,602},{4,340},
{4,378},{4,434},{4,490},{4,553},{4,616},{6,438},{6,466},{6,517},{6,567},{6,616},{6,666}, {6,719}, {6,772}};
uint16_t Table_51313[29][2] = {{2,300},{2,400},{2,500},{2,640},{2,780},{2,990},{2,1200},{2,1570},{2,1930},{2,2510},{2,3080},{2,3790},{2,4490},{2,5260},{2,6020},{4,3400},
{4,3780},{4,4340},{4,4900},{4,5530},{4,6160},{6,4380},{6,4660},{6,5170},{6,5670},{6,6160},{6,6660},{6,7190},{6,7720}};
uint16_t Table_61411[28][2] = {{2,120},{2,157},{2,193},{2,251},{2,308},{2,379},{2,449},{2,526},{2,602},{2,679},{4,340},{4,378},{4,434},{4,490},{4,553},{4,616},
{4,658},{6,466},{6,517},{6,567},{6,616},{6,666},{6,719},{6,772},{6,822},{6,873}, {6,910}, {6,948}};
uint16_t Table_61412[28][2] = {{2,30},{2,40},{2,50},{2,64},{2,78},{2,99},{2,120},{2,157},{2,193},{2,251},{2,308},{2,379},{2,449},{2,526},{2,602},{2,679},
{4,378},{4,434},{4,490},{4,553},{4,616},{4,658},{4,699},{4,772},{6,567},{6,616},{6,666}, {6,772}};
uint16_t Table_61411[28][2] = {{2,1200},{2,1570},{2,1930},{2,2510},{2,3080},{2,3790},{2,4490},{2,5260},{2,6020},{2,6790},{4,3400},{4,3780},{4,4340},{4,4900},{4,5530},{4,6160},
{4,6580},{6,4660},{6,5170},{6,5670},{6,6160},{6,6660},{6,7190},{6,7720},{6,8220},{6,8730},{6,9100},{6,9480}};
uint16_t Table_61412[28][2] = {{2,300},{2,400},{2,500},{2,640},{2,780},{2,990},{2,1200},{2,1570},{2,1930},{2,2510},{2,3080},{2,3790},{2,4490},{2,5260},{2,6020},{2,6790},
{4,3780},{4,4340},{4,4900},{4,5530},{4,6160},{4,6580},{4,6990},{4,7720},{6,5670},{6,6160},{6,6660},{6,7720}};
uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx) {
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.h
+17
View File
@@ -121,6 +121,23 @@ int32_t get_l_prime(uint8_t duration_in_symbols, uint8_t mapping_type, pusch_dmr
uint8_t get_L_ptrs(uint8_t mcs1, uint8_t mcs2, uint8_t mcs3, uint8_t I_mcs, uint8_t mcs_table);
uint8_t get_K_ptrs(uint16_t nrb0, uint16_t nrb1, uint16_t N_RB);
uint32_t nr_compute_tbs(uint16_t Qm,
uint16_t R,
uint16_t nb_rb,
uint16_t nb_symb_sch,
uint16_t nb_dmrs_prb,
uint16_t nb_rb_oh,
uint8_t tb_scaling,
uint8_t Nl);
/** \brief Computes Q based on I_MCS PDSCH and table_idx for downlink. Implements MCS Tables from 38.214. */
uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx);
uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx);
/** \brief Computes Q based on I_MCS PDSCH and table_idx for uplink. Implements MCS Tables from 38.214. */
uint8_t nr_get_Qm_ul(uint8_t Imcs, uint8_t table_idx);
uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx);
uint16_t get_nr_srs_offset(NR_SRS_PeriodicityAndOffset_t periodicityAndOffset);
int get_bw_tbslbrm(NR_BWP_t *genericParameters,
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
+36
View File
@@ -936,6 +936,23 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
return -1;
}
dlsch_config_pdu_1_0->qamModOrder = nr_get_Qm_dl(dlsch_config_pdu_1_0->mcs, dlsch_config_pdu_1_0->mcs_table);
int R = nr_get_code_rate_dl(dlsch_config_pdu_1_0->mcs, dlsch_config_pdu_1_0->mcs_table);
dlsch_config_pdu_1_0->targetCodeRate = R;
if (dlsch_config_pdu_1_0->targetCodeRate == 0 || dlsch_config_pdu_1_0->qamModOrder == 0) {
LOG_W(MAC, "Invalid code rate or Mod order, likely due to unexpected DL DCI.\n");
return -1;
}
int nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs
int nb_re_dmrs = ((dlsch_config_pdu_1_0->dmrsConfigType == NFAPI_NR_DMRS_TYPE1) ? 6:4)*dlsch_config_pdu_1_0->n_dmrs_cdm_groups;
dlsch_config_pdu_1_0->TBS = nr_compute_tbs(dlsch_config_pdu_1_0->qamModOrder,
R,
dlsch_config_pdu_1_0->number_rbs,
dlsch_config_pdu_1_0->number_symbols,
nb_re_dmrs*get_num_dmrs(dlsch_config_pdu_1_0->dlDmrsSymbPos),
nb_rb_oh, 0, 1);
int bw_tbslbrm;
if (mac->scc || mac->scc_SIB || mac->cg) {
NR_BWP_t genericParameters = mac->scc ? mac->scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters :
@@ -1353,6 +1370,25 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
dl_config->number_pdus = dl_config->number_pdus + 1;
/* TODO same calculation for MCS table as done in UL */
dlsch_config_pdu_1_1->mcs_table = (pdsch_Config->mcs_Table) ? (*pdsch_Config->mcs_Table + 1) : 0;
dlsch_config_pdu_1_1->qamModOrder = nr_get_Qm_dl(dlsch_config_pdu_1_1->mcs, dlsch_config_pdu_1_1->mcs_table);
int R = nr_get_code_rate_dl(dlsch_config_pdu_1_1->mcs, dlsch_config_pdu_1_1->mcs_table);
dlsch_config_pdu_1_1->targetCodeRate = R;
if (dlsch_config_pdu_1_1->targetCodeRate == 0 || dlsch_config_pdu_1_1->qamModOrder == 0) {
LOG_W(MAC, "Invalid code rate or Mod order, likely due to unexpected DL DCI.\n");
return -1;
}
uint8_t Nl = 0;
for (int i = 0; i < 12; i++) { // max 12 ports
if ((dlsch_config_pdu_1_1->dmrs_ports>>i)&0x01) Nl += 1;
}
int nb_rb_oh = 0; // it was not computed at UE side even before and set to 0 in nr_compute_tbs
int nb_re_dmrs = ((dmrs_type == NULL) ? 6:4)*dlsch_config_pdu_1_1->n_dmrs_cdm_groups;
dlsch_config_pdu_1_1->TBS = nr_compute_tbs(dlsch_config_pdu_1_1->qamModOrder,
R,
dlsch_config_pdu_1_1->number_rbs,
dlsch_config_pdu_1_1->number_symbols,
nb_re_dmrs*get_num_dmrs(dlsch_config_pdu_1_1->dlDmrsSymbPos),
nb_rb_oh, 0, Nl);
// TBS_LBRM according to section 5.4.2.1 of 38.212
long *maxMIMO_Layers = mac->cg->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->ext1->maxMIMO_Layers;
openair2/LAYER2/NR_MAC_UE/nr_ue_scheduler.c
+9 -7
View File
@@ -840,12 +840,14 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac,
mappingtype, add_pos, dmrslength,
pusch_config_pdu->start_symbol_index,
mac->scc ? mac->scc->dmrs_TypeA_Position : mac->mib->dmrs_TypeA_Position);
if ((mac->ULbwp[ul_bwp_id-1] && pusch_config_pdu->transform_precoding == NR_PUSCH_Config__transformPrecoder_disabled))
if ((mac->ULbwp[ul_bwp_id-1] && pusch_config_pdu->transform_precoding == NR_PUSCH_Config__transformPrecoder_disabled)) {
if (*dci_format != NR_UL_DCI_FORMAT_0_1) {
pusch_config_pdu->num_dmrs_cdm_grps_no_data = 1;
}
else if (*dci_format == NR_UL_DCI_FORMAT_0_0 || (mac->ULbwp[ul_bwp_id-1] && pusch_config_pdu->transform_precoding == NR_PUSCH_Config__transformPrecoder_enabled))
} else if (*dci_format == NR_UL_DCI_FORMAT_0_0 ||
(mac->ULbwp[ul_bwp_id-1] && pusch_config_pdu->transform_precoding == NR_PUSCH_Config__transformPrecoder_enabled)) {
pusch_config_pdu->num_dmrs_cdm_grps_no_data = 2;
}
// Num PRB Overhead from PUSCH-ServingCellConfig
if (mac->cg &&
@@ -891,7 +893,8 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac,
rnti_types[rnti_type]);
pusch_config_pdu->ul_dmrs_symb_pos = l_prime_mask;
pusch_config_pdu->target_code_rate = nr_get_code_rate_ul(pusch_config_pdu->mcs_index, pusch_config_pdu->mcs_table);
uint16_t R = nr_get_code_rate_ul(pusch_config_pdu->mcs_index, pusch_config_pdu->mcs_table);
pusch_config_pdu->target_code_rate = R;
pusch_config_pdu->qam_mod_order = nr_get_Qm_ul(pusch_config_pdu->mcs_index, pusch_config_pdu->mcs_table);
if (pusch_config_pdu->target_code_rate == 0 || pusch_config_pdu->qam_mod_order == 0) {
@@ -910,14 +913,13 @@ int nr_config_pusch_pdu(NR_UE_MAC_INST_t *mac,
// Compute TBS
pusch_config_pdu->pusch_data.tb_size = nr_compute_tbs(pusch_config_pdu->qam_mod_order,
pusch_config_pdu->target_code_rate,
R,
pusch_config_pdu->rb_size,
pusch_config_pdu->nr_of_symbols,
nb_dmrs_re_per_rb*number_dmrs_symbols,
N_PRB_oh,
0, // TBR to verify tb scaling
pusch_config_pdu->nrOfLayers)/8;
pusch_config_pdu->nrOfLayers)>>3;
return 0;
}
@@ -1087,7 +1089,7 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in
fill_scheduled_response(&scheduled_response, &dcireq.dl_config_req, NULL, NULL, mod_id, cc_id, rx_frame, rx_slot, dl_info->thread_id, dl_info->phy_data);
if(mac->if_module != NULL && mac->if_module->scheduled_response != NULL)
LOG_D(NR_MAC,"1# scheduled_response transmitted, %d, %d\n", rx_frame, rx_slot);
mac->if_module->scheduled_response(&scheduled_response);
mac->if_module->scheduled_response(&scheduled_response);
}
else {
// this is for Msg2/Msg4
openair2/LAYER2/NR_MAC_gNB/config.c
+28 -43
View File
@@ -455,18 +455,17 @@ int nr_mac_enable_ue_rrc_processing_timer(module_id_t Mod_idP, rnti_t rnti, NR_S
if (rrc_reconfiguration_delay == 0) {
return -1;
}
const int UE_id = find_nr_UE_id(Mod_idP,rnti);
if (UE_id < 0) {
NR_UE_info_t *UE_info = find_nr_UE(&RC.nrmac[Mod_idP]->UE_info,rnti);
if (!UE_info) {
LOG_W(NR_MAC, "Could not find UE for RNTI 0x%04x\n", rnti);
return -1;
}
NR_UE_info_t *UE_info = &RC.nrmac[Mod_idP]->UE_info;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl;
const uint16_t sf_ahead = 6/(0x01<<subcarrierSpacing) + ((6%(0x01<<subcarrierSpacing))>0);
const uint16_t sl_ahead = sf_ahead * (0x01<<subcarrierSpacing);
sched_ctrl->rrc_processing_timer = (rrc_reconfiguration_delay<<subcarrierSpacing) + sl_ahead;
LOG_I(NR_MAC, "Activating RRC processing timer for UE %d with %d ms\n", UE_id, rrc_reconfiguration_delay);
LOG_I(NR_MAC, "Activating RRC processing timer for UE %04x with %d ms\n", UE_info->rnti, rrc_reconfiguration_delay);
return 0;
}
@@ -551,9 +550,7 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
AssertFatal(RC.nrmac[Mod_idP]->common_channels[0].frame_type == FDD,"Dynamic TDD not handled yet\n");
for (int slot = 0; slot < n; ++slot) {
if (RC.nrmac[Mod_idP]->common_channels[0].frame_type == FDD ||
(slot != 0))
RC.nrmac[Mod_idP]->dlsch_slot_bitmap[slot / 64] |= (uint64_t)((slot % nr_slots_period) < nr_dl_slots) << (slot % 64);
RC.nrmac[Mod_idP]->dlsch_slot_bitmap[slot / 64] |= (uint64_t)((slot % nr_slots_period) < nr_dl_slots) << (slot % 64);
RC.nrmac[Mod_idP]->ulsch_slot_bitmap[slot / 64] |= (uint64_t)((slot % nr_slots_period) >= nr_ulstart_slot) << (slot % 64);
LOG_I(NR_MAC, "In %s: slot %d DL %d UL %d\n",
@@ -591,37 +588,19 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
if (CellGroup) {
if (get_softmodem_params()->sa) {
calculate_preferred_dl_tda(Mod_idP, NULL);
}
const NR_ServingCellConfig_t *servingCellConfig = NULL;
if(CellGroup->spCellConfig && CellGroup->spCellConfig->spCellConfigDedicated) {
if(CellGroup->spCellConfig && CellGroup->spCellConfig->spCellConfigDedicated)
servingCellConfig = CellGroup->spCellConfig->spCellConfigDedicated;
const struct NR_ServingCellConfig__downlinkBWP_ToAddModList *bwpList = servingCellConfig->downlinkBWP_ToAddModList;
if(bwpList) {
AssertFatal(bwpList->list.count > 0, "downlinkBWP_ToAddModList has no BWPs!\n");
for (int i = 0; i < bwpList->list.count; ++i) {
const NR_BWP_Downlink_t *bwp = bwpList->list.array[i];
calculate_preferred_dl_tda(Mod_idP, bwp);
}
}
const struct NR_UplinkConfig__uplinkBWP_ToAddModList *ubwpList = servingCellConfig->uplinkConfig->uplinkBWP_ToAddModList;
if(ubwpList) {
AssertFatal(ubwpList->list.count > 0, "uplinkBWP_ToAddModList no BWPs!\n");
for (int i = 0; i < ubwpList->list.count; ++i) {
const NR_BWP_Uplink_t *ubwp = ubwpList->list.array[i];
calculate_preferred_ul_tda(Mod_idP, ubwp);
}
}
}
NR_UE_info_t *UE_info = &RC.nrmac[Mod_idP]->UE_info;
if (add_ue == 1 && get_softmodem_params()->phy_test) {
const int UE_id = add_new_nr_ue(Mod_idP, rnti, CellGroup);
LOG_I(NR_MAC,"Added new UE_id %d/%x with initial CellGroup\n",UE_id,rnti);
process_CellGroup(CellGroup,&UE_info->UE_sched_ctrl[UE_id]);
NR_UE_info_t* UE = add_new_nr_ue(RC.nrmac[Mod_idP], rnti, CellGroup);
if (UE)
LOG_I(NR_MAC,"Added new UE %x with initial CellGroup\n", rnti);
else {
LOG_E(NR_MAC,"Error adding UE %04x\n", rnti);
return -1;
}
process_CellGroup(CellGroup,&UE->UE_sched_ctrl);
} else if (add_ue == 1 && !get_softmodem_params()->phy_test) {
const int CC_id = 0;
NR_COMMON_channels_t *cc = &RC.nrmac[Mod_idP]->common_channels[CC_id];
@@ -668,12 +647,18 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
LOG_I(NR_MAC,"Added new RA process for UE RNTI %04x with initial CellGroup\n", rnti);
} else { // CellGroup has been updated
NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels[0].ServingCellConfigCommon;
const int UE_id = find_nr_UE_id(Mod_idP,rnti);
NR_UE_info_t * UE = find_nr_UE(&RC.nrmac[Mod_idP]->UE_info,rnti);
if (!UE) {
LOG_E(NR_MAC, "Can't find UE %04x\n", rnti);
return -1;
}
int target_ss;
UE_info->CellGroup[UE_id] = CellGroup;
LOG_I(NR_MAC,"Modified UE_id %d/%x with CellGroup\n",UE_id,rnti);
process_CellGroup(CellGroup,&UE_info->UE_sched_ctrl[UE_id]);
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
UE->CellGroup = CellGroup;
LOG_I(NR_MAC,"Modified rnti %04x with CellGroup\n",rnti);
process_CellGroup(CellGroup,&UE->UE_sched_ctrl);
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
const NR_PDSCH_ServingCellConfig_t *pdsch = servingCellConfig ? servingCellConfig->pdsch_ServingCellConfig->choice.setup : NULL;
if (get_softmodem_params()->sa) {
// add all available DL HARQ processes for this UE in SA
@@ -696,7 +681,7 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
genericParameters = &scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters;
}
sched_ctrl->search_space = get_searchspace(sib1 ? sib1->message.choice.c1->choice.systemInformationBlockType1 : NULL, scc, bwpd, target_ss);
sched_ctrl->coreset = get_coreset(Mod_idP, scc, bwpd, sched_ctrl->search_space, target_ss);
sched_ctrl->coreset = get_coreset(RC.nrmac[Mod_idP], scc, bwpd, sched_ctrl->search_space, target_ss);
sched_ctrl->sched_pdcch = set_pdcch_structure(RC.nrmac[Mod_idP],
sched_ctrl->search_space,
sched_ctrl->coreset,
@@ -709,7 +694,7 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
CellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig &&
CellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup
)
compute_csi_bitlen (CellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup, UE_info, UE_id, Mod_idP);
compute_csi_bitlen (CellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup, UE);
}
}
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RRC_MAC_CONFIG, VCD_FUNCTION_OUT);
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
+2 -164
View File
@@ -104,167 +104,6 @@ void clear_nr_nfapi_information(gNB_MAC_INST * gNB,
TX_req[CC_idP].Number_of_PDUs = 0;
}
/*
void check_nr_ul_failure(module_id_t module_idP,
int CC_id,
int UE_id,
frame_t frameP,
sub_frame_t slotP) {
NR_UE_info_t *UE_info = &RC.nrmac[module_idP]->UE_info;
nfapi_nr_dl_dci_request_t *DL_req = &RC.nrmac[module_idP]->DL_req[0];
uint16_t rnti = UE_RNTI(module_idP, UE_id);
NR_COMMON_channels_t *cc = RC.nrmac[module_idP]->common_channels;
// check uplink failure
if ((UE_info->UE_sched_ctrl[UE_id].ul_failure_timer > 0) &&
(UE_info->UE_sched_ctrl[UE_id].ul_out_of_sync == 0)) {
LOG_I(MAC, "UE %d rnti %x: UL Failure timer %d \n", UE_id, rnti,
UE_info->UE_sched_ctrl[UE_id].ul_failure_timer);
if (UE_info->UE_sched_ctrl[UE_id].ra_pdcch_order_sent == 0) {
UE_info->UE_sched_ctrl[UE_id].ra_pdcch_order_sent = 1;
// add a format 1A dci for this UE to request an RA procedure (only one UE per subframe)
nfapi_nr_dl_dci_request_pdu_t *dl_config_pdu = &DL_req[CC_id].dl_tti_request_body.dl_config_pdu_list[DL_req[CC_id].dl_tti_request_body.number_pdu];
memset((void *) dl_config_pdu, 0,sizeof(nfapi_dl_dci_request_pdu_t));
dl_config_pdu->pdu_type = NFAPI_DL_CONFIG_DCI_DL_PDU_TYPE;
dl_config_pdu->pdu_size = (uint8_t) (2 + sizeof(nfapi_dl_config_dci_dl_pdu));
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.tl.tag = NFAPI_DL_DCI_REQUEST_DCI_DL_PDU_REL8_TAG;
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.dci_format = NFAPI_DL_DCI_FORMAT_1A;
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.aggregation_level = get_aggregation(get_bw_index(module_idP, CC_id),
UE_info->UE_sched_ctrl[UE_id].
dl_cqi[CC_id], format1A);
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti = rnti;
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.rnti_type = 1; // CRNTI : see Table 4-10 from SCF082 - nFAPI specifications
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.transmission_power = 6000; // equal to RS power
AssertFatal((cc[CC_id].mib->message.dl_Bandwidth >= 0) && (cc[CC_id].mib->message.dl_Bandwidth < 6),
"illegal dl_Bandwidth %d\n",
(int) cc[CC_id].mib->message.dl_Bandwidth);
dl_config_pdu->dci_dl_pdu.dci_dl_pdu_rel8.resource_block_coding = nr_pdcch_order_table[cc[CC_id].mib->message.dl_Bandwidth];
DL_req[CC_id].dl_tti_request_body.number_dci++;
DL_req[CC_id].dl_tti_request_body.number_pdu++;
DL_req[CC_id].dl_tti_request_body.tl.tag = NFAPI_DL_TTI_REQUEST_BODY_TAG;
LOG_I(MAC,
"UE %d rnti %x: sending PDCCH order for RAPROC (failure timer %d), resource_block_coding %d \n",
UE_id, rnti,
UE_info->UE_sched_ctrl[UE_id].ul_failure_timer,
dl_config_pdu->dci_dl_pdu.
dci_dl_pdu_rel8.resource_block_coding);
} else { // ra_pdcch_sent==1
LOG_I(MAC,
"UE %d rnti %x: sent PDCCH order for RAPROC waiting (failure timer %d) \n",
UE_id, rnti,
UE_info->UE_sched_ctrl[UE_id].ul_failure_timer);
if ((UE_info->UE_sched_ctrl[UE_id].ul_failure_timer % 40) == 0) UE_info->UE_sched_ctrl[UE_id].ra_pdcch_order_sent = 0; // resend every 4 frames
}
UE_info->UE_sched_ctrl[UE_id].ul_failure_timer++;
// check threshold
if (UE_info->UE_sched_ctrl[UE_id].ul_failure_timer > 20000) {
// inform RRC of failure and clear timer
LOG_I(MAC,
"UE %d rnti %x: UL Failure after repeated PDCCH orders: Triggering RRC \n",
UE_id, rnti);
mac_eNB_rrc_ul_failure(module_idP, CC_id, frameP, subframeP,rnti);
UE_info->UE_sched_ctrl[UE_id].ul_failure_timer = 0;
UE_info->UE_sched_ctrl[UE_id].ul_out_of_sync = 1;
//Inform the controller about the UE deactivation. Should be moved to RRC agent in the future
if (rrc_agent_registered[module_idP]) {
LOG_W(MAC, "notify flexran Agent of UE state change\n");
agent_rrc_xface[module_idP]->flexran_agent_notify_ue_state_change(module_idP,
rnti, PROTOCOL__FLEX_UE_STATE_CHANGE_TYPE__FLUESC_DEACTIVATED);
}
}
} // ul_failure_timer>0
}
*/
/*
void schedule_nr_SRS(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP)
{
gNB_MAC_INST *gNB = RC.nrmac[module_idP];
NR_UE_info_t *UE_info = &gNB->UE_info;
nfapi_ul_config_request_body_t *ul_req;
int CC_id, UE_id;
NR_COMMON_channels_t *cc = RC.nrmac[module_idP]->common_channels;
SoundingRS_UL_ConfigCommon_t *soundingRS_UL_ConfigCommon;
struct SoundingRS_UL_ConfigDedicated *soundingRS_UL_ConfigDedicated;
uint8_t TSFC;
uint16_t deltaTSFC; // bitmap
uint8_t srs_SubframeConfig;
// table for TSFC (Period) and deltaSFC (offset)
const uint16_t deltaTSFCTabType1[15][2] = { {1, 1}, {1, 2}, {2, 2}, {1, 5}, {2, 5}, {4, 5}, {8, 5}, {3, 5}, {12, 5}, {1, 10}, {2, 10}, {4, 10}, {8, 10}, {351, 10}, {383, 10} }; // Table 5.5.3.3-2 3GPP 36.211 FDD
const uint16_t deltaTSFCTabType2[14][2] = { {2, 5}, {6, 5}, {10, 5}, {18, 5}, {14, 5}, {22, 5}, {26, 5}, {30, 5}, {70, 10}, {74, 10}, {194, 10}, {326, 10}, {586, 10}, {210, 10} }; // Table 5.5.3.3-2 3GPP 36.211 TDD
uint16_t srsPeriodicity, srsOffset;
for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) {
soundingRS_UL_ConfigCommon = &cc[CC_id].radioResourceConfigCommon->soundingRS_UL_ConfigCommon;
// check if SRS is enabled in this frame/subframe
if (soundingRS_UL_ConfigCommon) {
srs_SubframeConfig = soundingRS_UL_ConfigCommon->choice.setup.srs_SubframeConfig;
if (cc[CC_id].tdd_Config == NULL) { // FDD
deltaTSFC = deltaTSFCTabType1[srs_SubframeConfig][0];
TSFC = deltaTSFCTabType1[srs_SubframeConfig][1];
} else { // TDD
deltaTSFC = deltaTSFCTabType2[srs_SubframeConfig][0];
TSFC = deltaTSFCTabType2[srs_SubframeConfig][1];
}
// Sounding reference signal subframes are the subframes satisfying ns/2 mod TSFC (- deltaTSFC
uint16_t tmp = (subframeP % TSFC);
if ((1 << tmp) & deltaTSFC) {
// This is an SRS subframe, loop over UEs
for (UE_id = 0; UE_id < MAX_MOBILES_PER_GNB; UE_id++) {
if (!RC.nrmac[module_idP]->UE_info.active[UE_id]) continue;
ul_req = &RC.nrmac[module_idP]->UL_req[CC_id].ul_config_request_body;
// drop the allocation if the UE hasn't send RRCConnectionSetupComplete yet
if (mac_eNB_get_rrc_status(module_idP,UE_RNTI(module_idP, UE_id)) < RRC_CONNECTED) continue;
AssertFatal(UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated != NULL,
"physicalConfigDedicated is null for UE %d\n",
UE_id);
if ((soundingRS_UL_ConfigDedicated = UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->soundingRS_UL_ConfigDedicated) != NULL) {
if (soundingRS_UL_ConfigDedicated->present == SoundingRS_UL_ConfigDedicated_PR_setup) {
get_srs_pos(&cc[CC_id],
soundingRS_UL_ConfigDedicated->choice.
setup.srs_ConfigIndex,
&srsPeriodicity, &srsOffset);
if (((10 * frameP + subframeP) % srsPeriodicity) == srsOffset) {
// Program SRS
ul_req->srs_present = 1;
nfapi_ul_config_request_pdu_t * ul_config_pdu = &ul_req->ul_config_pdu_list[ul_req->number_of_pdus];
memset((void *) ul_config_pdu, 0, sizeof(nfapi_ul_config_request_pdu_t));
ul_config_pdu->pdu_type = NFAPI_UL_CONFIG_SRS_PDU_TYPE;
ul_config_pdu->pdu_size = 2 + (uint8_t) (2 + sizeof(nfapi_ul_config_srs_pdu));
ul_config_pdu->srs_pdu.srs_pdu_rel8.tl.tag = NFAPI_UL_CONFIG_REQUEST_SRS_PDU_REL8_TAG;
ul_config_pdu->srs_pdu.srs_pdu_rel8.size = (uint8_t)sizeof(nfapi_ul_config_srs_pdu);
ul_config_pdu->srs_pdu.srs_pdu_rel8.rnti = UE_info->UE_template[CC_id][UE_id].rnti;
ul_config_pdu->srs_pdu.srs_pdu_rel8.srs_bandwidth = soundingRS_UL_ConfigDedicated->choice.setup.srs_Bandwidth;
ul_config_pdu->srs_pdu.srs_pdu_rel8.frequency_domain_position = soundingRS_UL_ConfigDedicated->choice.setup.freqDomainPosition;
ul_config_pdu->srs_pdu.srs_pdu_rel8.srs_hopping_bandwidth = soundingRS_UL_ConfigDedicated->choice.setup.srs_HoppingBandwidth;;
ul_config_pdu->srs_pdu.srs_pdu_rel8.transmission_comb = soundingRS_UL_ConfigDedicated->choice.setup.transmissionComb;
ul_config_pdu->srs_pdu.srs_pdu_rel8.i_srs = soundingRS_UL_ConfigDedicated->choice.setup.srs_ConfigIndex;
ul_config_pdu->srs_pdu.srs_pdu_rel8.sounding_reference_cyclic_shift = soundingRS_UL_ConfigDedicated->choice.setup.cyclicShift; // ul_config_pdu->srs_pdu.srs_pdu_rel10.antenna_port = ;//
// ul_config_pdu->srs_pdu.srs_pdu_rel13.number_of_combs = ;//
RC.nrmac[module_idP]->UL_req[CC_id].sfn_sf = (frameP << 4) + subframeP;
RC.nrmac[module_idP]->UL_req[CC_id].header.message_id = NFAPI_UL_CONFIG_REQUEST;
ul_req->number_of_pdus++;
} // if (((10*frameP+subframeP) % srsPeriodicity) == srsOffset)
} // if (soundingRS_UL_ConfigDedicated->present == SoundingRS_UL_ConfigDedicated_PR_setup)
} // if ((soundingRS_UL_ConfigDedicated = UE_info->UE_template[CC_id][UE_id].physicalConfigDedicated->soundingRS_UL_ConfigDedicated)!=NULL)
} // for (UE_id ...
} // if((1<<tmp) & deltaTSFC)
} // SRS config
}
}
*/
bool is_xlsch_in_slot(uint64_t bitmap, sub_frame_t slot) {
if (slot>=64) return false; //quickfix for FR2 where there are more than 64 slots (bitmap to be removed)
@@ -372,7 +211,6 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
schedule_nr_prach(module_idP, f, s);
}
// Schedule CSI-RS transmission
nr_csirs_scheduling(module_idP, frame, slot, nr_slots_per_frame[*scc->ssbSubcarrierSpacing]);
@@ -398,10 +236,10 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
nr_schedule_ue_spec(module_idP, frame, slot);
stop_meas(&gNB->schedule_dlsch);
nr_schedule_pucch(module_idP, frame, slot);
nr_schedule_pucch(RC.nrmac[module_idP], frame, slot);
// This schedule SR after PUCCH for multiplexing
nr_sr_reporting(module_idP, frame, slot);
nr_sr_reporting(RC.nrmac[module_idP], frame, slot);
stop_meas(&RC.nrmac[module_idP]->eNB_scheduler);
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+48 -48
View File
@@ -465,27 +465,24 @@ void nr_schedule_msg2(uint16_t rach_frame, uint16_t rach_slot,
int FR = *scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0] >= 257 ? nr_FR2 : nr_FR1;
uint8_t start_next_period = (rach_slot-(rach_slot%tdd_period_slot)+tdd_period_slot)%nr_slots_per_frame[mu];
*msg2_slot = start_next_period + last_dl_slot_period; // initializing scheduling of slot to next mixed (or last dl) slot
*msg2_frame = ((*msg2_slot>(rach_slot))? rach_frame : (rach_frame+1))%1024;
uint8_t start_next_period = rach_slot-(rach_slot%tdd_period_slot)+tdd_period_slot;
int eff_slot = start_next_period + last_dl_slot_period; // initializing scheduling of slot to next mixed (or last dl) slot
// we can't schedule msg2 before sl_ahead since prach
int eff_slot = *msg2_slot+(*msg2_frame-rach_frame)*nr_slots_per_frame[mu];
while ((eff_slot-rach_slot)<=sl_ahead) {
*msg2_slot = (*msg2_slot+tdd_period_slot)%nr_slots_per_frame[mu];
*msg2_frame = ((*msg2_slot>(rach_slot))? rach_frame : (rach_frame+1))%1024;
eff_slot = *msg2_slot+(*msg2_frame-rach_frame)*nr_slots_per_frame[mu];
eff_slot += tdd_period_slot;
}
if (FR==nr_FR2) {
int num_tdd_period = *msg2_slot/tdd_period_slot;
int num_tdd_period = (eff_slot%nr_slots_per_frame[mu])/tdd_period_slot;
while((tdd_beam_association[num_tdd_period]!=-1)&&(tdd_beam_association[num_tdd_period]!=beam_index)) {
*msg2_slot = (*msg2_slot+tdd_period_slot)%nr_slots_per_frame[mu];
*msg2_frame = ((*msg2_slot>(rach_slot))? rach_frame : (rach_frame+1))%1024;
num_tdd_period = *msg2_slot/tdd_period_slot;
eff_slot += tdd_period_slot;
num_tdd_period = (eff_slot % nr_slots_per_frame[mu])/tdd_period_slot;
}
if(tdd_beam_association[num_tdd_period] == -1)
tdd_beam_association[num_tdd_period] = beam_index;
}
*msg2_frame=(rach_frame + eff_slot/nr_slots_per_frame[mu])%1024;
*msg2_slot=eff_slot%nr_slots_per_frame[mu];
// go to previous slot if the current scheduled slot is beyond the response window
// and if the slot is not among the PDCCH monitored ones (38.213 10.1)
while (*msg2_frame > frame_limit
@@ -542,8 +539,10 @@ void nr_initiate_ra_proc(module_id_t module_idP,
for (int i = 0; i < NR_NB_RA_PROC_MAX; i++) {
NR_RA_t *ra = &cc->ra[i];
pr_found = 0;
const int UE_id = find_nr_UE_id(module_idP, ra->rnti);
if (UE_id != -1) {
const NR_UE_info_t * UE = find_nr_UE(&nr_mac->UE_info, ra->rnti);
if (UE) {
// the UE is already registered
LOG_W(NR_MAC, "Received RA for existing RNTI %04x\n", ra->rnti);
continue;
}
if (ra->state == RA_IDLE) {
@@ -637,7 +636,7 @@ void nr_initiate_ra_proc(module_id_t module_idP,
AssertFatal(ra->ra_ss!=NULL,"SearchSpace cannot be null for RA\n");
ra->coreset = get_coreset(module_idP, scc, bwp, ra->ra_ss, NR_SearchSpace__searchSpaceType_PR_common);
ra->coreset = get_coreset(nr_mac, scc, bwp, ra->ra_ss, NR_SearchSpace__searchSpaceType_PR_common);
ra->sched_pdcch = set_pdcch_structure(nr_mac,
ra->ra_ss,
ra->coreset,
@@ -672,7 +671,7 @@ void nr_initiate_ra_proc(module_id_t module_idP,
ra->rnti = (taus() % 65518) + 1;
loop++;
} while (loop != 100
&& !((find_nr_UE_id(module_idP, ra->rnti) == -1) && (find_nr_RA_id(module_idP, CC_id, ra->rnti) == -1)
&& !((find_nr_UE(&nr_mac->UE_info, ra->rnti) == NULL) && (find_nr_RA_id(module_idP, CC_id, ra->rnti) == -1)
&& ra->rnti >= 1 && ra->rnti <= 65519));
if (loop == 100) {
LOG_E(NR_MAC, "%s:%d:%s: [RAPROC] initialisation random access aborted\n", __FILE__, __LINE__, __FUNCTION__);
@@ -685,7 +684,7 @@ void nr_initiate_ra_proc(module_id_t module_idP,
ra->beam_id = beam_index;
LOG_I(NR_MAC,
"[gNB %d][RAPROC] CC_id %d Frame %d Activating Msg2 generation in frame %d, slot %d using RA rnti %x SSB "
"[gNB %d][RAPROC] CC_id %d Frame %d Activating Msg2 generation in frame %d, slot %d using RA rnti %x SSB, new rnti %04x "
"index %u RA index %d\n",
module_idP,
CC_id,
@@ -693,6 +692,7 @@ void nr_initiate_ra_proc(module_id_t module_idP,
ra->Msg2_frame,
ra->Msg2_slot,
ra->RA_rnti,
ra->rnti,
cc->ssb_index[beam_index],
i);
@@ -1109,10 +1109,11 @@ void fill_msg3_pusch_pdu(nfapi_nr_pusch_pdu_t *pusch_pdu,
int TBS = 0;
while(TBS<7) { // TBS for msg3 is 7 bytes (except for RRCResumeRequest1 currently not implemented)
mcsindex++;
pusch_pdu->target_code_rate = nr_get_code_rate_ul(mcsindex,pusch_pdu->mcs_table);
int R = nr_get_code_rate_ul(mcsindex,pusch_pdu->mcs_table);
pusch_pdu->target_code_rate = R;
pusch_pdu->qam_mod_order = nr_get_Qm_ul(mcsindex,pusch_pdu->mcs_table);
TBS = nr_compute_tbs(pusch_pdu->qam_mod_order,
pusch_pdu->target_code_rate,
R,
pusch_pdu->rb_size,
pusch_pdu->nr_of_symbols,
num_dmrs_symb*12, // nb dmrs set for no data in dmrs symbol
@@ -1200,20 +1201,13 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t
nr_fill_rar(module_idP, ra, RAR_pdu, pusch_pdu);
}
void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP, NR_RA_t *ra)
{
void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t slotP, NR_RA_t *ra) {
gNB_MAC_INST *nr_mac = RC.nrmac[module_idP];
NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id];
if ((ra->Msg2_frame == frameP) && (ra->Msg2_slot == slotP)) {
//TODO time domain assignment for msg2 needs to be improved
uint8_t time_domain_assignment;
if(cc->frame_type == TDD)
time_domain_assignment = 1;
else
time_domain_assignment = 0;
int mcsIndex = -1; // initialization value
int rbStart = 0;
int rbSize = 8;
@@ -1253,6 +1247,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
}
// Calculate number of symbols
int time_domain_assignment = get_dl_tda(nr_mac, scc, slotP);
int startSymbolIndex, nrOfSymbols;
const int startSymbolAndLength = pdsch_TimeDomainAllocationList->list.array[time_domain_assignment]->startSymbolAndLength;
SLIV2SL(startSymbolAndLength, &startSymbolIndex, &nrOfSymbols);
@@ -1525,7 +1520,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
}
ra->state = WAIT_Msg3;
LOG_D(NR_MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: RA state %d\n", module_idP, frameP, slotP, ra->state);
LOG_W(NR_MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: rnti %04x RA state %d\n", module_idP, frameP, slotP, ra->rnti, ra->state);
}
}
@@ -1568,9 +1563,14 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
ra->rnti = ra->crnti;
}
int UE_id = find_nr_UE_id(module_idP, ra->rnti);
NR_UE_info_t *UE_info = &nr_mac->UE_info;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_UE_info_t * UE = find_nr_UE(&nr_mac->UE_info, ra->rnti);
if (!UE) {
LOG_E(NR_MAC,"want to generate Msg4, but rnti %04x not in the table\n", ra->rnti);
return;
}
LOG_I(NR_MAC,"Generate msg4, rnti: %04x\n", ra->rnti);
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_BWP_t *genericParameters = bwp ? & bwp->bwp_Common->genericParameters : &scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters;
@@ -1603,7 +1603,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
// Remove UE associated to TC-RNTI
if(harq->round==0 && ra->msg3_dcch_dtch) {
mac_remove_nr_ue(module_idP, tc_rnti);
mac_remove_nr_ue(nr_mac, tc_rnti);
}
// get CCEindex, needed also for PUCCH and then later for PDCCH
@@ -1634,7 +1634,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
LOG_D(NR_MAC,"[RAPROC] Msg4 r_pucch %d (CCEIndex %d, nb_of_candidates %d, delta_PRI %d)\n", r_pucch, CCEIndex, nr_of_candidates, delta_PRI);
int alloc = nr_acknack_scheduling(module_idP, UE_id, frameP, slotP, r_pucch, 1);
int alloc = nr_acknack_scheduling(module_idP, UE, frameP, slotP, r_pucch, 1);
AssertFatal(alloc>=0,"Couldn't find a pucch allocation for ack nack (msg4)\n");
NR_sched_pucch_t *pucch = &sched_ctrl->sched_pucch[alloc];
harq->feedback_slot = pucch->ul_slot;
@@ -1799,7 +1799,8 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
pdsch_pdu_rel15->SubcarrierSpacing = genericParameters->subcarrierSpacing;
pdsch_pdu_rel15->CyclicPrefix = 0;
pdsch_pdu_rel15->NrOfCodewords = 1;
pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcsIndex,mcsTableIdx);
int R = nr_get_code_rate_dl(mcsIndex,mcsTableIdx);
pdsch_pdu_rel15->targetCodeRate[0] = R;
pdsch_pdu_rel15->qamModOrder[0] = 2;
pdsch_pdu_rel15->mcsIndex[0] = mcsIndex;
pdsch_pdu_rel15->mcsTable[0] = mcsTableIdx;
@@ -1949,10 +1950,9 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
if(ra->msg3_dcch_dtch) {
// If the UE used MSG3 to transfer a DCCH or DTCH message, then contention resolution is successful upon transmission of PDCCH
LOG_I(NR_MAC, "(ue %i, rnti 0x%04x) CBRA procedure succeeded!\n", UE_id, ra->rnti);
LOG_I(NR_MAC, "(ue rnti 0x%04x) CBRA procedure succeeded!\n", ra->rnti);
nr_clear_ra_proc(module_idP, CC_id, frameP, ra);
UE_info->active[UE_id] = true;
UE_info->Msg4_ACKed[UE_id] = true;
UE->Msg4_ACKed = true;
remove_front_nr_list(&sched_ctrl->feedback_dl_harq);
harq->feedback_slot = -1;
@@ -1964,7 +1964,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
const NR_ServingCellConfig_t *servingCellConfig = ra->CellGroup ? ra->CellGroup->spCellConfig->spCellConfigDedicated : NULL;
uint32_t delay_ms = servingCellConfig && servingCellConfig->downlinkBWP_ToAddModList ? NR_RRC_SETUP_DELAY_MS + NR_RRC_BWP_SWITCHING_DELAY_MS : NR_RRC_SETUP_DELAY_MS;
sched_ctrl->rrc_processing_timer = (delay_ms << genericParameters->subcarrierSpacing);
LOG_I(NR_MAC, "(%d.%d) Activating RRC processing timer for UE %d with %d ms\n", frameP, slotP, UE_id, delay_ms);
LOG_I(NR_MAC, "(%d.%d) Activating RRC processing timer for UE 0x%04x with %d ms\n", frameP, slotP, UE->rnti, delay_ms);
ra->state = WAIT_Msg4_ACK;
LOG_D(NR_MAC,"[gNB %d][RAPROC] Frame %d, Subframe %d: RA state %d\n", module_idP, frameP, slotP, ra->state);
}
@@ -1973,24 +1973,24 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
void nr_check_Msg4_Ack(module_id_t module_id, int CC_id, frame_t frame, sub_frame_t slot, NR_RA_t *ra) {
int UE_id = find_nr_UE_id(module_id, ra->rnti);
NR_UE_info_t * UE = find_nr_UE(&RC.nrmac[module_id]->UE_info, ra->rnti);
const int current_harq_pid = ra->harq_pid;
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_harq_t *harq = &sched_ctrl->harq_processes[current_harq_pid];
NR_mac_stats_t *stats = &UE_info->mac_stats[UE_id];
NR_mac_stats_t *stats = &UE->mac_stats;
LOG_D(NR_MAC, "ue %d, rnti 0x%04x, harq is waiting %d, round %d, frame %d %d, harq id %d\n", UE_id, ra->rnti, harq->is_waiting, harq->round, frame, slot, current_harq_pid);
LOG_D(NR_MAC, "ue rnti 0x%04x, harq is waiting %d, round %d, frame %d %d, harq id %d\n", ra->rnti, harq->is_waiting, harq->round, frame, slot, current_harq_pid);
if (harq->is_waiting == 0) {
if (harq->round == 0) {
if (stats->dlsch_errors == 0) {
LOG_I(NR_MAC, "(ue %i, rnti 0x%04x) Received Ack of RA-Msg4. CBRA procedure succeeded!\n", UE_id, ra->rnti);
UE_info->active[UE_id] = true;
UE_info->Msg4_ACKed[UE_id] = true;
if (stats->dl.errors == 0) {
LOG_A(NR_MAC, "(UE RNTI 0x%04x) Received Ack of RA-Msg4. CBRA procedure succeeded!\n", ra->rnti);
UE->Msg4_ACKed = true;
} else {
LOG_I(NR_MAC, "(ue %i, rnti 0x%04x) RA Procedure failed at Msg4!\n", UE_id, ra->rnti);
LOG_I(NR_MAC, "(ue rnti 0x%04x) RA Procedure failed at Msg4!\n", ra->rnti);
}
nr_clear_ra_proc(module_id, CC_id, frame, ra);
@@ -1998,7 +1998,7 @@ void nr_check_Msg4_Ack(module_id_t module_id, int CC_id, frame_t frame, sub_fram
remove_nr_list(&sched_ctrl->retrans_dl_harq, current_harq_pid);
}
} else {
LOG_D(NR_MAC, "(ue %i, rnti 0x%04x) Received Nack of RA-Msg4. Preparing retransmission!\n", UE_id, ra->rnti);
LOG_I(NR_MAC, "(UE %04x) Received Nack of RA-Msg4. Preparing retransmission!\n", ra->rnti);
ra->Msg4_frame = (frame + 1) % 1024;
ra->Msg4_slot = 1;
ra->state = Msg4;
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
+129 -299
View File
@@ -53,105 +53,21 @@
#define WORD 32
//#define SIZE_OF_POINTER sizeof (void *)
void calculate_preferred_dl_tda(module_id_t module_id, const NR_BWP_Downlink_t *bwp) {
gNB_MAC_INST *nrmac = RC.nrmac[module_id];
const int bwp_id = bwp ? bwp->bwp_Id : 0;
const int get_dl_tda(const gNB_MAC_INST *nrmac, const NR_ServingCellConfigCommon_t *scc, int slot) {
if (nrmac->preferred_dl_tda[bwp_id])
return;
const NR_TDD_UL_DL_Pattern_t *tdd = scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL;
AssertFatal(tdd || nrmac->common_channels->frame_type == FDD, "Dynamic TDD not handled yet\n");
/* there is a mixed slot only when in TDD */
NR_ServingCellConfigCommon_t *scc = nrmac->common_channels->ServingCellConfigCommon;
frame_type_t frame_type = nrmac->common_channels->frame_type;
const int n = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
const NR_TDD_UL_DL_Pattern_t *tdd =
scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL;
int symb_dlMixed = 0;
int nr_mix_slots = 0;
int nr_slots_period = n;
// Use special TDA in case of CSI-RS
if(nrmac->UE_info.sched_csirs)
return 1;
if (tdd) {
symb_dlMixed = (1 << tdd->nrofDownlinkSymbols) - 1;
nr_mix_slots = tdd->nrofDownlinkSymbols != 0 || tdd->nrofUplinkSymbols != 0;
nr_slots_period /= get_nb_periods_per_frame(tdd->dl_UL_TransmissionPeriodicity);
} else
// if TDD configuration is not present and the band is not FDD, it means it is a dynamic TDD configuration
AssertFatal(nrmac->common_channels->frame_type == FDD,"Dynamic TDD not handled yet\n");
int target_ss;
if (bwp) {
target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
} else {
target_ss = NR_SearchSpace__searchSpaceType_PR_common;
}
const NR_SIB1_t *sib1 = nrmac->common_channels[0].sib1 ? nrmac->common_channels[0].sib1->message.choice.c1->choice.systemInformationBlockType1 : NULL;
NR_SearchSpace_t *search_space = get_searchspace(sib1,
scc,
bwp ? bwp->bwp_Dedicated : NULL,
target_ss);
NR_ControlResourceSet_t *coreset = get_coreset(module_id, scc, bwp ? bwp->bwp_Dedicated : NULL, search_space, target_ss);
// get coreset symbol "map"
const uint16_t symb_coreset = (1 << coreset->duration) - 1;
NR_PDSCH_TimeDomainResourceAllocationList_t *tdaList = get_pdsch_TimeDomainAllocationList(bwp,
scc,
sib1);
AssertFatal(tdaList->list.count >= 1, "need to have at least one TDA for DL slots\n");
/* check that TDA index 0 fits into DL and does not overlap CORESET */
const NR_PDSCH_TimeDomainResourceAllocation_t *tdaP_DL = tdaList->list.array[0];
AssertFatal(!tdaP_DL->k0 || *tdaP_DL->k0 == 0,
"TimeDomainAllocation at index 1: non-null k0 (%ld) is not supported by the scheduler\n",
*tdaP_DL->k0);
int start, len;
SLIV2SL(tdaP_DL->startSymbolAndLength, &start, &len);
const uint16_t symb_tda = ((1 << len) - 1) << start;
// check whether coreset and TDA overlap: then we cannot use it. Note that
// here we assume that the coreset is scheduled every slot (which it
// currently is) and starting at symbol 0
AssertFatal((symb_coreset & symb_tda) == 0, "TDA index 0 for DL overlaps with CORESET\n");
/* check that TDA index 1 fits into DL part of mixed slot, if it exists */
int tdaMi = -1;
if (frame_type == TDD && tdaList->list.count > 1) {
const NR_PDSCH_TimeDomainResourceAllocation_t *tdaP_Mi = tdaList->list.array[1];
AssertFatal(!tdaP_Mi->k0 || *tdaP_Mi->k0 == 0,
"TimeDomainAllocation at index 1: non-null k0 (%ld) is not supported by the scheduler\n",
*tdaP_Mi->k0);
int start, len;
SLIV2SL(tdaP_Mi->startSymbolAndLength, &start, &len);
const uint16_t symb_tda = ((1 << len) - 1) << start;
// check whether coreset and TDA overlap: then, we cannot use it. Also,
// check whether TDA is entirely within mixed slot DL. Note that
// here we assume that the coreset is scheduled every slot (which it
// currently is)
if ((symb_coreset & symb_tda) == 0 && (symb_dlMixed & symb_tda) == symb_tda) {
tdaMi = 1;
} else {
LOG_E(MAC,
"TDA index 1 DL overlaps with CORESET or is not entirely in mixed slot (symb_coreset %x symb_dlMixed %x symb_tda %x), won't schedule DL mixed slot\n",
symb_coreset,
symb_dlMixed,
symb_tda);
}
}
nrmac->preferred_dl_tda[bwp_id] = malloc(n * sizeof(*nrmac->preferred_dl_tda[bwp_id]));
for (int i = 0; i < n; ++i) {
nrmac->preferred_dl_tda[bwp_id][i] = -1;
if (frame_type == FDD || i % nr_slots_period < tdd->nrofDownlinkSlots)
nrmac->preferred_dl_tda[bwp_id][i] = 0;
else if (nr_mix_slots && i % nr_slots_period == tdd->nrofDownlinkSlots)
nrmac->preferred_dl_tda[bwp_id][i] = tdaMi;
LOG_D(MAC, "slot %d preferred_dl_tda %d\n", i, nrmac->preferred_dl_tda[bwp_id][i]);
if (tdd && tdd->nrofDownlinkSymbols > 1) { // if there is a mixed slot where we can transmit DL
const int nr_slots_period = tdd->nrofDownlinkSlots + tdd->nrofUplinkSlots + 1;
if ((slot%nr_slots_period) == tdd->nrofDownlinkSlots)
return 2;
}
return 0; // if FDD or not mixed slot in TDD, for now use default TDA (TODO handle CSI-RS slots)
}
// Compute and write all MAC CEs and subheaders, and return number of written
@@ -397,88 +313,12 @@ int nr_write_ce_dlsch_pdu(module_id_t module_idP,
return offset;
}
#define BLER_UPDATE_FRAME 10
#define BLER_FILTER 0.9f
int get_mcs_from_bler(module_id_t mod_id, int CC_id, frame_t frame, sub_frame_t slot, int UE_id, int mcs_table) {
gNB_MAC_INST *nrmac = RC.nrmac[mod_id];
const NR_ServingCellConfigCommon_t *scc = nrmac->common_channels[CC_id].ServingCellConfigCommon;
const int n = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
int max_allowed_mcs = (mcs_table == 1) ? 27 : 28;
int max_mcs = nrmac->dl_max_mcs;
if (nrmac->dl_max_mcs>max_allowed_mcs)
max_mcs = max_allowed_mcs;
NR_DL_bler_stats_t *bler_stats = &nrmac->UE_info.UE_sched_ctrl[UE_id].dl_bler_stats;
/* first call: everything is zero. Initialize to sensible default */
if (bler_stats->last_frame_slot == 0 && bler_stats->mcs == 0) {
bler_stats->last_frame_slot = frame * n + slot;
bler_stats->mcs = 9;
bler_stats->bler = (nrmac->dl_bler_target_lower + nrmac->dl_bler_target_upper) / 2;
bler_stats->rd2_bler = nrmac->dl_rd2_bler_threshold;
}
const int now = frame * n + slot;
int diff = now - bler_stats->last_frame_slot;
if (diff < 0) // wrap around
diff += 1024 * n;
const uint8_t old_mcs = bler_stats->mcs;
const NR_mac_stats_t *stats = &nrmac->UE_info.mac_stats[UE_id];
// TODO put back this condition when relevant
/*const int dret3x = stats->dlsch_rounds[3] - bler_stats->dlsch_rounds[3];
if (dret3x > 0) {
if there is a third retransmission, decrease MCS for stabilization and
restart averaging window to stabilize transmission
bler_stats->last_frame_slot = now;
bler_stats->mcs = max(9, bler_stats->mcs - 1);
memcpy(bler_stats->dlsch_rounds, stats->dlsch_rounds, sizeof(stats->dlsch_rounds));
LOG_D(MAC, "%4d.%2d: %d retx in 3rd round, setting MCS to %d and restarting window\n", frame, slot, dret3x, bler_stats->mcs);
return bler_stats->mcs;
}*/
if (diff < BLER_UPDATE_FRAME * n)
return old_mcs; // no update
// last update is longer than x frames ago
const int dtx = (int)(stats->dlsch_rounds[0] - bler_stats->dlsch_rounds[0]);
const int dretx = (int)(stats->dlsch_rounds[1] - bler_stats->dlsch_rounds[1]);
const int dretx2 = (int)(stats->dlsch_rounds[2] - bler_stats->dlsch_rounds[2]);
const float bler_window = dtx > 0 ? (float) dretx / dtx : bler_stats->bler;
const float rd2_bler_wnd = dtx > 0 ? (float) dretx2 / dtx : bler_stats->rd2_bler;
bler_stats->bler = BLER_FILTER * bler_stats->bler + (1 - BLER_FILTER) * bler_window;
bler_stats->rd2_bler = BLER_FILTER / 4 * bler_stats->rd2_bler + (1 - BLER_FILTER / 4) * rd2_bler_wnd;
int new_mcs = old_mcs;
// TODO put back this condition when relevant
/* first ensure that number of 2nd retx is below threshold. If this is the
* case, use 1st retx to adjust faster
if (bler_stats->rd2_bler > nrmac->dl_rd2_bler_threshold && old_mcs > 6) {
new_mcs -= 2;
} else if (bler_stats->rd2_bler < nrmac->dl_rd2_bler_threshold) {*/
if (bler_stats->bler < nrmac->dl_bler_target_lower && old_mcs < max_mcs && dtx > 9)
new_mcs += 1;
else if (bler_stats->bler > nrmac->dl_bler_target_upper && old_mcs > 6)
new_mcs -= 1;
// else we are within threshold boundaries
bler_stats->last_frame_slot = now;
bler_stats->mcs = new_mcs;
memcpy(bler_stats->dlsch_rounds, stats->dlsch_rounds, sizeof(stats->dlsch_rounds));
LOG_D(MAC, "%4d.%2d MCS %d -> %d (dtx %d, dretx %d, BLER wnd %.3f avg %.6f, dretx2 %d, RD2 BLER wnd %.3f avg %.6f)\n",
frame, slot, old_mcs, new_mcs, dtx, dretx, bler_window, bler_stats->bler, dretx2, rd2_bler_wnd, bler_stats->rd2_bler);
return new_mcs;
}
void nr_store_dlsch_buffer(module_id_t module_id,
frame_t frame,
sub_frame_t slot) {
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
UE_iterator(RC.nrmac[module_id]->UE_info.list, UE) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
sched_ctrl->num_total_bytes = 0;
sched_ctrl->dl_pdus_total = 0;
@@ -486,13 +326,11 @@ void nr_store_dlsch_buffer(module_id_t module_id,
// Note: DL_SCH_LCID_DCCH, DL_SCH_LCID_DCCH1, DL_SCH_LCID_DTCH
for (int i = 0; i < sched_ctrl->dl_lc_num; ++i) {
const int lcid = sched_ctrl->dl_lc_ids[i];
const uint16_t rnti = UE_info->rnti[UE_id];
LOG_D(NR_MAC, "In %s: UE %d/%x: LCID %d\n", __FUNCTION__, UE_id, rnti, lcid);
const uint16_t rnti = UE->rnti;
LOG_D(NR_MAC, "In %s: UE %x: LCID %d\n", __FUNCTION__, rnti, lcid);
if (lcid == DL_SCH_LCID_DTCH && sched_ctrl->rrc_processing_timer > 0) {
continue;
}
start_meas(&RC.nrmac[module_id]->rlc_status_ind);
sched_ctrl->rlc_status[lcid] = mac_rlc_status_ind(module_id,
rnti,
@@ -518,7 +356,7 @@ void nr_store_dlsch_buffer(module_id_t module_id,
slot,
lcid < 4 ? "DCCH":"DTCH",
lcid,
UE_id,
UE->rnti,
sched_ctrl->rlc_status[lcid].bytes_in_buffer,
sched_ctrl->num_total_bytes,
sched_ctrl->dl_pdus_total,
@@ -532,15 +370,14 @@ bool allocate_dl_retransmission(module_id_t module_id,
sub_frame_t slot,
uint16_t *rballoc_mask,
int *n_rb_sched,
int UE_id,
NR_UE_info_t * UE,
int current_harq_pid) {
gNB_MAC_INST *nr_mac = RC.nrmac[module_id];
const NR_ServingCellConfigCommon_t *scc = nr_mac->common_channels->ServingCellConfigCommon;
NR_UE_info_t *UE_info = &nr_mac->UE_info;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_sched_pdsch_t *retInfo = &sched_ctrl->harq_processes[current_harq_pid].sched_pdsch;
NR_CellGroupConfig_t *cg = UE_info->CellGroup[UE_id];
NR_CellGroupConfig_t *cg = UE->CellGroup;
NR_BWP_DownlinkDedicated_t *bwpd =
cg &&
@@ -566,7 +403,7 @@ bool allocate_dl_retransmission(module_id_t module_id,
int rbStart = 0; // start wrt BWPstart
NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
int rbSize = 0;
const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0][slot];
const int tda = get_dl_tda(RC.nrmac[module_id], scc, slot);
AssertFatal(tda>=0,"Unable to find PDSCH time domain allocation in list\n");
if (tda == retInfo->time_domain_allocation) {
@@ -580,7 +417,7 @@ bool allocate_dl_retransmission(module_id_t module_id,
rbStart++;
if (rbStart >= bwpSize) {
LOG_D(NR_MAC, "cannot allocate retransmission for UE %d/RNTI %04x: no resources\n", UE_id, UE_info->rnti[UE_id]);
LOG_D(NR_MAC, "cannot allocate retransmission for RNTI %04x: no resources\n", UE->rnti);
return false;
}
@@ -653,7 +490,7 @@ bool allocate_dl_retransmission(module_id_t module_id,
/* Find a free CCE */
const int cid = sched_ctrl->coreset->controlResourceSetId;
const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
const uint16_t Y = get_Y(cid%3, slot, UE->rnti);
uint8_t nr_of_candidates;
for (int i=0; i<5; i++) {
@@ -675,8 +512,8 @@ bool allocate_dl_retransmission(module_id_t module_id,
Y);
if (CCEIndex<0) {
LOG_D(MAC, "%4d.%2d could not find CCE for DL DCI retransmission UE %d/RNTI %04x\n",
frame, slot, UE_id, UE_info->rnti[UE_id]);
LOG_D(MAC, "%4d.%2d could not find CCE for DL DCI retransmission RNTI %04x\n",
frame, slot, UE->rnti);
return false;
}
@@ -684,12 +521,11 @@ bool allocate_dl_retransmission(module_id_t module_id,
* allocation after CCE alloc fail would be more complex) */
int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, sched_ctrl->active_ubwp, ubwpd, CCEIndex);
const int alloc = nr_acknack_scheduling(module_id, UE_id, frame, slot, r_pucch, 0);
const int alloc = nr_acknack_scheduling(module_id, UE, frame, slot, r_pucch, 0);
if (alloc<0) {
LOG_D(MAC,
"could not find PUCCH for UE %d/%04x@%d.%d\n",
UE_id,
UE_info->rnti[UE_id],
"could not find PUCCH for UE %04x@%d.%d\n",
UE->rnti,
frame,
slot);
RC.nrmac[module_id]->pdcch_cand[cid]--;
@@ -715,47 +551,54 @@ bool allocate_dl_retransmission(module_id_t module_id,
return true;
}
float thr_ue[MAX_MOBILES_PER_GNB];
uint32_t pf_tbs[3][29]; // pre-computed, approximate TBS values for PF coefficient
typedef struct UEsched_s {
float coef;
NR_UE_info_t * UE;
} UEsched_t;
static int comparator(const void *p, const void *q) {
return ((UEsched_t*)p)->coef < ((UEsched_t*)q)->coef;
}
void pf_dl(module_id_t module_id,
frame_t frame,
sub_frame_t slot,
NR_list_t *UE_list,
NR_UE_info_t **UE_list,
int max_num_ue,
int n_rb_sched,
uint16_t *rballoc_mask) {
gNB_MAC_INST *mac = RC.nrmac[module_id];
NR_UE_info_t *UE_info = &mac->UE_info;
NR_ServingCellConfigCommon_t *scc=mac->common_channels[0].ServingCellConfigCommon;
float coeff_ue[MAX_MOBILES_PER_GNB];
// UEs that could be scheduled
int ue_array[MAX_MOBILES_PER_GNB];
int layers[MAX_MOBILES_PER_GNB];
NR_list_t UE_sched = { .head = -1, .next = ue_array, .tail = -1, .len = MAX_MOBILES_PER_GNB };
UEsched_t UE_sched[MAX_MOBILES_PER_GNB] = {0};
int remainUEs = max_num_ue;
int curUE = 0;
/* Loop UE_info->list to check retransmission */
for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
if (UE_info->Msg4_ACKed[UE_id] != true) continue;
UE_iterator(UE_list, UE) {
if (UE->Msg4_ACKed != true)
continue;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
if (sched_ctrl->ul_failure==1 && get_softmodem_params()->phy_test==0) continue;
const NR_mac_dir_stats_t *stats = &UE->mac_stats.dl;
NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch;
NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
/* get the PID of a HARQ process awaiting retrnasmission, or -1 otherwise */
sched_pdsch->dl_harq_pid = sched_ctrl->retrans_dl_harq.head;
layers[UE_id] = ps->nrOfLayers; // initialization of layers to the previous value in the strcuture
UE->layers = ps->nrOfLayers; // initialization of layers to the previous value in the strcuture
/* Calculate Throughput */
const float a = 0.0005f; // corresponds to 200ms window
const uint32_t b = UE_info->mac_stats[UE_id].dlsch_current_bytes;
thr_ue[UE_id] = (1 - a) * thr_ue[UE_id] + a * b;
const uint32_t b = UE->mac_stats.dl.current_bytes;
UE->dl_thr_ue = (1 - a) * UE->dl_thr_ue + a * b;
/* retransmission */
if (sched_pdsch->dl_harq_pid >= 0) {
/* Allocate retransmission */
bool r = allocate_dl_retransmission(module_id, frame, slot, rballoc_mask, &n_rb_sched, UE_id, sched_pdsch->dl_harq_pid);
bool r = allocate_dl_retransmission(module_id, frame, slot, rballoc_mask, &n_rb_sched, UE, sched_pdsch->dl_harq_pid);
if (!r) {
LOG_D(NR_MAC, "%4d.%2d retransmission can NOT be allocated\n", frame, slot);
@@ -763,18 +606,23 @@ void pf_dl(module_id_t module_id,
}
/* reduce max_num_ue once we are sure UE can be allocated, i.e., has CCE */
max_num_ue--;
remainUEs--;
if (max_num_ue < 0) return;
if (remainUEs == 0)
// we have filled all with mandatory retransmissions
// no need to schedule new transmissions
return;
} else {
/* Check DL buffer and skip this UE if no bytes and no TA necessary */
if (sched_ctrl->num_total_bytes == 0 && frame != (sched_ctrl->ta_frame + 10) % 1024)
continue;
/* Calculate coeff */
set_dl_mcs(sched_pdsch,sched_ctrl,&mac->dl_max_mcs,ps->mcsTableIdx);
sched_pdsch->mcs = get_mcs_from_bler(module_id, /* CC_id = */ 0, frame, slot, UE_id, ps->mcsTableIdx);
layers[UE_id] = set_dl_nrOfLayers(sched_ctrl);
const NR_bler_options_t *bo = &mac->dl_bler;
const int max_mcs_table = ps->mcsTableIdx == 1 ? 27 : 28;
const int max_mcs = min(sched_ctrl->dl_max_mcs, max_mcs_table);
sched_pdsch->mcs = get_mcs_from_bler(bo, stats, &sched_ctrl->dl_bler_stats, max_mcs, frame);
UE->layers = set_dl_nrOfLayers(sched_ctrl);
const uint8_t Qm = nr_get_Qm_dl(sched_pdsch->mcs, ps->mcsTableIdx);
const uint16_t R = nr_get_code_rate_dl(sched_pdsch->mcs, ps->mcsTableIdx);
uint32_t tbs = nr_compute_tbs(Qm,
@@ -784,40 +632,26 @@ void pf_dl(module_id_t module_id,
0, /* N_PRB_DMRS * N_DMRS_SLOT */
0 /* N_PRB_oh, 0 for initialBWP */,
0 /* tb_scaling */,
layers[UE_id]) >> 3;
coeff_ue[UE_id] = (float) tbs / thr_ue[UE_id];
LOG_D(NR_MAC,"b %d, thr_ue[%d] %f, tbs %d, coeff_ue[%d] %f\n",
b, UE_id, thr_ue[UE_id], tbs, UE_id, coeff_ue[UE_id]);
UE->layers) >> 3;
float coeff_ue = (float) tbs / UE->dl_thr_ue;
LOG_D(NR_MAC,"UE %04x b %d, thr_ue %f, tbs %d, coeff_ue %f\n",
UE->rnti, b, UE->dl_thr_ue, tbs, coeff_ue);
/* Create UE_sched list for UEs eligible for new transmission*/
add_tail_nr_list(&UE_sched, UE_id);
UE_sched[curUE].coef=coeff_ue;
UE_sched[curUE].UE=UE;
curUE++;
}
}
qsort(UE_sched, sizeof(*UE_sched), sizeofArray(UE_sched), comparator);
UEsched_t *iterator = UE_sched;
const int min_rbSize = 5;
/* Loop UE_sched to find max coeff and allocate transmission */
while (max_num_ue > 0 && n_rb_sched >= min_rbSize && UE_sched.head >= 0) {
/* Find max coeff from UE_sched*/
int *max = &UE_sched.head; /* assume head is max */
int *p = &UE_sched.next[*max];
while (*p >= 0) {
/* if the current one has larger coeff, save for later */
if (coeff_ue[*p] > coeff_ue[*max])
max = p;
p = &UE_sched.next[*p];
}
/* remove the max one: do not use remove_nr_list() it goes through the
* whole list every time. Note that UE_sched.tail might not be set
* correctly anymore */
const int UE_id = *max;
p = &UE_sched.next[*max];
*max = UE_sched.next[*max];
*p = -1;
NR_CellGroupConfig_t *cg = UE_info->CellGroup[UE_id];
while (remainUEs> 0 && n_rb_sched >= min_rbSize && iterator->UE != NULL) {
NR_CellGroupConfig_t *cg = iterator->UE->CellGroup;
NR_BWP_DownlinkDedicated_t *bwpd =
cg &&
@@ -832,26 +666,33 @@ void pf_dl(module_id_t module_id,
cg->spCellConfig->spCellConfigDedicated->uplinkConfig ?
cg->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP : NULL;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const uint16_t rnti = UE_info->rnti[UE_id];
const NR_SIB1_t *sib1 = RC.nrmac[module_id]->common_channels[0].sib1 ? RC.nrmac[module_id]->common_channels[0].sib1->message.choice.c1->choice.systemInformationBlockType1 : NULL;
NR_UE_sched_ctrl_t *sched_ctrl = &iterator->UE->UE_sched_ctrl;
const uint16_t rnti = iterator->UE->rnti;
const NR_SIB1_t *sib1 = RC.nrmac[module_id]->common_channels[0].sib1 ?
RC.nrmac[module_id]->common_channels[0].sib1->message.choice.c1->choice.systemInformationBlockType1 :
NULL;
NR_BWP_t *genericParameters = get_dl_bwp_genericParameters(sched_ctrl->active_bwp,
RC.nrmac[module_id]->common_channels[0].ServingCellConfigCommon,
sib1);
const int coresetid = (sched_ctrl->active_bwp||bwpd) ? sched_ctrl->coreset->controlResourceSetId : RC.nrmac[module_id]->sched_ctrlCommon->coreset->controlResourceSetId;
const uint16_t bwpSize = coresetid == 0 ? RC.nrmac[module_id]->cset0_bwp_size : NRRIV2BW(genericParameters->locationAndBandwidth, MAX_BWP_SIZE);
const int coresetid = (sched_ctrl->active_bwp||bwpd) ?
sched_ctrl->coreset->controlResourceSetId :
RC.nrmac[module_id]->sched_ctrlCommon->coreset->controlResourceSetId;
const uint16_t bwpSize = coresetid == 0 ?
RC.nrmac[module_id]->cset0_bwp_size :
NRRIV2BW(genericParameters->locationAndBandwidth, MAX_BWP_SIZE);
int rbStart = 0; // start wrt BWPstart
if (sched_ctrl->available_dl_harq.head < 0) {
LOG_D(MAC, "UE %d RNTI %04x has no free HARQ process, skipping\n", UE_id, UE_info->rnti[UE_id]);
LOG_D(MAC, "RNTI %04x has no free HARQ process, skipping\n", iterator->UE->rnti);
iterator++;
continue;
}
/* Find a free CCE */
const int cid = sched_ctrl->coreset->controlResourceSetId;
const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
const uint16_t Y = get_Y(cid%3, slot, iterator->UE->rnti);
uint8_t nr_of_candidates;
for (int i=0; i<5; i++) {
@@ -873,7 +714,8 @@ void pf_dl(module_id_t module_id,
Y);
if (CCEIndex<0) {
LOG_D(NR_MAC, "%4d.%2d could not find CCE for DL DCI UE %d/RNTI %04x\n", frame, slot, UE_id, rnti);
LOG_D(NR_MAC, "%4d.%2d could not find CCE for DL DCI RNTI %04x\n", frame, slot, rnti);
iterator++;
continue;
}
@@ -881,48 +723,40 @@ void pf_dl(module_id_t module_id,
* allocation after CCE alloc fail would be more complex) */
int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, sched_ctrl->active_ubwp, ubwpd, CCEIndex);
const int alloc = nr_acknack_scheduling(module_id, UE_id, frame, slot, r_pucch, 0);
const int alloc = nr_acknack_scheduling(module_id, iterator->UE, frame, slot, r_pucch, 0);
if (alloc<0) {
LOG_D(NR_MAC,
"could not find PUCCH for UE %d/%04x@%d.%d\n",
UE_id,
"could not find PUCCH for %04x@%d.%d\n",
rnti,
frame,
slot);
mac->pdcch_cand[cid]--;
iterator++;
continue;
}
/* reduce max_num_ue once we are sure UE can be allocated, i.e., has CCE
* and PUCCH */
max_num_ue--;
AssertFatal(max_num_ue >= 0, "Illegal max_num_ue %d\n", max_num_ue);
sched_ctrl->cce_index = CCEIndex;
fill_pdcch_vrb_map(mac,
/* CC_id = */ 0,
&sched_ctrl->sched_pdcch,
CCEIndex,
sched_ctrl->aggregation_level);
/* reduce max_num_ue once we are sure UE can be allocated, i.e., has CCE */
max_num_ue--;
if (max_num_ue < 0) return;
/* MCS has been set above */
const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0][slot];
const int tda = get_dl_tda(RC.nrmac[module_id], scc, slot);
AssertFatal(tda>=0,"Unable to find PDSCH time domain allocation in list\n");
NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch;
NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
if (ps->nrOfLayers != layers[UE_id] || ps->time_domain_allocation != tda) {
if (ps->nrOfLayers != iterator->UE->layers || ps->time_domain_allocation != tda ) {
nr_set_pdsch_semi_static(sib1,
scc,
UE_info->CellGroup[UE_id],
iterator->UE->CellGroup,
sched_ctrl->active_bwp,
bwpd,
tda,
layers[UE_id],
iterator->UE->layers,
sched_ctrl,
ps);
}
@@ -967,27 +801,25 @@ void pf_dl(module_id_t module_id,
for (int rb = 0; rb < sched_pdsch->rbSize; rb++)
rballoc_mask[rb + sched_pdsch->rbStart] ^= slbitmap;
remainUEs--;
iterator++;
}
}
void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t slot) {
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
NR_UEs_t *UE_info = &RC.nrmac[module_id]->UE_info;
if (UE_info->num_UEs == 0)
if (UE_info->list[0] == NULL)
return;
NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[0].ServingCellConfigCommon;
const int CC_id = 0;
/* Get bwpSize and TDAfrom the first UE */
/* This is temporary and it assumes all UEs have the same BWP and TDA*/
int UE_id = UE_info->list.head;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const int bwp_id = sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0;
if (!RC.nrmac[module_id]->preferred_dl_tda[bwp_id])
return;
const int tda = RC.nrmac[module_id]->preferred_dl_tda[bwp_id][slot];
NR_UE_info_t *UE=UE_info->list[0];
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
const int tda = get_dl_tda(RC.nrmac[module_id], scc, slot);
int startSymbolIndex, nrOfSymbols;
const struct NR_PDSCH_TimeDomainResourceAllocationList *tdaList = sched_ctrl->active_bwp ?
sched_ctrl->active_bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList :
@@ -1002,10 +834,10 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
sib1);
NR_BWP_DownlinkDedicated_t *bwpd =
UE_info->CellGroup[UE_id] &&
UE_info->CellGroup[UE_id]->spCellConfig &&
UE_info->CellGroup[UE_id]->spCellConfig->spCellConfigDedicated ?
UE_info->CellGroup[UE_id]->spCellConfig->spCellConfigDedicated->initialDownlinkBWP : NULL;
UE->CellGroup &&
UE->CellGroup->spCellConfig &&
UE->CellGroup->spCellConfig->spCellConfigDedicated ?
UE->CellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP : NULL;
const int coresetid = (sched_ctrl->active_bwp||bwpd) ? sched_ctrl->coreset->controlResourceSetId : RC.nrmac[module_id]->sched_ctrlCommon->coreset->controlResourceSetId;
@@ -1034,7 +866,7 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
pf_dl(module_id,
frame,
slot,
&UE_info->list,
UE_info->list,
MAX_MOBILES_PER_GNB,
n_rb_sched,
rballoc_mask);
@@ -1081,18 +913,17 @@ void nr_schedule_ue_spec(module_id_t module_id,
gNB_mac->pre_processor_dl(module_id, frame, slot);
const int CC_id = 0;
NR_ServingCellConfigCommon_t *scc = gNB_mac->common_channels[CC_id].ServingCellConfigCommon;
NR_UE_info_t *UE_info = &gNB_mac->UE_info;
NR_UEs_t *UE_info = &gNB_mac->UE_info;
nfapi_nr_dl_tti_request_body_t *dl_req = &gNB_mac->DL_req[CC_id].dl_tti_request_body;
NR_list_t *UE_list = &UE_info->list;
for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
UE_iterator(UE_info->list, UE) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
if (sched_ctrl->ul_failure==1 && get_softmodem_params()->phy_test==0) continue;
NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch;
UE_info->mac_stats[UE_id].dlsch_current_bytes = 0;
NR_CellGroupConfig_t *cg = UE_info->CellGroup[UE_id];
UE->mac_stats.dl.current_bytes = 0;
NR_CellGroupConfig_t *cg = UE->CellGroup;
NR_BWP_DownlinkDedicated_t *bwpd =
cg &&
@@ -1106,13 +937,13 @@ void nr_schedule_ue_spec(module_id_t module_id,
* If we add the CE, ta_apply will be reset */
if (frame == (sched_ctrl->ta_frame + 10) % 1024) {
sched_ctrl->ta_apply = true; /* the timer is reset once TA CE is scheduled */
LOG_D(NR_MAC, "[UE %d][%d.%d] UL timing alignment procedures: setting flag for Timing Advance command\n", UE_id, frame, slot);
LOG_D(NR_MAC, "[UE %04x][%d.%d] UL timing alignment procedures: setting flag for Timing Advance command\n", UE->rnti, frame, slot);
}
if (sched_pdsch->rbSize <= 0)
continue;
const rnti_t rnti = UE_info->rnti[UE_id];
const rnti_t rnti = UE->rnti;
/* pre-computed PDSCH values that only change if time domain
* allocation/DMRS parameters change. Updated in the preprocessor through
* nr_set_pdsch_semi_static() */
@@ -1128,8 +959,8 @@ void nr_schedule_ue_spec(module_id_t module_id,
/* PP has not selected a specific HARQ Process, get a new one */
current_harq_pid = sched_ctrl->available_dl_harq.head;
AssertFatal(current_harq_pid >= 0,
"no free HARQ process available for UE %d\n",
UE_id);
"no free HARQ process available for UE %04x\n",
UE->rnti);
remove_front_nr_list(&sched_ctrl->available_dl_harq);
sched_pdsch->dl_harq_pid = current_harq_pid;
} else {
@@ -1149,12 +980,11 @@ void nr_schedule_ue_spec(module_id_t module_id,
harq->feedback_frame = pucch->frame;
harq->feedback_slot = pucch->ul_slot;
harq->is_waiting = true;
UE_info->mac_stats[UE_id].dlsch_rounds[harq->round]++;
UE->mac_stats.dl.rounds[harq->round]++;
LOG_D(NR_MAC,
"%4d.%2d [DLSCH/PDSCH/PUCCH] UE %d RNTI %04x DCI L %d start %3d RBs %3d startSymbol %2d nb_symbol %2d dmrspos %x MCS %2d nrOfLayers %d TBS %4d HARQ PID %2d round %d RV %d NDI %d dl_data_to_ULACK %d (%d.%d) PUCCH allocation %d TPC %d\n",
"%4d.%2d [DLSCH/PDSCH/PUCCH] RNTI %04x DCI L %d start %3d RBs %3d startSymbol %2d nb_symbol %2d dmrspos %x MCS %2d nrOfLayers %d TBS %4d HARQ PID %2d round %d RV %d NDI %d dl_data_to_ULACK %d (%d.%d) PUCCH allocation %d TPC %d\n",
frame,
slot,
UE_id,
rnti,
sched_ctrl->aggregation_level,
sched_pdsch->rbStart,
@@ -1197,7 +1027,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
dl_tti_pdcch_pdu->PDUSize = (uint8_t)(2+sizeof(nfapi_nr_dl_tti_pdcch_pdu));
dl_req->nPDUs += 1;
pdcch_pdu = &dl_tti_pdcch_pdu->pdcch_pdu.pdcch_pdu_rel15;
LOG_D(NR_MAC,"Trying to configure DL pdcch for UE %d, bwp %d, cs %d\n",UE_id,bwp_id,coresetid);
LOG_D(NR_MAC,"Trying to configure DL pdcch for UE %04x, bwp %d, cs %d\n", UE->rnti, bwp_id, coresetid);
NR_ControlResourceSet_t *coreset = (bwp||bwpd)? sched_ctrl->coreset:gNB_mac->sched_ctrlCommon->coreset;
nr_configure_pdcch(pdcch_pdu, coreset, genericParameters, &sched_ctrl->sched_pdcch);
gNB_mac->pdcch_pdu_idx[CC_id][coresetid] = pdcch_pdu;
@@ -1229,6 +1059,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
pdsch_pdu->CyclicPrefix = genericParameters->cyclicPrefix ? *genericParameters->cyclicPrefix : 0;
// Codeword information
pdsch_pdu->NrOfCodewords = 1;
//number of information bits per 1024 coded bits expressed in 0.1 bit units
pdsch_pdu->targetCodeRate[0] = R;
pdsch_pdu->qamModOrder[0] = Qm;
pdsch_pdu->mcsIndex[0] = sched_pdsch->mcs;
@@ -1258,8 +1089,8 @@ void nr_schedule_ue_spec(module_id_t module_id,
pdsch_pdu->NrOfSymbols = ps->nrOfSymbols;
// Precoding
if (sched_ctrl->set_pmi) {
int report_id = sched_ctrl->CSI_report.cri_ri_li_pmi_cqi_report.csi_report_id;
nr_csi_report_t *csi_report = &UE_info->csi_report_template[UE_id][report_id];
const int report_id = sched_ctrl->CSI_report.cri_ri_li_pmi_cqi_report.csi_report_id;
nr_csi_report_t *csi_report = &UE->csi_report_template[report_id];
pdsch_pdu->precodingAndBeamforming.prg_size = pdsch_pdu->rbSize;
pdsch_pdu->precodingAndBeamforming.prgs_list[0].pm_idx = set_pm_index(sched_ctrl,
nrOfLayers,
@@ -1400,17 +1231,16 @@ void nr_schedule_ue_spec(module_id_t module_id,
* from RLC or encode MAC CEs. The TX_req structure is filled below
* or copy data to FAPI structures */
LOG_D(NR_MAC,
"%d.%2d DL retransmission UE %d/RNTI %04x HARQ PID %d round %d NDI %d\n",
"%d.%2d DL retransmission RNTI %04x HARQ PID %d round %d NDI %d\n",
frame,
slot,
UE_id,
rnti,
current_harq_pid,
harq->round,
harq->ndi);
AssertFatal(harq->sched_pdsch.tb_size == TBS,
"UE %d mismatch between scheduled TBS and buffered TB for HARQ PID %d\n",
UE_id,
"UE %04x mismatch between scheduled TBS and buffered TB for HARQ PID %d\n",
UE->rnti,
current_harq_pid);
T(T_GNB_MAC_RETRANSMISSION_DL_PDU_WITH_DATA, T_INT(module_id), T_INT(CC_id), T_INT(rnti),
T_INT(frame), T_INT(slot), T_INT(current_harq_pid), T_INT(harq->round), T_BUFFER(harq->transportBlock, TBS));
@@ -1482,7 +1312,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
lcid_bytes += len;
}
UE_info->mac_stats[UE_id].lc_bytes_tx[lcid] += lcid_bytes;
UE->mac_stats.dl.lc_bytes[lcid] += lcid_bytes;
}
} else if (get_softmodem_params()->phy_test || get_softmodem_params()->do_ra) {
/* we will need the large header, phy-test typically allocates all
@@ -1520,8 +1350,8 @@ void nr_schedule_ue_spec(module_id_t module_id,
buf=bufEnd;
}
UE_info->mac_stats[UE_id].dlsch_total_bytes += TBS;
UE_info->mac_stats[UE_id].dlsch_current_bytes = TBS;
UE->mac_stats.dl.total_bytes += TBS;
UE->mac_stats.dl.current_bytes = TBS;
/* save retransmission information */
harq->sched_pdsch = *sched_pdsch;
/* save which time allocation has been used, to be used on
@@ -1533,10 +1363,10 @@ void nr_schedule_ue_spec(module_id_t module_id,
sched_ctrl->ta_apply = false;
sched_ctrl->ta_frame = frame;
LOG_D(NR_MAC,
"%d.%2d UE %d TA scheduled, resetting TA frame\n",
"%d.%2d UE %04x TA scheduled, resetting TA frame\n",
frame,
slot,
UE_id);
UE->rnti);
}
T(T_GNB_MAC_DL_PDU_WITH_DATA, T_INT(module_id), T_INT(CC_id), T_INT(rnti),
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
+30 -106
View File
@@ -69,7 +69,6 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
nfapi_nr_pdu_t *TX_req;
uint16_t rnti = 0x1234;
// int time_domain_assignment,k0;
NR_ServingCellConfigCommon_t *scc=cc->ServingCellConfigCommon;
@@ -152,8 +151,6 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
NrOfSymbols = NrOfSymbols_tmp;
StartSymbolIndex = StartSymbolIndex_tmp;
mappingtype = mappingtype_tmp;
// k0 = *scc->downlinkConfigCommon->initialDownlinkBWP->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0;
// time_domain_assignment = i;
}
}
AssertFatal(StartSymbolIndex>=0,"StartSymbolIndex is negative\n");
@@ -165,78 +162,6 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
StartSymbolIndex,
mappingtype, 1);
/*
AssertFatal(k0==0,"k0 is not zero for Initial DL BWP TimeDomain Alloc\n");
nr_configure_css_dci_initial(pdcch_pdu_rel15,
scs,
scs,
FR,
0,
0,
0,
sfn_sf, slotP,
slots_per_frame,
dlBWP_carrier_bandwidth);
pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
pdsch_pdu_rel15->rbStart,
dlBWP_carrier_bandwidth);
pdu_rel15->time_domain_assignment = time_domain_assignment;
pdu_rel15->vrb_to_prb_mapping = 1;
pdu_rel15->mcs = 9;
pdu_rel15->tb_scaling = 1;
pdu_rel15->ra_preamble_index = 25;
pdu_rel15->format_indicator = 1;
pdu_rel15->ndi = 1;
pdu_rel15->rv = 0;
pdu_rel15->harq_pid = 0;
pdu_rel15->dai = 2;
pdu_rel15->tpc = 2;
pdu_rel15->pucch_resource_indicator = 7;
pdu_rel15->pdsch_to_harq_feedback_timing_indicator = 7;
LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d, time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n",
pdu_rel15->frequency_domain_assignment,
pdu_rel15->time_domain_assignment,
pdu_rel15->vrb_to_prb_mapping,
pdu_rel15->mcs,
pdu_rel15->tb_scaling,
pdu_rel15->ndi,
pdu_rel15->rv);
params_rel15->rnti = rnti;
params_rel15->rnti_type = NFAPI_NR_RNTI_C;
params_rel15->dci_format = NFAPI_NR_DL_DCI_FORMAT_1_0;
//params_rel15->aggregation_level = 1;
LOG_D(MAC, "DCI type 1 params: rnti %x, rnti_type %d, dci_format %d\n \
coreset params: mux_pattern %d, n_rb %d, n_symb %d, rb_offset %d \n \
ss params : nb_ss_sets_per_slot %d, first symb %d, nb_slots %d, sfn_mod2 %d, first slot %d\n",
params_rel15->rnti,
params_rel15->rnti_type,
params_rel15->dci_format,
params_rel15->mux_pattern,
params_rel15->n_rb,
params_rel15->n_symb,
params_rel15->rb_offset,
params_rel15->nb_ss_sets_per_slot,
params_rel15->first_symbol,
params_rel15->nb_slots,
params_rel15->sfn_mod2,
params_rel15->first_slot);
nr_get_tbs_dl(&dl_tti_pdsch_pdu->pdsch_pdu, dl_tti_dci_pdu->dci_dl_pdu,0);
LOG_D(MAC, "DLSCH PDU: start PRB %d n_PRB %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d\n",
pdsch_pdu_rel15->rbStart,
pdsch_pdu_rel15->rbSize,
pdsch_pdu_rel15->StartSymbolIndex,
pdsch_pdu_rel15->NrOfSymbols,
pdsch_pdu_rel15->nrOfLayers,
pdsch_pdu_rel15->NrOfCodewords,
pdsch_pdu_rel15->mcsIndex[0]);
*/
nr_mac->DL_req[CC_id].dl_tti_request_body.nPDUs+=2;
TX_req = &nr_mac->TX_req[CC_id].pdu_list[nr_mac->TX_req[CC_id].Number_of_PDUs];
@@ -266,20 +191,16 @@ void nr_preprocessor_phytest(module_id_t module_id,
{
if (!is_xlsch_in_slot(dlsch_slot_bitmap, slot))
return;
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
NR_UE_info_t *UE = RC.nrmac[module_id]->UE_info.list[0];
NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[0].ServingCellConfigCommon;
const int UE_id = 0;
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
const int CC_id = 0;
AssertFatal(UE_info->active[UE_id],
"%s(): expected UE %d to be active\n",
__func__,
UE_id);
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const int tda = sched_ctrl->active_bwp ? RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp->bwp_Id][slot] : 1;
const int tda = get_dl_tda(RC.nrmac[module_id], scc, slot);
NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static;
ps->nrOfLayers = target_dl_Nl;
if (ps->time_domain_allocation != tda || ps->nrOfLayers != target_dl_Nl)
nr_set_pdsch_semi_static(NULL, scc, UE_info->CellGroup[UE_id], sched_ctrl->active_bwp, NULL, tda, target_dl_Nl, sched_ctrl, ps);
nr_set_pdsch_semi_static(NULL, scc, UE->CellGroup, sched_ctrl->active_bwp, NULL, tda, target_dl_Nl,sched_ctrl , ps);
/* find largest unallocated chunk */
const int bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
@@ -315,7 +236,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
sched_ctrl->dl_lc_num = 1;
const int lcid = DL_SCH_LCID_DTCH;
sched_ctrl->dl_lc_ids[sched_ctrl->dl_lc_num - 1] = lcid;
const uint16_t rnti = UE_info->rnti[UE_id];
const uint16_t rnti = UE->rnti;
/* update sched_ctrl->num_total_bytes so that postprocessor schedules data,
* if available */
sched_ctrl->rlc_status[lcid] = mac_rlc_status_ind(module_id,
@@ -342,7 +263,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
AssertFatal(nr_of_candidates>0,"nr_of_candidates is 0\n");
const int cid = sched_ctrl->coreset->controlResourceSetId;
const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
const uint16_t Y = get_Y(cid%3, slot, UE->rnti);
int CCEIndex = find_pdcch_candidate(RC.nrmac[module_id],
CC_id,
@@ -353,17 +274,16 @@ void nr_preprocessor_phytest(module_id_t module_id,
Y);
AssertFatal(CCEIndex >= 0,
"%s(): could not find CCE for UE %d\n",
"%s(): could not find CCE for UE %04x\n",
__func__,
UE_id);
UE->rnti);
int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, sched_ctrl->active_ubwp, NULL, CCEIndex);
const int alloc = nr_acknack_scheduling(module_id, UE_id, frame, slot, r_pucch, 0);
const int alloc = nr_acknack_scheduling(module_id, UE, frame, slot, r_pucch, 0);
if (alloc < 0) {
LOG_D(MAC,
"%s(): could not find PUCCH for UE %d/%04x@%d.%d\n",
"%s(): could not find PUCCH for UE %04x@%d.%d\n",
__func__,
UE_id,
rnti,
frame,
slot);
@@ -421,32 +341,36 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
NR_COMMON_channels_t *cc = nr_mac->common_channels;
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
const int mu = scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.subcarrierSpacing;
NR_UE_info_t *UE_info = &nr_mac->UE_info;
NR_UE_info_t *UE = nr_mac->UE_info.list[0];
AssertFatal(UE_info->num_UEs <= 1,
"%s() cannot handle more than one UE, but found %d\n",
__func__,
UE_info->num_UEs);
if (UE_info->num_UEs == 0)
AssertFatal(nr_mac->UE_info.list[1] == NULL,
"cannot handle more than one UE\n");
if (UE == NULL)
return false;
const int UE_id = 0;
const int CC_id = 0;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
const int tda = sched_ctrl->active_ubwp ? RC.nrmac[module_id]->preferred_ul_tda[sched_ctrl->active_ubwp->bwp_Id][slot] : 1;
if (tda < 0)
return false;
const struct NR_PUSCH_TimeDomainResourceAllocationList *tdaList =
sched_ctrl->active_ubwp->bwp_Common->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList;
const int temp_tda = get_ul_tda(nr_mac, scc, slot);
if (temp_tda < 0)
return false;
AssertFatal(temp_tda < tdaList->list.count,
"time domain assignment %d >= %d\n",
temp_tda,
tdaList->list.count);
int K2 = get_K2(scc,NULL,sched_ctrl->active_ubwp, temp_tda, mu);
const int sched_frame = frame + (slot + K2 >= nr_slots_per_frame[mu]);
const int sched_slot = (slot + K2) % nr_slots_per_frame[mu];
const int tda = get_ul_tda(nr_mac, scc, sched_slot);
if (tda < 0)
return false;
AssertFatal(tda < tdaList->list.count,
"time domain assignment %d >= %d\n",
tda,
tdaList->list.count);
int K2 = get_K2(scc,NULL,sched_ctrl->active_ubwp, tda, mu);
const int sched_frame = frame + (slot + K2 >= nr_slots_per_frame[mu]);
const int sched_slot = (slot + K2) % nr_slots_per_frame[mu];
/* check if slot is UL, and that slot is 8 (assuming K2=6 because of UE
* limitations). Note that if K2 or the TDD configuration is changed, below
* conditions might exclude each other and never be true */
@@ -515,7 +439,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
AssertFatal(nr_of_candidates>0,"nr_of_candidates is 0\n");
const int cid = sched_ctrl->coreset->controlResourceSetId;
const uint16_t Y = get_Y(cid%3, slot, UE_info->rnti[UE_id]);
const uint16_t Y = get_Y(cid%3, slot, UE->rnti);
int CCEIndex = find_pdcch_candidate(nr_mac,
CC_id,
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+260 -532
View File
File diff suppressed because it is too large Load Diff
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_srs.c
+12 -15
View File
@@ -34,18 +34,17 @@
extern RAN_CONTEXT_t RC;
void nr_configure_srs(nfapi_nr_srs_pdu_t *srs_pdu, int module_id, int CC_id, int UE_id, NR_SRS_Resource_t *srs_resource) {
void nr_configure_srs(nfapi_nr_srs_pdu_t *srs_pdu, int module_id, int CC_id,NR_UE_info_t* UE, NR_SRS_Resource_t *srs_resource) {
gNB_MAC_INST *nrmac = RC.nrmac[module_id];
NR_ServingCellConfigCommon_t *scc = nrmac->common_channels[CC_id].ServingCellConfigCommon;
NR_UE_info_t *UE_info = &nrmac->UE_info;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_BWP_t ubwp = sched_ctrl->active_ubwp ?
sched_ctrl->active_ubwp->bwp_Common->genericParameters :
scc->uplinkConfigCommon->initialUplinkBWP->genericParameters;
srs_pdu->rnti = UE_info->rnti[UE_id];
srs_pdu->rnti = UE->rnti;
srs_pdu->handle = 0;
srs_pdu->bwp_size = NRRIV2BW(ubwp.locationAndBandwidth, MAX_BWP_SIZE);;
srs_pdu->bwp_start = NRRIV2PRBOFFSET(ubwp.locationAndBandwidth, MAX_BWP_SIZE);;
@@ -82,7 +81,7 @@ void nr_configure_srs(nfapi_nr_srs_pdu_t *srs_pdu, int module_id, int CC_id, int
srs_pdu->t_offset = get_nr_srs_offset(srs_resource->resourceType.choice.periodic->periodicityAndOffset_p);
}
void nr_fill_nfapi_srs(int module_id, int CC_id, int UE_id, sub_frame_t slot, NR_SRS_Resource_t *srs_resource) {
void nr_fill_nfapi_srs(int module_id, int CC_id, NR_UE_info_t* UE, sub_frame_t slot, NR_SRS_Resource_t *srs_resource) {
nfapi_nr_ul_tti_request_t *future_ul_tti_req = &RC.nrmac[module_id]->UL_tti_req_ahead[0][slot];
AssertFatal(future_ul_tti_req->n_pdus <
@@ -94,7 +93,7 @@ void nr_fill_nfapi_srs(int module_id, int CC_id, int UE_id, sub_frame_t slot, NR
memset(srs_pdu, 0, sizeof(nfapi_nr_srs_pdu_t));
future_ul_tti_req->n_pdus += 1;
nr_configure_srs(srs_pdu, module_id, CC_id, UE_id, srs_resource);
nr_configure_srs(srs_pdu, module_id, CC_id, UE, srs_resource);
}
/*******************************************************************
@@ -111,21 +110,19 @@ void nr_fill_nfapi_srs(int module_id, int CC_id, int UE_id, sub_frame_t slot, NR
void nr_schedule_srs(int module_id, frame_t frame) {
gNB_MAC_INST *nrmac = RC.nrmac[module_id];
NR_UE_info_t *UE_info = &nrmac->UE_info;
const NR_list_t *UE_list = &UE_info->list;
for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
NR_UEs_t *UE_info = &nrmac->UE_info;
UE_iterator(UE_info->list, UE) {
const int CC_id = 0;
NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[CC_id].ServingCellConfigCommon;
NR_CellGroupConfig_t *cg = UE_info->CellGroup[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_CellGroupConfig_t *cg = UE->CellGroup;
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
sched_ctrl->sched_srs.frame = -1;
sched_ctrl->sched_srs.slot = -1;
sched_ctrl->sched_srs.srs_scheduled = false;
if(!UE_info->Msg4_ACKed[UE_id] || sched_ctrl->rrc_processing_timer > 0) {
if(!UE->Msg4_ACKed || sched_ctrl->rrc_processing_timer > 0) {
continue;
}
@@ -178,11 +175,11 @@ void nr_schedule_srs(int module_id, frame_t frame) {
// Check if UE will transmit the SRS in this frame
if ( ((frame - offset/n_slots_frame)*n_slots_frame)%period == 0) {
LOG_D(NR_MAC,"Scheduling SRS reception for %d.%d\n", frame, offset%n_slots_frame);
nr_fill_nfapi_srs(module_id, CC_id, UE_id, offset%n_slots_frame, srs_resource);
nr_fill_nfapi_srs(module_id, CC_id, UE, offset%n_slots_frame, srs_resource);
sched_ctrl->sched_srs.frame = frame;
sched_ctrl->sched_srs.slot = offset%n_slots_frame;
sched_ctrl->sched_srs.srs_scheduled = true;
}
}
}
}
}
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c
+151 -153
View File
@@ -38,17 +38,15 @@
extern RAN_CONTEXT_t RC;
void nr_fill_nfapi_pucch(module_id_t mod_id,
frame_t frame,
sub_frame_t slot,
const NR_sched_pucch_t *pucch,
int UE_id)
{
gNB_MAC_INST *nr_mac = RC.nrmac[mod_id];
NR_UE_info_t *UE_info = &nr_mac->UE_info;
static void nr_fill_nfapi_pucch(gNB_MAC_INST *nrmac,
frame_t frame,
sub_frame_t slot,
const NR_sched_pucch_t *pucch,
NR_UE_info_t* UE)
{
nfapi_nr_ul_tti_request_t *future_ul_tti_req =
&RC.nrmac[mod_id]->UL_tti_req_ahead[0][pucch->ul_slot];
&nrmac->UL_tti_req_ahead[0][pucch->ul_slot];
AssertFatal(future_ul_tti_req->SFN == pucch->frame
&& future_ul_tti_req->Slot == pucch->ul_slot,
"Current %4d.%2d : future UL_tti_req's frame.slot %4d.%2d does not match PUCCH %4d.%2d\n",
@@ -57,9 +55,12 @@ void nr_fill_nfapi_pucch(module_id_t mod_id,
future_ul_tti_req->Slot,
pucch->frame,
pucch->ul_slot);
AssertFatal(future_ul_tti_req->n_pdus <
sizeof(future_ul_tti_req->pdus_list) / sizeof(future_ul_tti_req->pdus_list[0]),
"Invalid future_ul_tti_req->n_pdus %d\n", future_ul_tti_req->n_pdus);
// n_pdus is number of pdus, so, in the array, it is the index of the next free element
if (future_ul_tti_req->n_pdus >= sizeofArray(future_ul_tti_req->pdus_list) ) {
LOG_E(NR_MAC,"future_ul_tti_req->n_pdus %d is full, slot: %d, sr flag %d dropping request\n",
future_ul_tti_req->n_pdus, pucch->ul_slot, pucch->sr_flag);
return;
}
future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE;
future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pucch_pdu_t);
nfapi_nr_pucch_pdu_t *pucch_pdu = &future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pucch_pdu;
@@ -77,9 +78,9 @@ void nr_fill_nfapi_pucch(module_id_t mod_id,
pucch->dai_c,
pucch->csi_bits,
pucch->resource_indicator);
NR_ServingCellConfigCommon_t *scc = RC.nrmac[mod_id]->common_channels->ServingCellConfigCommon;
NR_CellGroupConfig_t *cg=UE_info->CellGroup[UE_id];
NR_COMMON_channels_t * common_ch=nrmac->common_channels;
NR_ServingCellConfigCommon_t *scc = common_ch->ServingCellConfigCommon;
NR_CellGroupConfig_t *cg=UE->CellGroup;
NR_BWP_UplinkDedicated_t *ubwpd = cg && cg->spCellConfig && cg->spCellConfig->spCellConfigDedicated &&
cg->spCellConfig->spCellConfigDedicated->uplinkConfig ?
@@ -88,14 +89,14 @@ void nr_fill_nfapi_pucch(module_id_t mod_id,
LOG_D(NR_MAC,"%4d.%2d Calling nr_configure_pucch (ubwpd %p,r_pucch %d) pucch to be scheduled in %4d.%2d\n",
frame,slot,ubwpd,pucch->r_pucch,pucch->frame,pucch->ul_slot);
const NR_SIB1_t *sib1 = nr_mac->common_channels[0].sib1 ? nr_mac->common_channels[0].sib1->message.choice.c1->choice.systemInformationBlockType1 : NULL;
const NR_SIB1_t *sib1 = common_ch->sib1 ? common_ch->sib1->message.choice.c1->choice.systemInformationBlockType1 : NULL;
nr_configure_pucch(sib1,
pucch_pdu,
scc,
UE_info->CellGroup[UE_id],
UE_info->UE_sched_ctrl[UE_id].active_ubwp,
UE->CellGroup,
UE->UE_sched_ctrl.active_ubwp,
ubwpd,
UE_info->rnti[UE_id],
UE->rnti,
pucch->resource_indicator,
pucch->csi_bits,
pucch->dai_c,
@@ -139,22 +140,18 @@ int diff_rsrp_ssb_csi_meas_10_1_6_1_2[16] = {
};
void nr_schedule_pucch(int Mod_idP,
void nr_schedule_pucch(gNB_MAC_INST *nrmac,
frame_t frameP,
sub_frame_t slotP)
{
gNB_MAC_INST *nrmac = RC.nrmac[Mod_idP];
if (!is_xlsch_in_slot(nrmac->ulsch_slot_bitmap[slotP / 64], slotP))
return;
NR_UE_info_t *UE_info = &nrmac->UE_info;
const NR_list_t *UE_list = &UE_info->list;
for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
UE_iterator(nrmac->UE_info.list, UE) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
const int n = sizeof(sched_ctrl->sched_pucch) / sizeof(*sched_ctrl->sched_pucch);
for (int i = 0; i < n; i++) {
NR_sched_pucch_t *curr_pucch = &UE_info->UE_sched_ctrl[UE_id].sched_pucch[i];
NR_sched_pucch_t *curr_pucch = &UE->UE_sched_ctrl.sched_pucch[i];
const uint16_t O_ack = curr_pucch->dai_c;
const uint16_t O_csi = curr_pucch->csi_bits;
const uint8_t O_sr = curr_pucch->sr_flag;
@@ -162,9 +159,11 @@ void nr_schedule_pucch(int Mod_idP,
|| frameP != curr_pucch->frame
|| slotP != curr_pucch->ul_slot)
continue;
if (O_csi > 0) LOG_D(NR_MAC,"Scheduling PUCCH[%d] RX for UE %d in %4d.%2d O_ack %d, O_sr %d, O_csi %d\n",
i,UE_id,curr_pucch->frame,curr_pucch->ul_slot,O_ack,O_sr,O_csi);
nr_fill_nfapi_pucch(Mod_idP, frameP, slotP, curr_pucch, UE_id);
if (O_csi > 0)
LOG_D(NR_MAC,"Scheduling PUCCH[%d] RX for UE %04x in %4d.%2d O_ack %d, O_sr %d, O_csi %d\n",
i,UE->rnti,curr_pucch->frame,curr_pucch->ul_slot,O_ack,O_sr,O_csi);
nr_fill_nfapi_pucch(nrmac, frameP, slotP, curr_pucch, UE);
memset(curr_pucch, 0, sizeof(*curr_pucch));
}
}
@@ -565,7 +564,7 @@ void compute_cqi_bitlen(struct NR_CSI_ReportConfig *csi_reportconfig,
//!TODO : same function can be written to handle csi_resources
void compute_csi_bitlen(NR_CSI_MeasConfig_t *csi_MeasConfig, NR_UE_info_t *UE_info, int UE_id, module_id_t Mod_idP){
void compute_csi_bitlen(NR_CSI_MeasConfig_t *csi_MeasConfig, NR_UE_info_t *UE){
uint8_t csi_report_id = 0;
uint8_t nb_resources = 0;
NR_CSI_ReportConfig__reportQuantity_PR reportQuantity_type;
@@ -577,7 +576,7 @@ void compute_csi_bitlen(NR_CSI_MeasConfig_t *csi_MeasConfig, NR_UE_info_t *UE_in
for (csi_report_id=0; csi_report_id < csi_MeasConfig->csi_ReportConfigToAddModList->list.count; csi_report_id++){
struct NR_CSI_ReportConfig *csi_reportconfig = csi_MeasConfig->csi_ReportConfigToAddModList->list.array[csi_report_id];
// MAC structure for CSI measurement reports (per UE and per report)
nr_csi_report_t *csi_report = &UE_info->csi_report_template[UE_id][csi_report_id];
nr_csi_report_t *csi_report = &UE->csi_report_template[csi_report_id];
// csi-ResourceConfigId of a CSI-ResourceConfig included in the configuration
// (either CSI-RS or SSB)
csi_ResourceConfigId = csi_reportconfig->resourcesForChannelMeasurement;
@@ -662,24 +661,22 @@ void compute_csi_bitlen(NR_CSI_MeasConfig_t *csi_MeasConfig, NR_UE_info_t *UE_in
}
uint16_t nr_get_csi_bitlen(int Mod_idP,
int UE_id,
uint16_t nr_get_csi_bitlen(NR_UE_info_t *UE,
uint8_t csi_report_id) {
uint16_t csi_bitlen = 0;
uint16_t max_bitlen = 0;
NR_UE_info_t *UE_info = &RC.nrmac[Mod_idP]->UE_info;
L1_RSRP_bitlen_t * CSI_report_bitlen = NULL;
CSI_Meas_bitlen_t * csi_meas_bitlen = NULL;
if (NR_CSI_ReportConfig__reportQuantity_PR_ssb_Index_RSRP==UE_info->csi_report_template[UE_id][csi_report_id].reportQuantity_type||
NR_CSI_ReportConfig__reportQuantity_PR_cri_RSRP==UE_info->csi_report_template[UE_id][csi_report_id].reportQuantity_type){
CSI_report_bitlen = &(UE_info->csi_report_template[UE_id][csi_report_id].CSI_report_bitlen); //This might need to be moodif for Aperiodic CSI-RS measurements
if (NR_CSI_ReportConfig__reportQuantity_PR_ssb_Index_RSRP==UE->csi_report_template[csi_report_id].reportQuantity_type||
NR_CSI_ReportConfig__reportQuantity_PR_cri_RSRP==UE->csi_report_template[csi_report_id].reportQuantity_type){
CSI_report_bitlen = &(UE->csi_report_template[csi_report_id].CSI_report_bitlen); //This might need to be moodif for Aperiodic CSI-RS measurements
csi_bitlen+= ((CSI_report_bitlen->cri_ssbri_bitlen * CSI_report_bitlen->nb_ssbri_cri) +
CSI_report_bitlen->rsrp_bitlen +(CSI_report_bitlen->diff_rsrp_bitlen *
(CSI_report_bitlen->nb_ssbri_cri -1 )));
} else{
csi_meas_bitlen = &(UE_info->csi_report_template[UE_id][csi_report_id].csi_meas_bitlen); //This might need to be moodif for Aperiodic CSI-RS measurements
csi_meas_bitlen = &(UE->csi_report_template[csi_report_id].csi_meas_bitlen); //This might need to be moodif for Aperiodic CSI-RS measurements
uint16_t temp_bitlen;
for (int i=0; i<8; i++) {
temp_bitlen = (csi_meas_bitlen->cri_bitlen+
@@ -705,11 +702,10 @@ void nr_csi_meas_reporting(int Mod_idP,
NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels->ServingCellConfigCommon;
const int n_slots_frame = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
NR_UE_info_t *UE_info = &RC.nrmac[Mod_idP]->UE_info;
NR_list_t *UE_list = &UE_info->list;
for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
const NR_CellGroupConfig_t *CellGroup = UE_info->CellGroup[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
UE_iterator(RC.nrmac[Mod_idP]->UE_info.list, UE ) {
const NR_CellGroupConfig_t *CellGroup = UE->CellGroup;
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
if ((sched_ctrl->rrc_processing_timer > 0) || (sched_ctrl->ul_failure==1 && get_softmodem_params()->phy_test==0)) {
continue;
}
@@ -761,13 +757,13 @@ void nr_csi_meas_reporting(int Mod_idP,
&& !curr_pucch->sr_flag
&& curr_pucch->dai_c == 0,
"PUCCH not free at index 1 for UE %04x\n",
UE_info->rnti[UE_id]);
UE->rnti);
curr_pucch->r_pucch = -1;
curr_pucch->frame = frame;
curr_pucch->ul_slot = sched_slot;
curr_pucch->resource_indicator = res_index;
curr_pucch->csi_bits +=
nr_get_csi_bitlen(Mod_idP,UE_id,csi_report_id);
nr_get_csi_bitlen(UE,csi_report_id);
const NR_SIB1_t *sib1 = RC.nrmac[Mod_idP]->common_channels[0].sib1 ? RC.nrmac[Mod_idP]->common_channels[0].sib1->message.choice.c1->choice.systemInformationBlockType1 : NULL;
NR_BWP_t *genericParameters = get_ul_bwp_genericParameters(sched_ctrl->active_ubwp,
@@ -819,37 +815,37 @@ void nr_csi_meas_reporting(int Mod_idP,
}
}
__attribute__((unused))
static void handle_dl_harq(module_id_t mod_id,
int UE_id,
static void handle_dl_harq(NR_UE_info_t * UE,
int8_t harq_pid,
bool success)
bool success,
int harq_round_max)
{
NR_UE_info_t *UE_info = &RC.nrmac[mod_id]->UE_info;
NR_UE_harq_t *harq = &UE_info->UE_sched_ctrl[UE_id].harq_processes[harq_pid];
NR_UE_harq_t *harq = &UE->UE_sched_ctrl.harq_processes[harq_pid];
harq->feedback_slot = -1;
harq->is_waiting = false;
if (success) {
add_tail_nr_list(&UE_info->UE_sched_ctrl[UE_id].available_dl_harq, harq_pid);
add_tail_nr_list(&UE->UE_sched_ctrl.available_dl_harq, harq_pid);
harq->round = 0;
harq->ndi ^= 1;
} else if (harq->round >= RC.nrmac[mod_id]->harq_round_max - 1) {
add_tail_nr_list(&UE_info->UE_sched_ctrl[UE_id].available_dl_harq, harq_pid);
} else if (harq->round >= harq_round_max - 1) {
add_tail_nr_list(&UE->UE_sched_ctrl.available_dl_harq, harq_pid);
harq->round = 0;
harq->ndi ^= 1;
NR_mac_stats_t *stats = &UE_info->mac_stats[UE_id];
stats->dlsch_errors++;
LOG_D(NR_MAC, "retransmission error for UE %d (total %"PRIu64")\n", UE_id, stats->dlsch_errors);
NR_mac_stats_t *stats = &UE->mac_stats;
stats->dl.errors++;
LOG_D(NR_MAC, "retransmission error for UE %04x (total %"PRIu64")\n", UE->rnti, stats->dl.errors);
} else {
LOG_D(PHY,"NACK for: pid %d, ue %x\n",harq_pid, UE_id);
add_tail_nr_list(&UE_info->UE_sched_ctrl[UE_id].retrans_dl_harq, harq_pid);
LOG_D(PHY,"NACK for: pid %d, ue %04x\n",harq_pid, UE->rnti);
add_tail_nr_list(&UE->UE_sched_ctrl.retrans_dl_harq, harq_pid);
harq->round++;
}
}
int checkTargetSSBInFirst64TCIStates_pdschConfig(int ssb_index_t, int Mod_idP, int UE_id) {
NR_UE_info_t *UE_info = &RC.nrmac[Mod_idP]->UE_info;
NR_CellGroupConfig_t *CellGroup = UE_info->CellGroup[UE_id] ;
int checkTargetSSBInFirst64TCIStates_pdschConfig(int ssb_index_t, NR_UE_info_t * UE) {
NR_CellGroupConfig_t *CellGroup = UE->CellGroup;
int nb_tci_states = CellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list.count;
NR_TCI_State_t *tci =NULL;
int i;
@@ -874,13 +870,12 @@ int checkTargetSSBInFirst64TCIStates_pdschConfig(int ssb_index_t, int Mod_idP, i
return -1;
}
int checkTargetSSBInTCIStates_pdcchConfig(int ssb_index_t, int Mod_idP, int UE_id) {
NR_UE_info_t *UE_info = &RC.nrmac[Mod_idP]->UE_info;
NR_CellGroupConfig_t *CellGroup = UE_info->CellGroup[UE_id] ;
int checkTargetSSBInTCIStates_pdcchConfig(int ssb_index_t, NR_UE_info_t *UE) {
NR_CellGroupConfig_t *CellGroup = UE->CellGroup ;
int nb_tci_states = CellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->tci_StatesToAddModList->list.count;
NR_TCI_State_t *tci =NULL;
NR_TCI_StateId_t *tci_id = NULL;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_ControlResourceSet_t *coreset = sched_ctrl->coreset;
int i;
int flag = 0;
@@ -935,7 +930,7 @@ int get_diff_rsrp(uint8_t index, int strongest_rsrp) {
//identifies the target SSB Beam index
//keeps the required date for PDCCH and PDSCH TCI state activation/deactivation CE consutruction globally
//handles triggering of PDCCH and PDSCH MAC CEs
void tci_handling(module_id_t Mod_idP, int UE_id, frame_t frame, slot_t slot) {
void tci_handling(NR_UE_info_t *UE, frame_t frame, slot_t slot) {
int strongest_ssb_rsrp = 0;
int cqi_idx = 0;
@@ -947,10 +942,10 @@ void tci_handling(module_id_t Mod_idP, int UE_id, frame_t frame, slot_t slot) {
int ssb_index[MAX_NUM_SSB] = {0};
int ssb_rsrp[MAX_NUM_SSB] = {0};
uint8_t idx = 0;
NR_UE_info_t *UE_info = &RC.nrmac[Mod_idP]->UE_info;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
const int bwp_id = sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0;
NR_CellGroupConfig_t *CellGroup = UE_info->CellGroup[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
const int bwp_id = sched_ctrl->active_bwp ? 1 : 0;
NR_CellGroupConfig_t *CellGroup = UE->CellGroup;
//bwp indicator
int n_dl_bwp=0;
@@ -960,7 +955,7 @@ void tci_handling(module_id_t Mod_idP, int UE_id, frame_t frame, slot_t slot) {
n_dl_bwp = CellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count;
uint8_t nr_ssbri_cri = 0;
uint8_t nb_of_csi_ssb_report = UE_info->csi_report_template[UE_id][cqi_idx].nb_of_csi_ssb_report;
uint8_t nb_of_csi_ssb_report = UE->csi_report_template[cqi_idx].nb_of_csi_ssb_report;
int better_rsrp_reported = -140-(-0); /*minimum_measured_RSRP_value - minimum_differntail_RSRP_value*///considering the minimum RSRP value as better RSRP initially
uint8_t diff_rsrp_idx = 0;
uint8_t i, j;
@@ -1031,7 +1026,7 @@ void tci_handling(module_id_t Mod_idP, int UE_id, frame_t frame, slot_t slot) {
The length of the field is 7 bits
*/
if(sched_ctrl->UE_mac_ce_ctrl.pdcch_state_ind.coresetId == 0) {
int tci_state_id = checkTargetSSBInFirst64TCIStates_pdschConfig(ssb_index[target_ssb_beam_index], Mod_idP, UE_id);
int tci_state_id = checkTargetSSBInFirst64TCIStates_pdschConfig(ssb_index[target_ssb_beam_index], UE);
if( tci_state_id != -1)
sched_ctrl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId = tci_state_id;
@@ -1041,7 +1036,7 @@ void tci_handling(module_id_t Mod_idP, int UE_id, frame_t frame, slot_t slot) {
int flag = 0;
for(i =0; ssb_index_sorted[i]!=0; i++) {
tci_state_id = checkTargetSSBInFirst64TCIStates_pdschConfig(ssb_index_sorted[i], Mod_idP, UE_id) ;
tci_state_id = checkTargetSSBInFirst64TCIStates_pdschConfig(ssb_index_sorted[i],UE) ;
if(tci_state_id != -1 && ssb_rsrp_sorted[i] > ssb_rsrp[curr_ssb_beam_index] && ssb_rsrp_sorted[i] - ssb_rsrp[curr_ssb_beam_index] > L1_RSRP_HYSTERIS) {
sched_ctrl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId = tci_state_id;
@@ -1055,7 +1050,7 @@ void tci_handling(module_id_t Mod_idP, int UE_id, frame_t frame, slot_t slot) {
}
}
} else {
int tci_state_id = checkTargetSSBInTCIStates_pdcchConfig(ssb_index[target_ssb_beam_index], Mod_idP, UE_id);
int tci_state_id = checkTargetSSBInTCIStates_pdcchConfig(ssb_index[target_ssb_beam_index], UE);
if (tci_state_id !=-1)
sched_ctrl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId = tci_state_id;
@@ -1065,7 +1060,7 @@ void tci_handling(module_id_t Mod_idP, int UE_id, frame_t frame, slot_t slot) {
int flag = 0;
for(i =0; ssb_index_sorted[i]!=0; i++) {
tci_state_id = checkTargetSSBInTCIStates_pdcchConfig(ssb_index_sorted[i], Mod_idP, UE_id);
tci_state_id = checkTargetSSBInTCIStates_pdcchConfig(ssb_index_sorted[i], UE);
if( tci_state_id != -1 && ssb_rsrp_sorted[i] > ssb_rsrp[curr_ssb_beam_index] && ssb_rsrp_sorted[i] - ssb_rsrp[curr_ssb_beam_index] > L1_RSRP_HYSTERIS) {
sched_ctrl->UE_mac_ce_ctrl.pdcch_state_ind.tciStateId = tci_state_id;
@@ -1126,15 +1121,14 @@ uint8_t pickandreverse_bits(uint8_t *payload, uint16_t bitlen, uint8_t start_bit
}
void evaluate_rsrp_report(NR_UE_info_t *UE_info,
void evaluate_rsrp_report(NR_UE_info_t *UE,
NR_UE_sched_ctrl_t *sched_ctrl,
int UE_id,
uint8_t csi_report_id,
uint8_t *payload,
int *cumul_bits,
NR_CSI_ReportConfig__reportQuantity_PR reportQuantity_type){
nr_csi_report_t *csi_report = &UE_info->csi_report_template[UE_id][csi_report_id];
nr_csi_report_t *csi_report = &UE->csi_report_template[csi_report_id];
uint8_t cri_ssbri_bitlen = csi_report->CSI_report_bitlen.cri_ssbri_bitlen;
uint16_t curr_payload;
@@ -1186,7 +1180,7 @@ void evaluate_rsrp_report(NR_UE_info_t *UE_info,
}
csi_report->nb_of_csi_ssb_report++;
int strongest_ssb_rsrp = get_measured_rsrp(sched_ctrl->CSI_report.ssb_cri_report.RSRP);
NR_mac_stats_t *stats = &UE_info->mac_stats[UE_id];
NR_mac_stats_t *stats = &UE->mac_stats;
// including ssb rsrp in mac stats
stats->cumul_rsrp += strongest_ssb_rsrp;
stats->num_rsrp_meas++;
@@ -1250,7 +1244,12 @@ void evaluate_cqi_report(uint8_t *payload,
sched_ctrl->CSI_report.cri_ri_li_pmi_cqi_report.wb_cqi_2tb = temp_cqi;
LOG_D(MAC,"Wide-band CQI for the second TB %d\n", temp_cqi);
}
sched_ctrl->set_mcs = true;
// TODO for wideband case and multiple TB
const int cqi_idx = sched_ctrl->CSI_report.cri_ri_li_pmi_cqi_report.wb_cqi_1tb;
const int mcs_table = sched_ctrl->pdsch_semi_static.mcsTableIdx;
const int cqi_table = sched_ctrl->CSI_report.cri_ri_li_pmi_cqi_report.cqi_table;
sched_ctrl->dl_max_mcs = get_mcs_from_cqi(mcs_table, cqi_table, cqi_idx);
}
@@ -1319,22 +1318,19 @@ void extract_pucch_csi_report(NR_CSI_MeasConfig_t *csi_MeasConfig,
const nfapi_nr_uci_pucch_pdu_format_2_3_4_t *uci_pdu,
frame_t frame,
slot_t slot,
int UE_id,
module_id_t Mod_idP) {
NR_UE_info_t *UE,
NR_ServingCellConfigCommon_t *scc)
{
/** From Table 6.3.1.1.2-3: RI, LI, CQI, and CRI of codebookType=typeI-SinglePanel */
NR_ServingCellConfigCommon_t *scc =
RC.nrmac[Mod_idP]->common_channels->ServingCellConfigCommon;
const int n_slots_frame = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
uint8_t *payload = uci_pdu->csi_part1.csi_part1_payload;
uint16_t bitlen = uci_pdu->csi_part1.csi_part1_bit_len;
NR_CSI_ReportConfig__reportQuantity_PR reportQuantity_type = NR_CSI_ReportConfig__reportQuantity_PR_NOTHING;
NR_UE_info_t *UE_info = &(RC.nrmac[Mod_idP]->UE_info);
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
int cumul_bits = 0;
int r_index = -1;
for (int csi_report_id = 0; csi_report_id < csi_MeasConfig->csi_ReportConfigToAddModList->list.count; csi_report_id++ ) {
nr_csi_report_t *csi_report = &UE_info->csi_report_template[UE_id][csi_report_id];
nr_csi_report_t *csi_report = &UE->csi_report_template[csi_report_id];
csi_report->nb_of_csi_ssb_report = 0;
uint8_t cri_bitlen = 0;
uint8_t ri_bitlen = 0;
@@ -1349,10 +1345,10 @@ void extract_pucch_csi_report(NR_CSI_MeasConfig_t *csi_MeasConfig,
LOG_D(MAC,"SFN/SF:%d/%d reportQuantity type = %d\n",frame,slot,reportQuantity_type);
switch(reportQuantity_type){
case NR_CSI_ReportConfig__reportQuantity_PR_cri_RSRP:
evaluate_rsrp_report(UE_info,sched_ctrl,UE_id,csi_report_id,payload,&cumul_bits,reportQuantity_type);
evaluate_rsrp_report(UE,sched_ctrl,csi_report_id,payload,&cumul_bits,reportQuantity_type);
break;
case NR_CSI_ReportConfig__reportQuantity_PR_ssb_Index_RSRP:
evaluate_rsrp_report(UE_info,sched_ctrl,UE_id,csi_report_id,payload,&cumul_bits,reportQuantity_type);
evaluate_rsrp_report(UE,sched_ctrl,csi_report_id,payload,&cumul_bits,reportQuantity_type);
break;
case NR_CSI_ReportConfig__reportQuantity_PR_cri_RI_CQI:
cri_bitlen = csi_report->csi_meas_bitlen.cri_bitlen;
@@ -1408,7 +1404,7 @@ void extract_pucch_csi_report(NR_CSI_MeasConfig_t *csi_MeasConfig,
}
}
static NR_UE_harq_t *find_harq(module_id_t mod_id, frame_t frame, sub_frame_t slot, int UE_id)
static NR_UE_harq_t *find_harq(frame_t frame, sub_frame_t slot, NR_UE_info_t * UE, int harq_round_max)
{
/* In case of realtime problems: we can only identify a HARQ process by
* timing. If the HARQ process's feedback_frame/feedback_slot is not the one we
@@ -1416,7 +1412,7 @@ static NR_UE_harq_t *find_harq(module_id_t mod_id, frame_t frame, sub_frame_t sl
* skip this HARQ process, which is what happens in the loop below.
* Similarly, we might be "in advance", in which case we need to skip
* this result. */
NR_UE_sched_ctrl_t *sched_ctrl = &RC.nrmac[mod_id]->UE_info.UE_sched_ctrl[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
int8_t pid = sched_ctrl->feedback_dl_harq.head;
if (pid < 0)
return NULL;
@@ -1432,7 +1428,7 @@ static NR_UE_harq_t *find_harq(module_id_t mod_id, frame_t frame, sub_frame_t sl
frame,
slot);
remove_front_nr_list(&sched_ctrl->feedback_dl_harq);
handle_dl_harq(mod_id, UE_id, pid, 0);
handle_dl_harq(UE, pid, 0, harq_round_max);
pid = sched_ctrl->feedback_dl_harq.head;
if (pid < 0)
return NULL;
@@ -1457,20 +1453,19 @@ void handle_nr_uci_pucch_0_1(module_id_t mod_id,
sub_frame_t slot,
const nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_01)
{
int UE_id = find_nr_UE_id(mod_id, uci_01->rnti);
if (UE_id < 0) {
NR_UE_info_t * UE = find_nr_UE(&RC.nrmac[mod_id]->UE_info, uci_01->rnti);
if (!UE) {
LOG_E(NR_MAC, "%s(): unknown RNTI %04x in PUCCH UCI\n", __func__, uci_01->rnti);
return;
}
NR_UE_info_t *UE_info = &RC.nrmac[mod_id]->UE_info;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
if (((uci_01->pduBitmap >> 1) & 0x01)) {
// iterate over received harq bits
for (int harq_bit = 0; harq_bit < uci_01->harq->num_harq; harq_bit++) {
const uint8_t harq_value = uci_01->harq->harq_list[harq_bit].harq_value;
const uint8_t harq_confidence = uci_01->harq->harq_confidence_level;
NR_UE_harq_t *harq = find_harq(mod_id, frame, slot, UE_id);
NR_UE_harq_t *harq = find_harq(frame, slot, UE, RC.nrmac[mod_id]->harq_round_max);
if (!harq) {
LOG_E(NR_MAC, "Oh no! Could not find a harq in %s!\n", __FUNCTION__);
break;
@@ -1479,8 +1474,8 @@ void handle_nr_uci_pucch_0_1(module_id_t mod_id,
const int8_t pid = sched_ctrl->feedback_dl_harq.head;
remove_front_nr_list(&sched_ctrl->feedback_dl_harq);
LOG_D(NR_MAC,"%4d.%2d bit %d pid %d ack/nack %d\n",frame, slot, harq_bit,pid,harq_value);
handle_dl_harq(mod_id, UE_id, pid, harq_value == 0 && harq_confidence == 0);
if (harq_confidence == 1) UE_info->mac_stats[UE_id].pucch0_DTX++;
handle_dl_harq(UE, pid, harq_value == 0 && harq_confidence == 0, RC.nrmac[mod_id]->harq_round_max);
if (harq_confidence == 1) UE->mac_stats.pucch0_DTX++;
}
}
@@ -1505,19 +1500,21 @@ void handle_nr_uci_pucch_2_3_4(module_id_t mod_id,
sub_frame_t slot,
const nfapi_nr_uci_pucch_pdu_format_2_3_4_t *uci_234)
{
int UE_id = find_nr_UE_id(mod_id, uci_234->rnti);
if (UE_id < 0) {
NR_UE_info_t * UE = find_nr_UE(&RC.nrmac[mod_id]->UE_info, uci_234->rnti);
if (!UE) {
LOG_E(NR_MAC, "%s(): unknown RNTI %04x in PUCCH UCI\n", __func__, uci_234->rnti);
return;
}
AssertFatal(RC.nrmac[mod_id]->UE_info.CellGroup[UE_id],"Cellgroup is null for UE %d/%x\n",UE_id,uci_234->rnti);
AssertFatal(RC.nrmac[mod_id]->UE_info.CellGroup[UE_id]->spCellConfig, "Cellgroup->spCellConfig is null for UE %d/%x\n",UE_id,uci_234->rnti);
AssertFatal(RC.nrmac[mod_id]->UE_info.CellGroup[UE_id]->spCellConfig->spCellConfigDedicated, "Cellgroup->spCellConfig->spCellConfigDedicated is null for UE %d/%x\n",UE_id,uci_234->rnti);
if ( RC.nrmac[mod_id]->UE_info.CellGroup[UE_id]->spCellConfig->spCellConfigDedicated->csi_MeasConfig==NULL) return;
AssertFatal(UE->CellGroup,"Cellgroup is null for UE %04x\n", uci_234->rnti);
AssertFatal(UE->CellGroup->spCellConfig,
"Cellgroup->spCellConfig is null for UE %04x\n", uci_234->rnti);
AssertFatal(UE->CellGroup->spCellConfig->spCellConfigDedicated,
"Cellgroup->spCellConfig->spCellConfigDedicated is null for UE %04x\n", uci_234->rnti);
if ( UE->CellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig==NULL)
return;
NR_CSI_MeasConfig_t *csi_MeasConfig = RC.nrmac[mod_id]->UE_info.CellGroup[UE_id]->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup;
NR_UE_info_t *UE_info = &RC.nrmac[mod_id]->UE_info;
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_CSI_MeasConfig_t *csi_MeasConfig = UE->CellGroup->spCellConfig->spCellConfigDedicated->csi_MeasConfig->choice.setup;
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
// tpc (power control)
// TODO PUCCH2 SNR computation is not correct -> ignore the following
@@ -1530,20 +1527,20 @@ void handle_nr_uci_pucch_2_3_4(module_id_t mod_id,
// iterate over received harq bits
for (int harq_bit = 0; harq_bit < uci_234->harq.harq_bit_len; harq_bit++) {
const int acknack = ((uci_234->harq.harq_payload[harq_bit >> 3]) >> harq_bit) & 0x01;
NR_UE_harq_t *harq = find_harq(mod_id, frame, slot, UE_id);
NR_UE_harq_t *harq = find_harq(frame, slot, UE, RC.nrmac[mod_id]->harq_round_max);
if (!harq)
break;
DevAssert(harq->is_waiting);
const int8_t pid = sched_ctrl->feedback_dl_harq.head;
remove_front_nr_list(&sched_ctrl->feedback_dl_harq);
handle_dl_harq(mod_id, UE_id, pid, uci_234->harq.harq_crc != 1 && acknack);
handle_dl_harq(UE, pid, uci_234->harq.harq_crc != 1 && acknack, RC.nrmac[mod_id]->harq_round_max);
}
}
if ((uci_234->pduBitmap >> 2) & 0x01) {
//API to parse the csi report and store it into sched_ctrl
extract_pucch_csi_report(csi_MeasConfig, uci_234, frame, slot, UE_id, mod_id);
extract_pucch_csi_report(csi_MeasConfig, uci_234, frame, slot, UE, RC.nrmac[mod_id]->common_channels->ServingCellConfigCommon);
//TCI handling function
tci_handling(mod_id, UE_id,frame, slot);
tci_handling(UE,frame, slot);
}
if ((uci_234->pduBitmap >> 3) & 0x01) {
//@TODO:Handle CSI Report 2
@@ -1611,12 +1608,11 @@ bool test_acknack_vrb_occupation(NR_UE_sched_ctrl_t *sched_ctrl,
// if the function returns -1 it was not possible to schedule acknack
// when current pucch is ready to be scheduled nr_fill_nfapi_pucch is called
int nr_acknack_scheduling(int mod_id,
int UE_id,
NR_UE_info_t * UE,
frame_t frame,
sub_frame_t slot,
int r_pucch,
int is_common) {
const int CC_id = 0;
const int minfbtime = RC.nrmac[mod_id]->minRXTXTIMEpdsch;
const NR_ServingCellConfigCommon_t *scc = RC.nrmac[mod_id]->common_channels[CC_id].ServingCellConfigCommon;
@@ -1634,8 +1630,8 @@ int nr_acknack_scheduling(int mod_id,
* * SR uses format 0 and is allocated in the first UL (mixed) slot (and not
* later)
* * each UE has dedicated PUCCH Format 0 resources, and we use index 0! */
NR_UE_sched_ctrl_t *sched_ctrl = &RC.nrmac[mod_id]->UE_info.UE_sched_ctrl[UE_id];
NR_CellGroupConfig_t *cg = RC.nrmac[mod_id]->UE_info.CellGroup[UE_id];
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_CellGroupConfig_t *cg = UE->CellGroup;
NR_PUCCH_Config_t *pucch_Config = NULL;
if (sched_ctrl->active_ubwp) {
@@ -1670,11 +1666,13 @@ int nr_acknack_scheduling(int mod_id,
const int f = pucch->frame;
const int s = pucch->ul_slot;
LOG_D(NR_MAC, "In %s: %4d.%2d DAI = 2 pucch currently in %4d.%2d, advancing by 1 slot\n", __FUNCTION__, frame, slot, f, s);
if (!(csi_pucch
&& csi_pucch->csi_bits > 0
&& csi_pucch->frame == f
&& csi_pucch->ul_slot == s))
nr_fill_nfapi_pucch(mod_id, frame, slot, pucch, UE_id);
if (!(csi_pucch
&& csi_pucch->csi_bits > 0
&& csi_pucch->frame == f
&& csi_pucch->ul_slot == s))
nr_fill_nfapi_pucch(RC.nrmac[mod_id], frame, slot, pucch, UE);
memset(pucch, 0, sizeof(*pucch));
pucch->frame = s == n_slots_frame - 1 ? (f + 1) % 1024 : f;
if(((s + 1)%nr_slots_period) == 0)
@@ -1691,7 +1689,8 @@ int nr_acknack_scheduling(int mod_id,
&& csi_pucch->ul_slot == pucch->ul_slot
&& !csi_pucch->simultaneous_harqcsi) {
LOG_D(NR_MAC,"Cannot multiplex csi_pucch for %d.%d\n",csi_pucch->frame,csi_pucch->ul_slot);
nr_fill_nfapi_pucch(mod_id, frame, slot, csi_pucch, UE_id);
nr_fill_nfapi_pucch(RC.nrmac[mod_id], frame, slot, csi_pucch, UE);
memset(csi_pucch, 0, sizeof(*csi_pucch));
pucch->frame = pucch->ul_slot == n_slots_frame - 1 ? (pucch->frame + 1) % 1024 : pucch->frame;
if(((pucch->ul_slot + 1)%nr_slots_period) == 0)
@@ -1718,7 +1717,7 @@ int nr_acknack_scheduling(int mod_id,
const int bwp_id = sched_ctrl->active_bwp ? sched_ctrl->active_bwp->bwp_Id : 0;
int max_fb_time = 0;
get_pdsch_to_harq_feedback(mod_id, UE_id, bwp_id, ss_type, &max_fb_time, pdsch_to_harq_feedback);
get_pdsch_to_harq_feedback(UE, bwp_id, ss_type, &max_fb_time, pdsch_to_harq_feedback);
LOG_D(NR_MAC, "In %s: 1b. DL %4d.%2d, UL_ACK %4d.%2d, DAI_C %d\n", __FUNCTION__, frame,slot,pucch->frame,pucch->ul_slot,pucch->dai_c);
/* there is a HARQ. Check whether we can use it for this ACKNACK */
@@ -1745,14 +1744,14 @@ int nr_acknack_scheduling(int mod_id,
csi_pucch->csi_bits > 0 &&
csi_pucch->frame == f &&
csi_pucch->ul_slot == s))
nr_fill_nfapi_pucch(mod_id, frame, slot, pucch, UE_id);
nr_fill_nfapi_pucch(RC.nrmac[mod_id], frame, slot, pucch, UE);
memset(pucch, 0, sizeof(*pucch));
pucch->frame = s == n_slots_frame - 1 ? (f + 1) % 1024 : f;
if(((s + 1)%nr_slots_period) == 0)
pucch->ul_slot = (s + 1 + first_ul_slot_period) % n_slots_frame;
else
pucch->ul_slot = (s + 1) % n_slots_frame;
return nr_acknack_scheduling(mod_id, UE_id, frame, slot, r_pucch,is_common);
return nr_acknack_scheduling(mod_id, UE, frame, slot, r_pucch,is_common);
}
pucch->timing_indicator = i;
@@ -1778,10 +1777,11 @@ int nr_acknack_scheduling(int mod_id,
((pucch->frame*n_slots_frame + pucch->ul_slot) <
(frame*n_slots_frame + slot))) {
AssertFatal(pucch->sr_flag + pucch->dai_c == 0,
"expected no SR/AckNack for UE %d in %4d.%2d, but has %d/%d for %4d.%2d\n",
UE_id, frame, slot, pucch->sr_flag, pucch->dai_c, pucch->frame, pucch->ul_slot);
"expected no SR/AckNack for UE %04x in %4d.%2d, but has %d/%d for %4d.%2d\n",
UE->rnti, frame, slot, pucch->sr_flag, pucch->dai_c, pucch->frame, pucch->ul_slot);
const int s = next_ul_slot;
pucch->frame = s < n_slots_frame ? frame : (frame + 1) % 1024;
pucch->ul_slot = s % n_slots_frame;
}
@@ -1829,11 +1829,11 @@ int nr_acknack_scheduling(int mod_id,
}
if (ind_found==-1) {
LOG_D(NR_MAC,
"%4d.%2d could not find pdsch_to_harq_feedback for UE %d: earliest "
"%4d.%2d could not find pdsch_to_harq_feedback for UE %04x: earliest "
"ack slot %d\n",
frame,
slot,
UE_id,
UE->rnti,
pucch->ul_slot);
return -1;
}
@@ -1847,8 +1847,9 @@ int nr_acknack_scheduling(int mod_id,
// FIXME currently we support at most 11 bits in pucch2 so skip also in that case
if(!csi_pucch->simultaneous_harqcsi
|| ((csi_pucch->csi_bits + csi_pucch->dai_c) >= 11)) {
LOG_D(NR_MAC,"Cannot multiplex csi_pucch %d +csi_pucch->dai_c %d for %d.%d\n",csi_pucch->csi_bits,csi_pucch->dai_c,csi_pucch->frame,csi_pucch->ul_slot);
nr_fill_nfapi_pucch(mod_id, frame, slot, csi_pucch, UE_id);
nr_fill_nfapi_pucch(RC.nrmac[mod_id], frame, slot, csi_pucch, UE);
memset(csi_pucch, 0, sizeof(*csi_pucch));
/* advance the UL slot information in PUCCH by one so we won't schedule in
* the same slot again */
@@ -1860,7 +1861,7 @@ int nr_acknack_scheduling(int mod_id,
pucch->ul_slot = (s + 1 + first_ul_slot_period) % n_slots_frame;
else
pucch->ul_slot = (s + 1) % n_slots_frame;
return nr_acknack_scheduling(mod_id, UE_id, frame, slot, r_pucch,is_common);
return nr_acknack_scheduling(mod_id, UE, frame, slot, r_pucch,is_common);
}
// multiplexing harq and csi in a pucch
else {
@@ -1897,29 +1898,26 @@ int nr_acknack_scheduling(int mod_id,
}
void nr_sr_reporting(int Mod_idP, frame_t SFN, sub_frame_t slot)
void nr_sr_reporting(gNB_MAC_INST *nrmac, frame_t SFN, sub_frame_t slot)
{
gNB_MAC_INST *nrmac = RC.nrmac[Mod_idP];
if (!is_xlsch_in_slot(nrmac->ulsch_slot_bitmap[slot / 64], slot))
return;
NR_ServingCellConfigCommon_t *scc = nrmac->common_channels->ServingCellConfigCommon;
const int n_slots_frame = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
NR_UE_info_t *UE_info = &nrmac->UE_info;
NR_list_t *UE_list = &UE_info->list;
for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
UE_iterator(nrmac->UE_info.list, UE) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
if (sched_ctrl->ul_failure==1 || sched_ctrl->rrc_processing_timer>0) continue;
NR_PUCCH_Config_t *pucch_Config = NULL;
if (sched_ctrl->active_ubwp) {
pucch_Config = sched_ctrl->active_ubwp->bwp_Dedicated->pucch_Config->choice.setup;
} else if (RC.nrmac[Mod_idP]->UE_info.CellGroup[UE_id] &&
RC.nrmac[Mod_idP]->UE_info.CellGroup[UE_id]->spCellConfig &&
RC.nrmac[Mod_idP]->UE_info.CellGroup[UE_id]->spCellConfig->spCellConfigDedicated &&
RC.nrmac[Mod_idP]->UE_info.CellGroup[UE_id]->spCellConfig->spCellConfigDedicated->uplinkConfig &&
RC.nrmac[Mod_idP]->UE_info.CellGroup[UE_id]->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP &&
RC.nrmac[Mod_idP]->UE_info.CellGroup[UE_id]->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP->pucch_Config->choice.setup) {
pucch_Config = RC.nrmac[Mod_idP]->UE_info.CellGroup[UE_id]->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP->pucch_Config->choice.setup;
} else if (UE->CellGroup &&
UE->CellGroup->spCellConfig &&
UE->CellGroup->spCellConfig->spCellConfigDedicated &&
UE->CellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig &&
UE->CellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP &&
UE->CellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP->pucch_Config->choice.setup) {
pucch_Config = UE->CellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->initialUplinkBWP->pucch_Config->choice.setup;
}
else continue;
@@ -1966,7 +1964,7 @@ void nr_sr_reporting(int Mod_idP, frame_t SFN, sub_frame_t slot)
continue;
nfapi_nr_pucch_pdu_t *pdu = &ul_tti_req->pdus_list[i].pucch_pdu;
/* check that it is our PUCCH F0. Assuming there can be only one */
if (pdu->rnti == UE_info->rnti[UE_id]
if (pdu->rnti == UE->rnti
&& pdu->format_type == 0 // does not use NR_PUCCH_Resource__format_PR_format0
&& pdu->initial_cyclic_shift == pucch_res->format.choice.format0->initialCyclicShift
&& pdu->nr_of_symbols == pucch_res->format.choice.format0->nrofSymbols
@@ -1976,7 +1974,7 @@ void nr_sr_reporting(int Mod_idP, frame_t SFN, sub_frame_t slot)
nfapi_allocated = true;
break;
}
else if (pdu->rnti == UE_info->rnti[UE_id]
else if (pdu->rnti == UE->rnti
&& pdu->format_type == 2 // does not use NR_PUCCH_Resource__format_PR_format0
&& pdu->nr_of_symbols == pucch_res->format.choice.format2->nrofSymbols
&& pdu->start_symbol_index == pucch_res->format.choice.format2->startingSymbolIndex) {
@@ -1986,7 +1984,7 @@ void nr_sr_reporting(int Mod_idP, frame_t SFN, sub_frame_t slot)
break;
}
else if (pdu->rnti == UE_info->rnti[UE_id]
else if (pdu->rnti == UE->rnti
&& pdu->format_type == 1 // does not use NR_PUCCH_Resource__format_PR_format0
&& pdu->nr_of_symbols == pucch_res->format.choice.format1->nrofSymbols
&& pdu->start_symbol_index == pucch_res->format.choice.format1->startingSymbolIndex) {
@@ -1996,7 +1994,7 @@ void nr_sr_reporting(int Mod_idP, frame_t SFN, sub_frame_t slot)
break;
}
else if (pdu->rnti == UE_info->rnti[UE_id]
else if (pdu->rnti == UE->rnti
&& pdu->format_type == 3 // does not use NR_PUCCH_Resource__format_PR_format0
&& pdu->nr_of_symbols == pucch_res->format.choice.format3->nrofSymbols
&& pdu->start_symbol_index == pucch_res->format.choice.format3->startingSymbolIndex) {
@@ -2006,7 +2004,7 @@ void nr_sr_reporting(int Mod_idP, frame_t SFN, sub_frame_t slot)
break;
}
else if (pdu->rnti == UE_info->rnti[UE_id]
else if (pdu->rnti == UE->rnti
&& pdu->format_type == 4 // does not use NR_PUCCH_Resource__format_PR_format0
&& pdu->nr_of_symbols == pucch_res->format.choice.format4->nrofSymbols
&& pdu->start_symbol_index == pucch_res->format.choice.format4->startingSymbolIndex) {
@@ -2038,7 +2036,7 @@ void nr_sr_reporting(int Mod_idP, frame_t SFN, sub_frame_t slot)
.resource_indicator = found,
.r_pucch = -1
};
nr_fill_nfapi_pucch(Mod_idP, SFN, slot, &sched_sr, UE_id);
nr_fill_nfapi_pucch(nrmac, SFN, slot, &sched_sr, UE);
}
}
}
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
+235 -356
View File
File diff suppressed because it is too large Load Diff
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+20 -26
View File
@@ -203,7 +203,7 @@ void config_uldci(const NR_SIB1_t *sib1,
int n_ubwp,
int bwp_id);
void nr_schedule_pucch(int Mod_idP,
void nr_schedule_pucch(gNB_MAC_INST* nrmac,
frame_t frameP,
sub_frame_t slotP);
@@ -218,15 +218,14 @@ void nr_csi_meas_reporting(int Mod_idP,
frame_t frameP,
sub_frame_t slotP);
int nr_acknack_scheduling(int Mod_idP,
int UE_id,
int nr_acknack_scheduling( int Mod_idP,
NR_UE_info_t * UE,
frame_t frameP,
sub_frame_t slotP,
int r_pucch,
int do_common);
void get_pdsch_to_harq_feedback(int Mod_idP,
int UE_id,
void get_pdsch_to_harq_feedback(NR_UE_info_t *,
int bwp_id,
NR_SearchSpace__searchSpaceType_PR ss_type,
int *max_fb_time,
@@ -336,7 +335,7 @@ NR_PDSCH_TimeDomainResourceAllocationList_t *get_pdsch_TimeDomainAllocationList(
const NR_SIB1_t *sib1);
/* find coreset within the search space */
NR_ControlResourceSet_t *get_coreset(module_id_t module_idP,
NR_ControlResourceSet_t *get_coreset(gNB_MAC_INST *nrmac,
NR_ServingCellConfigCommon_t *scc,
void *bwp,
NR_SearchSpace_t *ss,
@@ -388,20 +387,12 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu,
int x_overhead,
uint8_t numdmrscdmgroupnodata,
uint8_t tb_scaling);
/** \brief Computes Q based on I_MCS PDSCH and table_idx for downlink. Implements MCS Tables from 38.214. */
uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx);
uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx);
/** \brief Computes Q based on I_MCS PDSCH and table_idx for uplink. Implements MCS Tables from 38.214. */
uint8_t nr_get_Qm_ul(uint8_t Imcs, uint8_t table_idx);
uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx);
int NRRIV2BW(int locationAndBandwidth,int N_RB);
int NRRIV2PRBOFFSET(int locationAndBandwidth,int N_RB);
/* Functions to manage an NR_list_t */
void dump_nr_list(NR_list_t *listP);
void create_nr_list(NR_list_t *listP, int len);
void resize_nr_list(NR_list_t *list, int new_len);
void destroy_nr_list(NR_list_t *list);
@@ -411,13 +402,13 @@ void add_tail_nr_list(NR_list_t *listP, int id);
void add_front_nr_list(NR_list_t *listP, int id);
void remove_front_nr_list(NR_list_t *listP);
int find_nr_UE_id(module_id_t mod_idP, rnti_t rntiP);
NR_UE_info_t * find_nr_UE(NR_UEs_t* UEs, rnti_t rntiP);
int find_nr_RA_id(module_id_t mod_idP, int CC_idP, rnti_t rntiP);
int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP, NR_CellGroupConfig_t *CellGroup);
NR_UE_info_t*add_new_nr_ue(gNB_MAC_INST *nr_mac, rnti_t rntiP, NR_CellGroupConfig_t *CellGroup);
void mac_remove_nr_ue(module_id_t mod_id, rnti_t rnti);
void mac_remove_nr_ue(gNB_MAC_INST *nr_mac, rnti_t rnti);
void nr_mac_remove_ra_rnti(module_id_t mod_id, rnti_t rnti);
@@ -431,7 +422,7 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
int nr_get_default_pucch_res(int pucch_ResourceCommon);
void compute_csi_bitlen(NR_CSI_MeasConfig_t *csi_MeasConfig, NR_UE_info_t *UE_info, int UE_id, module_id_t Mod_idP);
void compute_csi_bitlen(NR_CSI_MeasConfig_t *csi_MeasConfig, NR_UE_info_t *UE);
int get_dlscs(nfapi_nr_config_request_t *cfg);
@@ -514,18 +505,15 @@ uint16_t set_pm_index(NR_UE_sched_ctrl_t *sched_ctrl,
int xp_pdsch_antenna_ports,
int codebook_mode);
void set_dl_mcs(NR_sched_pdsch_t *sched_pdsch,
NR_UE_sched_ctrl_t *sched_ctrl,
uint8_t *target_mcs,
uint8_t mcs_table_idx);
uint8_t get_mcs_from_cqi(int mcs_table, int cqi_table, int cqi_idx);
uint8_t set_dl_nrOfLayers(NR_UE_sched_ctrl_t *sched_ctrl);
int get_dci_format(NR_UE_sched_ctrl_t *sched_ctrl);
void calculate_preferred_dl_tda(module_id_t module_id, const NR_BWP_Downlink_t *bwp);
void calculate_preferred_ul_tda(module_id_t module_id, const NR_BWP_Uplink_t *ubwp);
const int get_dl_tda(const gNB_MAC_INST *nrmac, const NR_ServingCellConfigCommon_t *scc, int slot);
const int get_ul_tda(const gNB_MAC_INST *nrmac, const NR_ServingCellConfigCommon_t *scc, int slot);
bool find_free_CCE(module_id_t module_id, sub_frame_t slot, int UE_id);
bool find_free_CCE(sub_frame_t slot, NR_UE_info_t *UE);
bool nr_find_nb_rb(uint16_t Qm,
uint16_t R,
@@ -538,7 +526,13 @@ bool nr_find_nb_rb(uint16_t Qm,
uint32_t *tbs,
uint16_t *nb_rb);
void nr_sr_reporting(int Mod_idP, frame_t frameP, sub_frame_t slotP);
int get_mcs_from_bler(const NR_bler_options_t *bler_options,
const NR_mac_dir_stats_t *stats,
NR_bler_stats_t *bler_stats,
int max_mcs,
frame_t frame);
void nr_sr_reporting(gNB_MAC_INST *nrmac, frame_t frameP, sub_frame_t slotP);
void dump_mac_stats(gNB_MAC_INST *gNB, char *output, int strlen, bool reset_rsrp);
openair2/LAYER2/NR_MAC_gNB/main.c
+51 -53
View File
@@ -57,7 +57,7 @@ void *nrmac_stats_thread(void *arg) {
AssertFatal(fd!=NULL,"Cannot open nrMAC_stats.log, error %s\n",strerror(errno));
while (oai_exit == 0) {
dump_mac_stats(gNB,output,MACSTATSSTRLEN,false);
dump_mac_stats(gNB,output,MACSTATSSTRLEN,false);
fprintf(fd,"%s\n",output);
fflush(fd);
usleep(200000);
@@ -68,43 +68,43 @@ void *nrmac_stats_thread(void *arg) {
}
void clear_mac_stats(gNB_MAC_INST *gNB) {
memset((void*)gNB->UE_info.mac_stats,0,MAX_MOBILES_PER_GNB*sizeof(NR_mac_stats_t));
UE_iterator(gNB->UE_info.list, UE) {
memset(&UE->mac_stats,0,sizeof(UE->mac_stats));
}
}
void dump_mac_stats(gNB_MAC_INST *gNB, char *output, int strlen, bool reset_rsrp)
{
NR_UE_info_t *UE_info = &gNB->UE_info;
int num = 1;
int stroff=0;
if (UE_info->num_UEs == 0) return;
for (int UE_id = UE_info->list.head; UE_id >= 0; UE_id = UE_info->list.next[UE_id]) {
const NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
NR_mac_stats_t *stats = &UE_info->mac_stats[UE_id];
pthread_mutex_lock(&gNB->UE_info.mutex);
UE_iterator(gNB->UE_info.list, UE) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_mac_stats_t *stats = &UE->mac_stats;
const int avg_rsrp = stats->num_rsrp_meas > 0 ? stats->cumul_rsrp / stats->num_rsrp_meas : 0;
stroff+=sprintf(output+stroff,"UE ID %d RNTI %04x (%d/%d) PH %d dB PCMAX %d dBm, average RSRP %d (%d meas)\n",
UE_id,
UE_info->rnti[UE_id],
num++,
UE_info->num_UEs,
sched_ctrl->ph,
sched_ctrl->pcmax,
avg_rsrp,
stats->num_rsrp_meas);
stroff+=sprintf(output+stroff,"UE %d: CQI %d, RI %d, PMI (%d,%d)\n",
UE_id,
UE_info->UE_sched_ctrl[UE_id].CSI_report.cri_ri_li_pmi_cqi_report.wb_cqi_1tb,
UE_info->UE_sched_ctrl[UE_id].CSI_report.cri_ri_li_pmi_cqi_report.ri+1,
UE_info->UE_sched_ctrl[UE_id].CSI_report.cri_ri_li_pmi_cqi_report.pmi_x1,
UE_info->UE_sched_ctrl[UE_id].CSI_report.cri_ri_li_pmi_cqi_report.pmi_x2);
stroff+=sprintf(output+stroff,"UE %d: dlsch_rounds %"PRIu64"/%"PRIu64"/%"PRIu64"/%"PRIu64", dlsch_errors %"PRIu64", pucch0_DTX %d, BLER %.5f MCS %d\n",
UE_id,
stats->dlsch_rounds[0], stats->dlsch_rounds[1],
stats->dlsch_rounds[2], stats->dlsch_rounds[3],
stats->dlsch_errors,
stroff+=sprintf(output+stroff,"UE RNTI %04x (%d) PH %d dB PCMAX %d dBm, average RSRP %d (%d meas)\n",
UE->rnti,
num++,
sched_ctrl->ph,
sched_ctrl->pcmax,
avg_rsrp,
stats->num_rsrp_meas);
stroff+=sprintf(output+stroff,"UE %04x: CQI %d, RI %d, PMI (%d,%d)\n",
UE->rnti,
UE->UE_sched_ctrl.CSI_report.cri_ri_li_pmi_cqi_report.wb_cqi_1tb,
UE->UE_sched_ctrl.CSI_report.cri_ri_li_pmi_cqi_report.ri+1,
UE->UE_sched_ctrl.CSI_report.cri_ri_li_pmi_cqi_report.pmi_x1,
UE->UE_sched_ctrl.CSI_report.cri_ri_li_pmi_cqi_report.pmi_x2);
stroff+=sprintf(output+stroff,"UE %04x: dlsch_rounds %"PRIu64"/%"PRIu64"/%"PRIu64"/%"PRIu64", dlsch_errors %"PRIu64", pucch0_DTX %d, BLER %.5f MCS %d\n",
UE->rnti,
stats->dl.rounds[0], stats->dl.rounds[1],
stats->dl.rounds[2], stats->dl.rounds[3],
stats->dl.errors,
stats->pucch0_DTX,
sched_ctrl->dl_bler_stats.bler,
sched_ctrl->dl_bler_stats.mcs);
@@ -112,28 +112,32 @@ void dump_mac_stats(gNB_MAC_INST *gNB, char *output, int strlen, bool reset_rsrp
stats->num_rsrp_meas = 0;
stats->cumul_rsrp = 0;
}
stroff+=sprintf(output+stroff,"UE %d: dlsch_total_bytes %"PRIu64"\n", UE_id, stats->dlsch_total_bytes);
stroff+=sprintf(output+stroff,"UE %d: ulsch_rounds %"PRIu64"/%"PRIu64"/%"PRIu64"/%"PRIu64", ulsch_DTX %d, ulsch_errors %"PRIu64"\n",
UE_id,
stats->ulsch_rounds[0], stats->ulsch_rounds[1],
stats->ulsch_rounds[2], stats->ulsch_rounds[3],
stroff+=sprintf(output+stroff,"UE %04x: dlsch_total_bytes %"PRIu64"\n", UE->rnti, stats->dl.total_bytes);
stroff+=sprintf(output+stroff,"UE %04x: ulsch_rounds %"PRIu64"/%"PRIu64"/%"PRIu64"/%"PRIu64", ulsch_DTX %d, ulsch_errors %"PRIu64", BLER %.5f MCS %d\n",
UE->rnti,
stats->ul.rounds[0], stats->ul.rounds[1],
stats->ul.rounds[2], stats->ul.rounds[3],
stats->ulsch_DTX,
stats->ulsch_errors);
stats->ul.errors,
sched_ctrl->ul_bler_stats.bler,
sched_ctrl->ul_bler_stats.mcs);
stroff+=sprintf(output+stroff,
"UE %d: ulsch_total_bytes_scheduled %"PRIu64", ulsch_total_bytes_received %"PRIu64"\n",
UE_id,
stats->ulsch_total_bytes_scheduled, stats->ulsch_total_bytes_rx);
"UE %04x: ulsch_total_bytes_scheduled %"PRIu64", ulsch_total_bytes_received %"PRIu64"\n",
UE->rnti,
stats->ulsch_total_bytes_scheduled, stats->ul.total_bytes);
for (int lc_id = 0; lc_id < 63; lc_id++) {
if (stats->lc_bytes_tx[lc_id] > 0) {
stroff+=sprintf(output+stroff, "UE %d: LCID %d: %"PRIu64" bytes TX\n", UE_id, lc_id, stats->lc_bytes_tx[lc_id]);
LOG_D(NR_MAC, "UE %d: LCID %d: %"PRIu64" bytes TX\n", UE_id, lc_id, stats->lc_bytes_tx[lc_id]);
if (stats->dl.lc_bytes[lc_id] > 0) {
stroff+=sprintf(output+stroff, "UE %04x: LCID %d: %"PRIu64" bytes TX\n", UE->rnti, lc_id, stats->dl.lc_bytes[lc_id]);
LOG_D(NR_MAC, "UE %04x: LCID %d: %"PRIu64" bytes TX\n", UE->rnti, lc_id, stats->dl.lc_bytes[lc_id]);
}
if (stats->lc_bytes_rx[lc_id] > 0) {
stroff+=sprintf(output+stroff, "UE %d: LCID %d: %"PRIu64" bytes RX\n", UE_id, lc_id, stats->lc_bytes_rx[lc_id]);
LOG_D(NR_MAC, "UE %d: LCID %d: %"PRIu64" bytes RX\n", UE_id, lc_id, stats->lc_bytes_rx[lc_id]);
if (stats->ul.lc_bytes[lc_id] > 0) {
stroff+=sprintf(output+stroff, "UE %04x: LCID %d: %"PRIu64" bytes RX\n", UE->rnti, lc_id, stats->ul.lc_bytes[lc_id]);
LOG_D(NR_MAC, "UE %04x: LCID %d: %"PRIu64" bytes RX\n", UE->rnti, lc_id, stats->ul.lc_bytes[lc_id]);
}
}
}
pthread_mutex_unlock(&gNB->UE_info.mutex);
print_meas(&gNB->eNB_scheduler, "DL & UL scheduling timing stats", NULL, NULL);
print_meas(&gNB->schedule_dlsch,"dlsch scheduler",NULL,NULL);
print_meas(&gNB->rlc_data_req, "rlc_data_req",NULL,NULL);
@@ -144,8 +148,6 @@ void dump_mac_stats(gNB_MAC_INST *gNB, char *output, int strlen, bool reset_rsrp
void mac_top_init_gNB(void)
{
module_id_t i;
int list_el;
NR_UE_info_t *UE_info;
gNB_MAC_INST *nrmac;
LOG_I(MAC, "[MAIN] Init function start:nb_nr_macrlc_inst=%d\n",RC.nb_nr_macrlc_inst);
@@ -179,6 +181,8 @@ void mac_top_init_gNB(void)
RC.nrmac[i]->first_MIB = true;
pthread_mutex_init(&RC.nrmac[i]->UE_info.mutex, NULL);
if (get_softmodem_params()->phy_test) {
RC.nrmac[i]->pre_processor_dl = nr_preprocessor_phytest;
RC.nrmac[i]->pre_processor_ul = nr_ul_preprocessor_phytest;
@@ -210,13 +214,7 @@ void mac_top_init_gNB(void)
nrmac = RC.nrmac[i];
nrmac->if_inst = NR_IF_Module_init(i);
UE_info = &nrmac->UE_info;
UE_info->num_UEs = 0;
create_nr_list(&UE_info->list, MAX_MOBILES_PER_GNB);
for (list_el = 0; list_el < MAX_MOBILES_PER_GNB; list_el++) {
UE_info->active[list_el] = false;
}
memset(&nrmac->UE_info, 0, sizeof(nrmac->UE_info));
}
srand48(0);
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+52 -42
View File
@@ -91,6 +91,7 @@ typedef struct {
int len;
} NR_list_t;
typedef enum {
RA_IDLE = 0,
Msg2 = 1,
@@ -459,13 +460,12 @@ typedef struct NR_UE_harq {
//! fixme : need to enhace for the multiple TB CQI report
typedef struct NR_DL_bler_stats {
frame_t last_frame_slot;
typedef struct NR_bler_stats {
frame_t last_frame;
float bler;
float rd2_bler;
uint8_t mcs;
uint64_t dlsch_rounds[8];
} NR_DL_bler_stats_t;
uint64_t rounds[8];
} NR_bler_stats_t;
//
/*! As per spec 38.214 section 5.2.1.4.2
@@ -613,6 +613,9 @@ typedef struct {
NR_pdsch_semi_static_t pdsch_semi_static;
/// Sched PDSCH: scheduling decisions, copied into HARQ and cleared every TTI
NR_sched_pdsch_t sched_pdsch;
/// UE-estimated maximum MCS (from CSI-RS)
uint8_t dl_max_mcs;
/// For UL synchronization: store last UL scheduling grant
frame_t last_ul_frame;
sub_frame_t last_ul_slot;
@@ -624,7 +627,8 @@ typedef struct {
mac_rlc_status_resp_t rlc_status[NR_MAX_NUM_LCID];
/// Estimation of HARQ from BLER
NR_DL_bler_stats_t dl_bler_stats;
NR_bler_stats_t dl_bler_stats;
NR_bler_stats_t ul_bler_stats;
uint16_t ta_frame;
int16_t ta_update;
@@ -641,7 +645,6 @@ typedef struct {
int ul_failure;
struct CSI_Report CSI_report;
bool SR;
bool set_mcs;
bool set_pmi;
/// information about every HARQ process
NR_UE_harq_t harq_processes[NR_MAX_NB_HARQ_PROCESSES];
@@ -674,45 +677,61 @@ typedef struct {
uicc_t *uicc;
} NRUEcontext_t;
typedef struct {
uint64_t lc_bytes_tx[64];
uint64_t lc_bytes_rx[64];
uint64_t dlsch_rounds[8];
uint64_t dlsch_errors;
uint64_t dlsch_total_bytes;
int dlsch_current_bytes;
uint64_t ulsch_rounds[8];
uint64_t ulsch_errors;
typedef struct NR_mac_dir_stats {
uint64_t lc_bytes[64];
uint64_t rounds[8];
uint64_t errors;
uint64_t total_bytes;
uint32_t current_bytes;
} NR_mac_dir_stats_t;
typedef struct NR_mac_stats {
NR_mac_dir_stats_t dl;
NR_mac_dir_stats_t ul;
uint32_t ulsch_DTX;
uint64_t ulsch_total_bytes_scheduled;
uint64_t ulsch_total_bytes_rx;
int ulsch_current_bytes;
uint32_t pucch0_DTX;
int cumul_rsrp;
uint8_t num_rsrp_meas;
} NR_mac_stats_t;
typedef struct NR_bler_options {
double upper;
double lower;
uint8_t max_mcs;
} NR_bler_options_t;
/*! \brief UE list used by gNB to order UEs/CC for scheduling*/
#define MAX_CSI_REPORTCONFIG 48
typedef struct {
rnti_t rnti;
/// scheduling control info
nr_csi_report_t csi_report_template[MAX_MOBILES_PER_GNB][MAX_CSI_REPORTCONFIG];
NR_UE_sched_ctrl_t UE_sched_ctrl[MAX_MOBILES_PER_GNB];
NR_mac_stats_t mac_stats[MAX_MOBILES_PER_GNB];
NR_list_t list;
int num_UEs;
bool active[MAX_MOBILES_PER_GNB];
rnti_t rnti[MAX_MOBILES_PER_GNB];
NR_CellGroupConfig_t *CellGroup[MAX_MOBILES_PER_GNB];
nr_csi_report_t csi_report_template[MAX_CSI_REPORTCONFIG];
NR_UE_sched_ctrl_t UE_sched_ctrl;
NR_mac_stats_t mac_stats;
NR_CellGroupConfig_t *CellGroup;
/// CCE indexing
int m[MAX_MOBILES_PER_GNB];
int m;
// UE selected beam index
uint8_t UE_beam_index[MAX_MOBILES_PER_GNB];
bool Msg4_ACKed[MAX_MOBILES_PER_GNB];
uint8_t UE_beam_index;
bool Msg4_ACKed;
/// Sched CSI-RS: scheduling decisions
NR_gNB_UCI_STATS_t uci_statS;
float ul_thr_ue;
float dl_thr_ue;
int layers;
} NR_UE_info_t;
typedef struct {
/// scheduling control info
// last element always NULL
pthread_mutex_t mutex;
NR_UE_info_t *list[MAX_MOBILES_PER_GNB+1];
bool sched_csirs;
} NR_UEs_t;
#define UE_iterator(BaSe, VaR) NR_UE_info_t ** VaR##pptr=BaSe, *VaR; while ((VaR=*(VaR##pptr++)))
typedef void (*nr_pp_impl_dl)(module_id_t mod_id,
frame_t frame,
sub_frame_t slot);
@@ -771,7 +790,7 @@ typedef struct gNB_MAC_INST_s {
/// NFAPI DL PDU structure
nfapi_nr_tx_data_request_t TX_req[NFAPI_CC_MAX];
int pdcch_cand[MAX_NUM_CORESET];
NR_UE_info_t UE_info;
NR_UEs_t UE_info;
/// UL handle
uint32_t ul_handle;
@@ -807,15 +826,8 @@ typedef struct gNB_MAC_INST_s {
/// bitmap of DLSCH slots, can hold up to 160 slots
uint64_t dlsch_slot_bitmap[3];
/// Lookup for preferred time domain allocation for BWP, in DL, slots
/// dynamically allocated
int *preferred_dl_tda[MAX_NUM_BWP];
/// bitmap of ULSCH slots, can hold up to 160 slots
uint64_t ulsch_slot_bitmap[3];
/// Lookup for preferred time domain allocation for UL BWP, dynamically
/// allocated. The index refers to the DL slot, and the indicated TDA's k2
/// points to the right UL slot
int *preferred_ul_tda[MAX_NUM_BWP];
/// maximum number of slots before a UE will be scheduled ULSCH automatically
uint32_t ulsch_max_frame_inactivity;
@@ -833,10 +845,8 @@ typedef struct gNB_MAC_INST_s {
int xp_pdsch_antenna_ports;
bool first_MIB;
double dl_bler_target_upper;
double dl_bler_target_lower;
double dl_rd2_bler_threshold;
uint8_t dl_max_mcs;
NR_bler_options_t dl_bler;
NR_bler_options_t ul_bler;
uint8_t harq_round_max;
uint8_t min_grant_prb;
uint8_t min_grant_mcs;
openair2/NR_PHY_INTERFACE/NR_IF_Module.c
-3
View File
@@ -372,9 +372,6 @@ static void match_crc_rx_pdu(nfapi_nr_rx_data_indication_t *rx_ind, nfapi_nr_crc
void NR_UL_indication(NR_UL_IND_t *UL_info) {
AssertFatal(UL_info!=NULL,"UL_info is null\n");
#ifdef DUMP_FAPI
dump_ul(UL_info);
#endif
module_id_t module_id = UL_info->module_id;
int CC_id = UL_info->CC_id;
NR_Sched_Rsp_t *sched_info = &NR_Sched_INFO[module_id][CC_id];
openair2/RRC/NR/nr_rrc_config.c
+37 -49
View File
@@ -325,8 +325,7 @@ void nr_rrc_config_dl_tda(NR_ServingCellConfigCommon_t *scc,
int len_coreset = 1;
if (curr_bwp < 48)
len_coreset = 2;
// setting default TDA for DL with
// setting default TDA for DL with TDA index 0
struct NR_PDSCH_TimeDomainResourceAllocation *timedomainresourceallocation = CALLOC(1,sizeof(NR_PDSCH_TimeDomainResourceAllocation_t));
// k0: Slot offset between DCI and its scheduled PDSCH (see TS 38.214 clause 5.1.2.1) When the field is absent the UE applies the value 0.
//timedomainresourceallocation->k0 = calloc(1,sizeof(*timedomainresourceallocation->k0));
@@ -334,18 +333,20 @@ void nr_rrc_config_dl_tda(NR_ServingCellConfigCommon_t *scc,
timedomainresourceallocation->mappingType = NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA;
timedomainresourceallocation->startSymbolAndLength = get_SLIV(len_coreset,14-len_coreset); // basic slot configuration starting in symbol 1 til the end of the slot
ASN_SEQUENCE_ADD(&pdsch_TimeDomainAllocationList->list, timedomainresourceallocation);
// setting TDA for CSI-RS symbol with index 1
struct NR_PDSCH_TimeDomainResourceAllocation *timedomainresourceallocation1 = CALLOC(1,sizeof(NR_PDSCH_TimeDomainResourceAllocation_t));
timedomainresourceallocation1->mappingType = NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA;
timedomainresourceallocation1->startSymbolAndLength = get_SLIV(len_coreset,14-len_coreset-1); // 1 symbol CSI-RS
ASN_SEQUENCE_ADD(&pdsch_TimeDomainAllocationList->list, timedomainresourceallocation1);
if(frame_type==TDD) {
// TDD
if(scc->tdd_UL_DL_ConfigurationCommon) {
int dl_symb = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSymbols;
if(dl_symb > 1) {
timedomainresourceallocation = CALLOC(1,sizeof(NR_PDSCH_TimeDomainResourceAllocation_t));
// k0: Slot offset between DCI and its scheduled PDSCH (see TS 38.214 clause 5.1.2.1) When the field is absent the UE applies the value 0.
//timedomainresourceallocation->k0 = calloc(1,sizeof(*timedomainresourceallocation->k0));
//*timedomainresourceallocation->k0 = 0;
timedomainresourceallocation->mappingType = NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA;
timedomainresourceallocation->startSymbolAndLength = get_SLIV(len_coreset,dl_symb-len_coreset); // mixed slot configuration starting in symbol 1 til the end of the dl allocation
ASN_SEQUENCE_ADD(&pdsch_TimeDomainAllocationList->list, timedomainresourceallocation);
// mixed slot TDA with TDA index 2
struct NR_PDSCH_TimeDomainResourceAllocation *timedomainresourceallocation2 = CALLOC(1,sizeof(NR_PDSCH_TimeDomainResourceAllocation_t));
timedomainresourceallocation2->mappingType = NR_PDSCH_TimeDomainResourceAllocation__mappingType_typeA;
timedomainresourceallocation2->startSymbolAndLength = get_SLIV(len_coreset,dl_symb-len_coreset); // mixed slot configuration starting in symbol 1 til the end of the dl allocation
ASN_SEQUENCE_ADD(&pdsch_TimeDomainAllocationList->list, timedomainresourceallocation2);
}
}
}
@@ -357,58 +358,45 @@ void nr_rrc_config_ul_tda(NR_ServingCellConfigCommon_t *scc, int min_fb_delay){
//TODO change to accomodate for SRS
frame_type_t frame_type = get_frame_type(*scc->downlinkConfigCommon->frequencyInfoDL->frequencyBandList.list.array[0], *scc->ssbSubcarrierSpacing);
int temp_min_delay = 6; // k2 = 2 or 3 won'r work as well as higher values
if(frame_type==TDD && scc->tdd_UL_DL_ConfigurationCommon) {
switch (scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity) {
case NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms2p5: // 30kHz SCS
case NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms2: // 60kHz SCS
case NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms1p25: // 60kHz SCS
case NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms1: // 120kHz SCS
case NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms0p625: // 120kHz SCS
case NR_TDD_UL_DL_Pattern__dl_UL_TransmissionPeriodicity_ms0p5: // 120kHz SCS
temp_min_delay = 2;
break;
}
}
int k2 = (min_fb_delay<temp_min_delay)?temp_min_delay:min_fb_delay;
const int k2 = min_fb_delay;
uint8_t DELTA[4]= {2,3,4,6}; // Delta parameter for Msg3
int mu = scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.subcarrierSpacing;
// UL TDA index 0 is basic slot configuration starting in symbol 0 til the last but one symbol
struct NR_PUSCH_TimeDomainResourceAllocation *pusch_timedomainresourceallocation = CALLOC(1,sizeof(struct NR_PUSCH_TimeDomainResourceAllocation));
pusch_timedomainresourceallocation->k2 = CALLOC(1,sizeof(long));
*pusch_timedomainresourceallocation->k2 = k2;
pusch_timedomainresourceallocation->mappingType = NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB;
pusch_timedomainresourceallocation->startSymbolAndLength = get_SLIV(0,13); // basic slot configuration starting in symbol 0 til the last but one symbol
pusch_timedomainresourceallocation->startSymbolAndLength = get_SLIV(0,13);
ASN_SEQUENCE_ADD(&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list,pusch_timedomainresourceallocation);
if(frame_type==TDD) {
// TDD
if(scc->tdd_UL_DL_ConfigurationCommon) {
int ul_symb = scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofUplinkSymbols;
pusch_timedomainresourceallocation = CALLOC(1,sizeof(struct NR_PUSCH_TimeDomainResourceAllocation));
pusch_timedomainresourceallocation->k2 = CALLOC(1,sizeof(long));
*pusch_timedomainresourceallocation->k2 = k2;
pusch_timedomainresourceallocation->mappingType = NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB;
pusch_timedomainresourceallocation->startSymbolAndLength = get_SLIV(14-ul_symb,ul_symb-1); // starting in fist ul symbol til the last but one
ASN_SEQUENCE_ADD(&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list,pusch_timedomainresourceallocation);
if (ul_symb>1) {
// UL TDA index 1 for mixed slot (TDD)
pusch_timedomainresourceallocation = CALLOC(1,sizeof(struct NR_PUSCH_TimeDomainResourceAllocation));
pusch_timedomainresourceallocation->k2 = CALLOC(1,sizeof(long));
*pusch_timedomainresourceallocation->k2 = k2;
pusch_timedomainresourceallocation->mappingType = NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB;
pusch_timedomainresourceallocation->startSymbolAndLength = get_SLIV(14-ul_symb,ul_symb-1); // starting in fist ul symbol til the last but one
ASN_SEQUENCE_ADD(&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list,pusch_timedomainresourceallocation);
// for msg3 in the mixed slot
int nb_periods_per_frame = get_nb_periods_per_frame(scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity);
int nb_slots_per_period = ((1<<mu) * 10)/nb_periods_per_frame;
struct NR_PUSCH_TimeDomainResourceAllocation *pusch_timedomainresourceallocation_msg3 = CALLOC(1,sizeof(struct NR_PUSCH_TimeDomainResourceAllocation));
pusch_timedomainresourceallocation_msg3->k2 = CALLOC(1,sizeof(long));
*pusch_timedomainresourceallocation_msg3->k2 = nb_slots_per_period - DELTA[mu];
if(*pusch_timedomainresourceallocation_msg3->k2 < min_fb_delay)
*pusch_timedomainresourceallocation_msg3->k2 += nb_slots_per_period;
AssertFatal(*pusch_timedomainresourceallocation_msg3->k2<33,"Computed k2 for msg3 %ld is larger than the range allowed by RRC (0..32)\n",
*pusch_timedomainresourceallocation_msg3->k2);
pusch_timedomainresourceallocation_msg3->mappingType = NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB;
pusch_timedomainresourceallocation_msg3->startSymbolAndLength = get_SLIV(14-ul_symb,ul_symb-1); // starting in fist ul symbol til the last but one
ASN_SEQUENCE_ADD(&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list,pusch_timedomainresourceallocation_msg3);
// UL TDA index 2 for msg3 in the mixed slot (TDD)
int nb_periods_per_frame = get_nb_periods_per_frame(scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity);
int nb_slots_per_period = ((1<<mu) * 10)/nb_periods_per_frame;
struct NR_PUSCH_TimeDomainResourceAllocation *pusch_timedomainresourceallocation_msg3 = CALLOC(1,sizeof(struct NR_PUSCH_TimeDomainResourceAllocation));
pusch_timedomainresourceallocation_msg3->k2 = CALLOC(1,sizeof(long));
*pusch_timedomainresourceallocation_msg3->k2 = nb_slots_per_period - DELTA[mu];
if(*pusch_timedomainresourceallocation_msg3->k2 < min_fb_delay)
*pusch_timedomainresourceallocation_msg3->k2 += nb_slots_per_period;
AssertFatal(*pusch_timedomainresourceallocation_msg3->k2<33,"Computed k2 for msg3 %ld is larger than the range allowed by RRC (0..32)\n",
*pusch_timedomainresourceallocation_msg3->k2);
pusch_timedomainresourceallocation_msg3->mappingType = NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB;
pusch_timedomainresourceallocation_msg3->startSymbolAndLength = get_SLIV(14-ul_symb,ul_symb-1); // starting in fist ul symbol til the last but one
ASN_SEQUENCE_ADD(&scc->uplinkConfigCommon->initialUplinkBWP->pusch_ConfigCommon->choice.setup->pusch_TimeDomainAllocationList->list,pusch_timedomainresourceallocation_msg3);
}
}
}
}
@@ -633,7 +621,7 @@ void set_dl_mcs_table(int scs, NR_UE_NR_Capability_t *cap,
}
AssertFatal(bw_rb>0,"Could not find scs-SpecificCarrierList element for scs %d",scs);
int bw = get_supported_band_index(scs, band, bw_rb);
AssertFatal(bw>0,"Supported band corresponding to %d RBs not found\n", bw_rb);
AssertFatal(bw>=0,"Supported band corresponding to %d RBs not found\n", bw_rb);
bool supported = false;
if (band>256) {
openair2/RRC/NR/rrc_gNB.c
+4 -3
View File
@@ -1643,7 +1643,7 @@ rrc_gNB_generate_RRCReestablishment(
ue_context->Srb0.Tx_buffer.payload_size);
#if(0)
/* TODO : It may be needed if gNB goes into full stack working. */
UE_id = find_nr_UE_id(module_id, rnti);
UE = find_nr_UE(module_id, rnti);
if (UE_id != -1) {
/* Activate reject timer, if RRCComplete not received after 10 frames, reject UE */
RC.nrmac[module_id]->UE_info.UE_sched_ctrl[UE_id].ue_reestablishment_reject_timer = 1;
@@ -3549,6 +3549,7 @@ void nr_rrc_subframe_process(protocol_ctxt_t *const ctxt_pP, const int CC_id) {
FILE *fd=NULL;//fopen("nrRRCstats.log","w");
RB_FOREACH(ue_context_p, rrc_nr_ue_tree_s, &(RC.nrrrc[ctxt_pP->module_id]->rrc_ue_head)) {
ctxt_pP->rnti = ue_context_p->ue_id_rnti;
gNB_MAC_INST *nrmac=RC.nrmac[ctxt_pP->module_id]; //WHAT A BEAUTIFULL RACE CONDITION !!!
if (fd) {
if (ue_context_p->ue_context.Initialue_identity_5g_s_TMSI.presence == TRUE) {
@@ -3588,7 +3589,7 @@ void nr_rrc_subframe_process(protocol_ctxt_t *const ctxt_pP, const int CC_id) {
// Remove here the MAC and RRC context when RRC is not connected or gNB is not connected to CN5G
if(ue_context_p->ue_context.StatusRrc < NR_RRC_CONNECTED || ue_context_p->ue_context.gNB_ue_ngap_id == 0) {
mac_remove_nr_ue(ctxt_pP->module_id, ctxt_pP->rnti);
mac_remove_nr_ue(nrmac, ctxt_pP->rnti);
rrc_rlc_remove_ue(ctxt_pP);
pdcp_remove_UE(ctxt_pP);
@@ -3612,7 +3613,7 @@ void nr_rrc_subframe_process(protocol_ctxt_t *const ctxt_pP, const int CC_id) {
ue_context_p->ue_context.rnti);
ue_context_p->ue_context.ue_release_timer_rrc = 0;
mac_remove_nr_ue(ctxt_pP->module_id, ctxt_pP->rnti);
mac_remove_nr_ue(nrmac, ctxt_pP->rnti);
rrc_rlc_remove_ue(ctxt_pP);
pdcp_remove_UE(ctxt_pP);
newGtpuDeleteAllTunnels(ctxt_pP->instance, ctxt_pP->rnti);
openair2/RRC/NR/rrc_gNB_nsa.c
+2 -1
View File
@@ -426,7 +426,8 @@ void rrc_remove_nsa_user(gNB_RRC_INST *rrc, int rnti) {
rrc_rlc_remove_ue(&ctxt);
mac_remove_nr_ue(rrc->module_id, rnti);
// WHAT A RACE CONDITION
mac_remove_nr_ue(RC.nrmac[rrc->module_id], rnti);
gtpv1u_enb_delete_tunnel_req_t tmp={0};
tmp.rnti=rnti;
tmp.from_gnb=1;
openair2/UTIL/OPT/opt.h
+4 -1
View File
@@ -109,11 +109,14 @@ typedef enum radio_type_e {
extern int opt_enabled;
#define trace_pdu(x...) if (opt_enabled) trace_pdu_implementation(0, x)
#define trace_NRpdu(x...) if (opt_enabled) trace_pdu_implementation(1, x)
#define trace_NRpdu(x...) if (opt_enabled) nr_trace_pdu_implementation(1, x)
void trace_pdu_implementation(int nr, int direction, uint8_t *pdu_buffer, unsigned int pdu_buffer_size,
int ueid, int rntiType, int rnti, uint16_t sysFrame, uint8_t subframe,
int oob_event, int oob_event_value);
void nr_trace_pdu_implementation(int nr, int direction, uint8_t *pdu_buffer, unsigned int pdu_buffer_size,
int rntiType, int rnti, uint16_t sysFrame, uint8_t subframe,
int oob_event, int oob_event_value);
int init_opt(void);
openair2/UTIL/OPT/probe.c
+8
View File
@@ -476,6 +476,14 @@ static void SendFrameNR(guint8 radioType, guint8 direction, guint8 rntiType,
extern RAN_CONTEXT_t RC;
#include <openair1/PHY/phy_extern_ue.h>
/* Remote serveraddress (where Wireshark is running) */
void nr_trace_pdu_implementation(int nr, int direction, uint8_t *pdu_buffer, unsigned int pdu_buffer_size,
int rntiType, int rnti, uint16_t sysFrameNumber, uint8_t subFrameNumber, int oob_event,
int oob_event_value) {
trace_pdu_implementation(nr, direction, pdu_buffer, pdu_buffer_size,
rnti, rntiType, rnti, sysFrameNumber, subFrameNumber, oob_event,
oob_event_value);
}
void trace_pdu_implementation(int nr, int direction, uint8_t *pdu_buffer, unsigned int pdu_buffer_size,
int ueid, int rntiType, int rnti, uint16_t sysFrameNumber, uint8_t subFrameNumber, int oob_event,
int oob_event_value) {
targets/ARCH/COMMON/common_lib.h
+1
View File
@@ -188,6 +188,7 @@ typedef struct {
//! \brief Center frequency in Hz for TX.
//! index: [0..rx_num_channels[ !!! see lte-ue.c:427 FIXME iterates over rx_num_channels
double tx_freq[4];
double tune_offset;
//! \brief memory
//! \brief Pointer to Calibration table for RX gains
rx_gain_calib_table_t *rx_gain_calib_table;
targets/ARCH/USRP/USERSPACE/LIB/usrp_lib.cpp
+25 -10
View File
@@ -644,6 +644,7 @@ static int trx_usrp_read(openair0_device *device, openair0_timestamp *ptimestamp
break;
case USRP_X300_DEV:
case USRP_N300_DEV:
case USRP_X400_DEV:
rxshift=2;
break;
default:
@@ -746,8 +747,12 @@ static bool is_equal(double a, double b) {
void *freq_thread(void *arg) {
openair0_device *device=(openair0_device *)arg;
usrp_state_t *s = (usrp_state_t *)device->priv;
s->usrp->set_tx_freq(device->openair0_cfg[0].tx_freq[0]);
s->usrp->set_rx_freq(device->openair0_cfg[0].rx_freq[0]);
uhd::tune_request_t tx_tune_req(device->openair0_cfg[0].tx_freq[0],
device->openair0_cfg[0].tune_offset);
uhd::tune_request_t rx_tune_req(device->openair0_cfg[0].rx_freq[0],
device->openair0_cfg[0].tune_offset);
s->usrp->set_tx_freq(tx_tune_req);
s->usrp->set_rx_freq(rx_tune_req);
return NULL;
}
/*! \brief Set frequencies (TX/RX). Spawns a thread to handle the frequency change to not block the calling thread
@@ -759,14 +764,18 @@ void *freq_thread(void *arg) {
int trx_usrp_set_freq(openair0_device *device, openair0_config_t *openair0_cfg, int dont_block) {
usrp_state_t *s = (usrp_state_t *)device->priv;
pthread_t f_thread;
printf("Setting USRP TX Freq %f, RX Freq %f\n",openair0_cfg[0].tx_freq[0],openair0_cfg[0].rx_freq[0]);
printf("Setting USRP TX Freq %f, RX Freq %f, tune_offset: %f, dont_block: %d\n",
openair0_cfg[0].tx_freq[0],openair0_cfg[0].rx_freq[0],
openair0_cfg[0].tune_offset, dont_block);
// spawn a thread to handle the frequency change to not block the calling thread
if (dont_block == 1)
pthread_create(&f_thread,NULL,freq_thread,(void *)device);
else {
s->usrp->set_tx_freq(device->openair0_cfg[0].tx_freq[0]);
s->usrp->set_rx_freq(device->openair0_cfg[0].rx_freq[0]);
uhd::tune_request_t tx_tune_req(openair0_cfg[0].tx_freq[0], openair0_cfg[0].tune_offset);
uhd::tune_request_t rx_tune_req(openair0_cfg[0].rx_freq[0], openair0_cfg[0].tune_offset);
s->usrp->set_tx_freq(tx_tune_req);
s->usrp->set_rx_freq(rx_tune_req);
}
return(0);
@@ -779,9 +788,11 @@ int trx_usrp_set_freq(openair0_device *device, openair0_config_t *openair0_cfg,
*/
int openair0_set_rx_frequencies(openair0_device *device, openair0_config_t *openair0_cfg) {
usrp_state_t *s = (usrp_state_t *)device->priv;
uhd::tune_request_t rx_tune_req(openair0_cfg[0].rx_freq[0]);
rx_tune_req.rf_freq_policy = uhd::tune_request_t::POLICY_MANUAL;
rx_tune_req.rf_freq = openair0_cfg[0].rx_freq[0];
uhd::tune_request_t rx_tune_req(openair0_cfg[0].rx_freq[0], openair0_cfg[0].tune_offset);
printf("In openair0_set_rx_frequencies, freq: %f, tune offset: %f\n",
openair0_cfg[0].rx_freq[0], openair0_cfg[0].tune_offset);
//rx_tune_req.rf_freq_policy = uhd::tune_request_t::POLICY_MANUAL;
//rx_tune_req.rf_freq = openair0_cfg[0].rx_freq[0];
s->usrp->set_rx_freq(rx_tune_req);
return(0);
}
@@ -1276,7 +1287,9 @@ extern "C" {
for(int i=0; i<((int) s->usrp->get_rx_num_channels()); i++) {
if (i<openair0_cfg[0].rx_num_channels) {
s->usrp->set_rx_rate(openair0_cfg[0].sample_rate,i+choffset);
s->usrp->set_rx_freq(openair0_cfg[0].rx_freq[i],i+choffset);
uhd::tune_request_t rx_tune_req(openair0_cfg[0].rx_freq[i],
openair0_cfg[0].tune_offset);
s->usrp->set_rx_freq(rx_tune_req, i+choffset);
set_rx_gain_offset(&openair0_cfg[0],i,bw_gain_adjust);
::uhd::gain_range_t gain_range = s->usrp->get_rx_gain_range(i+choffset);
// limit to maximum gain
@@ -1302,7 +1315,9 @@ extern "C" {
if (i<openair0_cfg[0].tx_num_channels) {
s->usrp->set_tx_rate(openair0_cfg[0].sample_rate,i+choffset);
s->usrp->set_tx_freq(openair0_cfg[0].tx_freq[i],i+choffset);
uhd::tune_request_t tx_tune_req(openair0_cfg[0].tx_freq[i],
openair0_cfg[0].tune_offset);
s->usrp->set_tx_freq(tx_tune_req, i+choffset);
s->usrp->set_tx_gain(gain_range_tx.stop()-openair0_cfg[0].tx_gain[i],i+choffset);
LOG_I(HW,"USRP TX_GAIN:%3.2lf gain_range:%3.2lf tx_gain:%3.2lf\n", gain_range_tx.stop()-openair0_cfg[0].tx_gain[i], gain_range_tx.stop(), openair0_cfg[0].tx_gain[i]);
}
targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band66.tm1.25PRB.usrpn300.conf
+266
View File
@@ -0,0 +1,266 @@
Active_gNBs = ( "gNB-Eurecom-5GNRBox");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
cell_type = "CELL_MACRO_GNB";
gNB_name = "gNB-Eurecom-5GNRBox";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({mcc = 208; mnc = 93; mnc_length = 2;});
tr_s_preference = "local_mac";
////////// Physical parameters:
ssb_SubcarrierOffset = 0;
pdsch_AntennaPorts = 1;
pusch_AntennaPorts = 1;
min_rxtxtime = 6;
servingCellConfigCommon = (
{
#spCellConfigCommon
physCellId = 0;
# downlinkConfigCommon
#frequencyInfoDL
# this is 2150 MHz + 12 PRBs@15kHz SCS (same as initial BWP), points to Subcarrier 0 of RB#10 of SSB block
absoluteFrequencySSB = 430432;
dl_frequencyBand = 66;
# this is 2150 MHz
dl_absoluteFrequencyPointA = 430000;
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 0;
dl_carrierBandwidth = 25;
#initialDownlinkBWP
#genericParameters
# this is RBstart=0,L=25 (275*(L-1))+RBstart
initialDLBWPlocationAndBandwidth = 6600;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 0;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 0;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 66;
ul_absoluteFrequencyPointA = 350000;
#scs-SpecificCarrierList
ul_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 0;
ul_carrierBandwidth = 25;
pMax = 20;
#initialUplinkBWP
#genericParameters
initialULBWPlocationAndBandwidth = 6600;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 0;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 98;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 13;
preambleReceivedTargetPower = -118;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
#ra_ReponseWindow
#1,2,4,8,10,20,40,80
ra_ResponseWindow = 4;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#oneHalf (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#1 = 839, 2 = 139
prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
msg1_SubcarrierSpacing = 0;
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0;
msg3_DeltaPreamble = 1;
p0_NominalWithGrant =-90;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 40;
p0_nominal = -90;
# ssb_PositionsInBurs_BitmapPR
# 1=short, 2=medium, 3=long
ssb_PositionsInBurst_PR = 2;
ssb_PositionsInBurst_Bitmap = 0x1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
dmrs_TypeA_Position = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
subcarrierSpacing = 0;
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
referenceSubcarrierSpacing = 0;
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 6;
nrofDownlinkSlots = 7;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2;
nrofUplinkSymbols = 4;
ssPBCH_BlockPower = -25;
}
);
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// MME parameters:
mme_ip_address = ( { ipv4 = "192.168.12.26";
ipv6 = "192:168:30::17";
active = "yes";
preference = "ipv4";
}
);
NETWORK_INTERFACES :
{
GNB_INTERFACE_NAME_FOR_S1_MME = "eth0";
GNB_IPV4_ADDRESS_FOR_S1_MME = "192.168.12.111/24";
GNB_INTERFACE_NAME_FOR_S1U = "eth0";
GNB_IPV4_ADDRESS_FOR_S1U = "192.168.12.111/24";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
thread_pool_size = 8;
ofdm_offset_divisor = 8; #set this to UINT_MAX for offset 0
}
);
RUs = (
{
local_rf = "yes";
nb_tx = 1;
nb_rx = 1;
att_tx = 0;
att_rx = 0;
bands = [7];
max_pdschReferenceSignalPower = -27;
max_rxgain = 50;
eNB_instances = [0];
## beamforming 1x2 matrix: 1 layer x 2 antennas
bf_weights = [0x00007fff, 0x0000];
## beamforming 1x4 matrix: 1 layer x 4 antennas
#bf_weights = [0x00007fff, 0x0000,0x0000, 0x0000];
## beamforming 2x2 matrix:
#bf_weights = [0x00007fff, 0x00000000, 0x00000000, 0x00007fff];
## beamforming 4x4 matrix:
#bf_weights = [0x00007fff, 0x0000, 0x0000, 0x0000, 0x00000000, 0x00007fff, 0x0000, 0x0000, 0x0000, 0x0000, 0x00007fff, 0x0000, 0x0000, 0x0000, 0x0000, 0x00007fff];
sdr_addrs = "addr=192.168.10.2,mgmt_addr=192.168.10.2,second_addr=192.168.20.2";
clock_src = "external";
# if_freq = 3700000000L;
# if_offset = 1000000;
}
);
THREAD_STRUCT = (
{
#three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
parallel_config = "PARALLEL_RU_L1_TRX_SPLIT";
#two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
worker_config = "WORKER_DISABLE";
}
);
security = {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
# valid values: nea0, nea1, nea2, nea3
ciphering_algorithms = ( "nea0" );
# preferred integrity algorithms
# the first one of the list that an UE supports in chosen
# valid values: nia0, nia1, nia2, nia3
integrity_algorithms = ( "nia2", "nia0" );
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
};
targets/RT/USER/lte-ru.c
+5 -2
View File
@@ -1371,11 +1371,12 @@ void fill_rf_config(RU_t *ru,
cfg->tx_gain[i] = (double)ru->att_tx;
cfg->rx_gain[i] = ru->max_rxgain-(double)ru->att_rx;
cfg->configFilename = rf_config_file;
LOG_I(PHY,"channel %d, Setting tx_gain offset %f, rx_gain offset %f, tx_freq %f, rx_freq %f\n",
LOG_I(PHY,"channel %d, Setting tx_gain offset %.0f, rx_gain offset %.0f, tx_freq %.0f, rx_freq %.0f, tune_offset %.0f Hz\n",
i, cfg->tx_gain[i],
cfg->rx_gain[i],
cfg->tx_freq[i],
cfg->rx_freq[i]);
cfg->rx_freq[i],
cfg->tune_offset);
}
}
@@ -2972,6 +2973,8 @@ RU_t **RCconfig_RU(int nb_RU,int nb_L1_inst,PHY_VARS_eNB ***eNB,uint64_t *ru_mas
ru[j]->openair0_cfg.time_source = unset;
}
ru[j]->openair0_cfg.tune_offset = get_softmodem_params()->tune_offset;
LOG_I(PHY,"RU %d is_slave=%s\n",j,*(RUParamList.paramarray[j][RU_IS_SLAVE_IDX].strptr));
if (strcmp(*(RUParamList.paramarray[j][RU_IS_SLAVE_IDX].strptr), "yes") == 0) ru[j]->is_slave=1;
targets/RT/USER/lte-uesoftmodem.c
+4 -2
View File
@@ -446,6 +446,7 @@ void init_openair0(LTE_DL_FRAME_PARMS *frame_parms,int rxgain) {
openair0_cfg[card].num_rb_dl=frame_parms->N_RB_DL;
openair0_cfg[card].clock_source = get_softmodem_params()->clock_source;
openair0_cfg[card].time_source = get_softmodem_params()->timing_source;
openair0_cfg[card].tune_offset = get_softmodem_params()->tune_offset;
openair0_cfg[card].tx_num_channels=min(2,frame_parms->nb_antennas_tx);
openair0_cfg[card].rx_num_channels=min(2,frame_parms->nb_antennas_rx);
@@ -464,11 +465,12 @@ void init_openair0(LTE_DL_FRAME_PARMS *frame_parms,int rxgain) {
openair0_cfg[card].tx_gain[i] = tx_gain[0][i];
openair0_cfg[card].rx_gain[i] = rxgain - rx_gain_off;
openair0_cfg[card].configFilename = get_softmodem_params()->rf_config_file;
printf("Card %d, channel %d, Setting tx_gain %f, rx_gain %f, tx_freq %f, rx_freq %f\n",
printf("Card %d, channel %d, Setting tx_gain %.0f, rx_gain %.0f, tx_freq %.0f, rx_freq %.0f, tune_offset %.0f\n",
card,i, openair0_cfg[card].tx_gain[i],
openair0_cfg[card].rx_gain[i],
openair0_cfg[card].tx_freq[i],
openair0_cfg[card].rx_freq[i]);
openair0_cfg[card].rx_freq[i],
openair0_cfg[card].tune_offset);
}
if (usrp_args) openair0_cfg[card].sdr_addrs = usrp_args;