nr_fill_nfapi_dl_pdu(): Parameters by value, not pointers
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@@ -420,6 +420,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
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const int ta_len = gNB_mac->ta_len;
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const int UE_id = 0;
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const int CC_id = 0;
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const int bwp_id = 1;
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nfapi_nr_dl_tti_request_body_t *dl_req = &gNB_mac->DL_req[CC_id].dl_tti_request_body;
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nfapi_nr_pdu_t *tx_req = &gNB_mac->TX_req[CC_id].pdu_list[gNB_mac->TX_req[CC_id].Number_of_PDUs];
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@@ -427,6 +428,12 @@ void nr_schedule_ue_spec(module_id_t module_id,
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NR_UE_list_t *UE_list = &gNB_mac->UE_list;
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if (UE_list->num_UEs ==0) return;
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NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id];
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AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1,
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"downlinkBWP_ToAddModList has %d BWP!\n",
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secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count);
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NR_BWP_Downlink_t *bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id - 1];
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const uint16_t bwpSize = NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275);
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unsigned char sdu_lcids[NB_RB_MAX] = {0};
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uint16_t sdu_lengths[NB_RB_MAX] = {0};
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@@ -439,7 +446,12 @@ void nr_schedule_ue_spec(module_id_t module_id,
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int pucch_sched;
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nr_update_pucch_scheduling(module_id, UE_id, frame, slot, num_slots_per_tdd, &pucch_sched);
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NR_sched_pucch *pucch = &UE_list->UE_sched_ctrl[UE_id].sched_pucch[pucch_sched];
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const int TBS_bytes = nr_fill_nfapi_dl_pdu(module_id, dl_req, pucch, NULL, NULL, NULL);
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const int TBS_bytes = nr_fill_nfapi_dl_pdu(module_id,
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dl_req,
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pucch,
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9 /* mcs */,
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bwpSize,
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0 /* bwpStart */);
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if (TBS_bytes == 0)
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return;
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@@ -410,9 +410,9 @@ void nr_configure_css_dci_initial(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
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int nr_fill_nfapi_dl_pdu(int Mod_idP,
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nfapi_nr_dl_tti_request_body_t *dl_req,
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NR_sched_pucch *pucch_sched,
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uint8_t *mcsIndex,
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uint16_t *rbSize,
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uint16_t *rbStart) {
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uint8_t mcs,
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uint16_t rbSize,
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uint16_t rbStart) {
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gNB_MAC_INST *nr_mac = RC.nrmac[Mod_idP];
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NR_COMMON_channels_t *cc = nr_mac->common_channels;
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NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
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@@ -464,7 +464,6 @@ int nr_fill_nfapi_dl_pdu(int Mod_idP,
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pdsch_pdu_rel15->CyclicPrefix = 0;
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pdsch_pdu_rel15->NrOfCodewords = 1;
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int mcs = (mcsIndex!=NULL) ? *mcsIndex : 9;
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int current_harq_pid = UE_list->UE_sched_ctrl[UE_id].current_harq_pid;
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pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcs,0);
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pdsch_pdu_rel15->qamModOrder[0] = 2;
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@@ -482,8 +481,8 @@ int nr_fill_nfapi_dl_pdu(int Mod_idP,
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pdsch_pdu_rel15->numDmrsCdmGrpsNoData = 1;
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pdsch_pdu_rel15->dmrsPorts = 1;
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pdsch_pdu_rel15->resourceAlloc = 1;
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pdsch_pdu_rel15->rbStart = (rbStart!=NULL) ? *rbStart : 0;
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pdsch_pdu_rel15->rbSize = (rbSize!=NULL) ? *rbSize : pdsch_pdu_rel15->BWPSize;
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pdsch_pdu_rel15->rbStart = rbStart;
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pdsch_pdu_rel15->rbSize = rbSize;
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pdsch_pdu_rel15->VRBtoPRBMapping = 1; // non-interleaved, check if this is ok for initialBWP
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int startSymbolAndLength=0;
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@@ -132,9 +132,9 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
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int nr_fill_nfapi_dl_pdu(int Mod_id,
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nfapi_nr_dl_tti_request_body_t *dl_req,
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NR_sched_pucch *pucch_sched,
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uint8_t *mcsIndex,
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uint16_t *rbSize,
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uint16_t *rbStart);
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uint8_t mcs,
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uint16_t rbSize,
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uint16_t rbStart);
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int configure_fapi_dl_pdu_phytest(int Mod_id,
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nfapi_nr_dl_tti_request_body_t *dl_req,
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