Inter/intra-slice sharing are now optional
This commit is contained in:
committed by
Robert Schmidt
parent
8d9a8ab59a
commit
9efd5d6f27
@@ -114,6 +114,11 @@ typedef enum {
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CR_NUM = 6
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} sorting_criterion_t;
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typedef enum {
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POL_FAIR = 0,
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POL_GREEDY = 1,
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POL_NUM = 2
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} accounting_policy_t;
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//-----------------------------------------------------------------------------
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// PHY TYPES
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//-----------------------------------------------------------------------------
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@@ -435,6 +435,34 @@ schedule_dlsch(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP, in
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slice_percentage_total += slice_percentage[i];
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}
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// Check for *intra*slice share activation
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if (intraslice_share_active_current != intraslice_share_active) {
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if (intraslice_share_active != 1 && intraslice_share_active != 0) {
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LOG_W(MAC,
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"[eNB %d][DL] frame %d subframe %d: invalid intraslice sharing status (%d), revert to its previous value (%d)\n",
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module_idP, i, frameP, subframeP, intraslice_share_active, intraslice_share_active_current);
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intraslice_share_active = intraslice_share_active_current;
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} else {
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LOG_N(MAC, "[eNB %d][DL] frame %d subframe %d: intraslice sharing status has changed (%x-->%x)\n",
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module_idP, i, frameP, subframeP, intraslice_share_active_current, intraslice_share_active);
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intraslice_share_active_current = intraslice_share_active;
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}
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}
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// Check for *inter*slice share activation
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if (interslice_share_active_current != interslice_share_active) {
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if (interslice_share_active != 1 && interslice_share_active != 0) {
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LOG_W(MAC,
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"[eNB %d][DL] frame %d subframe %d: invalid interslice sharing status (%d), revert to its previous value (%d)\n",
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module_idP, i, frameP, subframeP, interslice_share_active, interslice_share_active_current);
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interslice_share_active = interslice_share_active_current;
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} else {
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LOG_N(MAC, "[eNB %d][DL] frame %d subframe %d: interslice sharing status has changed (%x-->%x)\n",
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module_idP, i, frameP, subframeP, interslice_share_active_current, interslice_share_active);
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interslice_share_active_current = interslice_share_active;
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}
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}
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for (i = 0; i < n_active_slices; i++) {
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// Load any updated functions
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@@ -712,7 +740,9 @@ schedule_ue_spec(module_id_t module_idP, slice_id_t slice_idP,
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return;
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}
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dlsch_scheduler_interslice_multiplexing(module_idP, frameP, subframeP);
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if (interslice_share_active) {
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dlsch_scheduler_interslice_multiplexing(module_idP, frameP, subframeP);
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}
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for (CC_id = 0; CC_id < NFAPI_CC_MAX; CC_id++) {
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LOG_D(MAC, "doing schedule_ue_spec for CC_id %d\n", CC_id);
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@@ -1732,7 +1762,7 @@ void dlsch_scheduler_qos_multiplexing(module_id_t Mod_id, int frameP, sub_frame_
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UE_list_t *UE_list = &RC.mac[Mod_id]->UE_list;
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UE_sched_ctrl *ue_sched_ctl;
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for (CC_id = 0; CC_id < MAX_NUM_CCs; ++CC_id) {
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for (CC_id = 0; CC_id < NFAPI_CC_MAX; ++CC_id) {
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for (i = 0; i < n_active_slices; ++i) {
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// Sort UE again
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@@ -42,6 +42,11 @@ int n_active_slices = 1;
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int n_active_slices_current = 1;
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int slice_counter = 0;
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int intraslice_share_active = 1;
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int intraslice_share_active_current = 1;
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int interslice_share_active = 1;
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int interslice_share_active_current = 1;
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// RB share for each slice for past and current time
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float slice_percentage[MAX_NUM_SLICES] = {1.0, 0.0, 0.0, 0.0};
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float slice_percentage_current[MAX_NUM_SLICES] = {1.0, 0.0, 0.0, 0.0};
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@@ -1582,6 +1582,10 @@ typedef struct {
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uint8_t slice_allocation_mask[NFAPI_CC_MAX][N_RBG_MAX];
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uint8_t slice_allocated_rbgs[NFAPI_CC_MAX][N_RBG_MAX];
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uint8_t MIMO_mode_indicator[NFAPI_CC_MAX][N_RBG_MAX];
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uint32_t bytes_lcid[MAX_MOBILES_PER_ENB][MAX_NUM_LCID];
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uint32_t wb_pmi[MAX_NUM_CCs][MAX_MOBILES_PER_ENB];
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uint8_t mcs[MAX_NUM_CCs][MAX_MOBILES_PER_ENB];
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} pre_processor_results_t;
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#include "mac_proto.h"
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@@ -63,6 +63,8 @@ extern int slice_maxmcs[MAX_NUM_SLICES];
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extern int slice_maxmcs_uplink[MAX_NUM_SLICES];
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extern pre_processor_results_t pre_processor_results[MAX_NUM_SLICES];
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extern int intraslice_share_active;
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//#define ICIC 0
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/* this function checks that get_eNB_UE_stats returns
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@@ -164,6 +166,7 @@ store_dlsch_buffer(module_id_t Mod_id,
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#endif
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}
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if (UE_template->dl_buffer_total > 0)
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@@ -204,7 +207,8 @@ assign_rbs_required(module_id_t Mod_id,
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CC_id = UE_list->ordered_CCids[n][UE_id];
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eNB_UE_stats = &UE_list->eNB_UE_stats[CC_id][UE_id];
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eNB_UE_stats->dlsch_mcs1 = cmin(cqi_to_mcs[UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id]], slice_maxmcs[slice_id]);
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// eNB_UE_stats->dlsch_mcs1 = cmin(cqi_to_mcs[UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id]], slice_maxmcs[slice_id]);
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eNB_UE_stats->dlsch_mcs1 = cmin(cqi2mcs(UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id]), slice_maxmcs[slice_id]);
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}
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@@ -266,6 +270,8 @@ assign_rbs_required(module_id_t Mod_id,
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Mod_id, frameP, UE_id, CC_id, min_rb_unit[CC_id],
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nb_rbs_required[CC_id][UE_id], TBS,
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eNB_UE_stats->dlsch_mcs1);
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pre_processor_results[slice_id].mcs[CC_id][UE_id] = eNB_UE_stats->dlsch_mcs1;
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}
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}
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}
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@@ -646,7 +652,7 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id,
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CC_id = UE_list->ordered_CCids[i][UE_id];
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ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id];
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cc = &RC.mac[Mod_id]->common_channels[CC_id];
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// TODO Can we use subframe2harqpid() here?
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// FIXME: Can we use subframe2harqpid() here?
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if (cc->tdd_Config)
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harq_pid = ((frameP * 10) + subframeP) % 10;
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else
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@@ -675,7 +681,7 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id,
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switch (slice_accounting[slice_id]) {
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// If greedy scheduling, try to account all the required RBs
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case 1:
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case POL_GREEDY:
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for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
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rnti = UE_RNTI(Mod_id, UE_id);
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if (rnti == NOT_A_RNTI) continue;
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@@ -691,6 +697,7 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id,
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// Use the old, fair algorithm
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// Loop over all active UEs and account the avg number of RBs to each UE, based on all non-retx UEs.
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// case POL_FAIR:
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default:
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// FIXME: This is not ideal, why loop on UEs to find average_rbs_per_user[], that is per-CC?
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// TODO: Look how to loop on active CCs only without using the UE_num_active_CC() function.
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@@ -1252,12 +1259,14 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
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#endif
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// Initialize scheduling information for all active UEs
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memset(&pre_processor_results[slice_id], 0, sizeof(pre_processor_results));
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// FIXME: After the memset above, some of the resets in reset() are redundant
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dlsch_scheduler_pre_processor_reset(Mod_id, slice_id, frameP, subframeP,
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min_rb_unit,
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nb_rbs_required,
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rballoc_sub,
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MIMO_mode_indicator,
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mbsfn_flag); // TODO Not sure if useful
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mbsfn_flag); // FIXME: Not sure if useful
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// STATUS
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// Store the DLSCH buffer for each logical channel
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@@ -1289,13 +1298,15 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id,
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// SHARING
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// If there are available RBs left in the slice, allocate them to the highest priority UEs
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dlsch_scheduler_pre_processor_intraslice_sharing(Mod_id, slice_id,
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min_rb_unit,
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nb_rbs_required,
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nb_rbs_accounted,
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nb_rbs_remaining,
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rballoc_sub,
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MIMO_mode_indicator);
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if (intraslice_share_active) {
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dlsch_scheduler_pre_processor_intraslice_sharing(Mod_id, slice_id,
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min_rb_unit,
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nb_rbs_required,
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nb_rbs_accounted,
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nb_rbs_remaining,
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rballoc_sub,
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MIMO_mode_indicator);
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}
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#ifdef TM5
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// This has to be revisited!!!!
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@@ -2075,3 +2086,7 @@ void sort_ue_ul(module_id_t module_idP, int frameP, sub_frame_t subframeP)
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UE_list->head_ul = -1;
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}
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}
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int cqi2mcs(int cqi) {
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return cqi_to_mcs[cqi];
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}
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