DL scheduler: correctly calculate mixed slot TDA, check TDA before scheduling
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@@ -100,7 +100,7 @@ void calculate_preferred_dl_tda(module_id_t module_id, const NR_BWP_Downlink_t *
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*tdaP_Mi->k0);
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int start, len;
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SLIV2SL(tdaP_Mi->startSymbolAndLength, &start, &len);
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const uint16_t symb_tda = ((1 << start) - 1) << start;
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const uint16_t symb_tda = ((1 << len) - 1) << start;
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// check whether coreset and TDA overlap: then, we cannot use it. Also,
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// check whether TDA is entirely within mixed slot DL. Note that
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// here we assume that the coreset is scheduled every slot (which it
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@@ -685,6 +685,11 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
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/* Get bwpSize from the first UE */
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int UE_id = UE_info->list.head;
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NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
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const int tda = RC.nrmac[module_id]->preferred_dl_tda[sched_ctrl->active_bwp->bwp_Id][slot];
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if (tda < 0)
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return;
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const uint16_t bwpSize = NRRIV2BW(sched_ctrl->active_bwp->bwp_Common->genericParameters.locationAndBandwidth, MAX_BWP_SIZE);
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uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map;
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