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Testing of NR PDCCH/PDSCH with RRC Configuration. added RRC configuration to NR UE. Updates to UE DCI procedures (moved to MAC) and updates to FAPI interfaces for UE. nr_dlsim is functional, added profiling information for gNB TX.

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This commit is contained in:
Raymond Knopp
2020-01-01 21:16:56 +01:00
parent 6bf81627e0
commit ad2667fbd5
55 changed files with 4704 additions and 5825 deletions
Download Patch File Download Diff File Expand all files Collapse all files
cmake_targets/CMakeLists.txt
+2 -2
View File
@@ -1205,7 +1205,6 @@ set(PHY_SRC_COMMON
${OPENAIR1_DIR}/PHY/LTE_REFSIG/lte_ul_ref.c
${OPENAIR1_DIR}/PHY/CODING/lte_segmentation.c
${OPENAIR1_DIR}/PHY/CODING/nr_segmentation.c
${OPENAIR1_DIR}/PHY/CODING/nr_compute_tbs.c
${OPENAIR1_DIR}/PHY/CODING/nr_rate_matching.c
${OPENAIR1_DIR}/PHY/CODING/ccoding_byte.c
${OPENAIR1_DIR}/PHY/CODING/ccoding_byte_lte.c
@@ -1646,6 +1645,7 @@ set (MAC_NR_SRC_UE
${NR_UE_MAC_DIR}/mac_vars.c
${NR_UE_MAC_DIR}/main_ue_nr.c
${NR_UE_MAC_DIR}/nr_ue_procedures.c
${NR_UE_MAC_DIR}/nr_ue_dci_configuration.c
)
set (ENB_APP_SRC
@@ -1700,7 +1700,7 @@ add_dependencies(L2_UE rrc_flag s1ap_flag x2_flag)
add_library( NR_L2_UE ${NR_L2_SRC_UE} ${MAC_NR_SRC_UE} )
add_library( MAC_NR_COMMON ${OPENAIR2_DIR}/LAYER2/NR_MAC_gNB/nr_mac_common.c )
add_library( MAC_NR_COMMON ${OPENAIR2_DIR}/LAYER2/NR_MAC_gNB/nr_mac_common.c ${OPENAIR2_DIR}/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c)
include_directories("${OPENAIR2_DIR}/NR_UE_PHY_INTERFACE")
include_directories("${OPENAIR2_DIR}/LAYER2/NR_MAC_UE")
common/utils/nr/nr_common.c
+7 -8
View File
@@ -37,8 +37,8 @@ int NRRIV2BW(int locationAndBandwidth,int N_RB) {
int tmp = locationAndBandwidth/N_RB;
int tmp2 = locationAndBandwidth%N_RB;
if (tmp <= (N_RB-tmp2+1)) return(tmp);
else return(N_RB-tmp);
if (tmp <= ((N_RB>>1)-tmp2+1)) return(tmp+1);
else return(N_RB+1-tmp);
}
@@ -46,15 +46,14 @@ int NRRIV2PRBOFFSET(int locationAndBandwidth,int N_RB) {
int tmp = locationAndBandwidth/N_RB;
int tmp2 = locationAndBandwidth%N_RB;
if (tmp <= (N_RB-tmp2+1)) return(tmp2);
else return(N_RB-tmp2);
if (tmp <= ((N_RB>>1)-tmp2+1)) return(tmp2);
else return(N_RB-1-tmp2);
}
int PRBalloc_to_locationandbandwidth0(int NPRB,int RBstart,int BWPsize) {
if (NPRB < 138)
return(BWPsize*(NPRB-1)+RBstart);
else
return(BWPsize*(BWPsize+1-NPRB) + (BWPsize-1-RBstart));
AssertFatal(NPRB>0 && (NPRB + RBstart <= BWPsize),"Illegal NPRB/RBstart Configuration (%d,%d)\n",NPRB,RBstart);
if (NPRB <= 1+(BWPsize>>1)) return(BWPsize*(NPRB-1)+RBstart);
else return(BWPsize*(BWPsize+1-NPRB) + (BWPsize-1-RBstart));
}
int PRBalloc_to_locationandbandwidth(int NPRB,int RBstart) {
common/utils/nr/nr_common.h
+18
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@@ -45,3 +45,21 @@ uint8_t nr_get_Qm(uint8_t Imcs, uint8_t table_idx);
uint32_t nr_get_code_rate(uint8_t Imcs, uint8_t table_idx);
int get_subband_size(int NPRB,int size);
void SLIV2SL(int SLIV,int *S,int *L);
#define CEILIDIV(a,b) ((a+b-1)/b)
#define ROUNDIDIV(a,b) (((a<<1)+b)/(b<<1))
#define cmax(a,b) ((a>b) ? (a) : (b))
#define cmax3(a,b,c) ((cmax(a,b)>c) ? (cmax(a,b)) : (c))
#define cmin(a,b) ((a<b) ? (a) : (b))
#ifdef __cplusplus
#ifdef min
#undef min
#undef max
#endif
#else
#define max(a,b) cmax(a,b)
#define min(a,b) cmin(a,b)
#endif
nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h
+5 -2
View File
@@ -8,6 +8,9 @@
#define FAPI_NR_MAX_NUM_ZP_CSI_RS_RESOURCE_PER_SET 16
#define FAPI_NR_MAX_NUM_CANDIDATE_BEAMS 16
#define FAPI_NR_MAX_RA_OCCASION_PER_CSIRS 64
// Constants Defined in 38.213
#define FAPI_NR_MAX_CORESET_PER_BWP 3
#define FAPI_NR_MAX_SS_PER_CORESET 10
/// RX_IND
@@ -41,8 +44,8 @@
#define FAPI_NR_DL_CONFIG_TYPE_DLSCH 0x02
#define CCE_REG_MAPPING_TYPE_INTERLEAVED 0x01
#define CCE_REG_MAPPING_TYPE_NON_INTERLEAVED 0x02
#define FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED 0x01
#define FAPI_NR_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED 0x02
#define PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE 0x01
#define PRECODER_GRANULARITY_ALL_CONTIGUOUS_RBS 0x02
nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
+26 -92
View File
@@ -31,77 +31,7 @@
typedef signed char int8_t;
*/
typedef struct {
uint8_t identifier_dci_formats ; // 0 IDENTIFIER_DCI_FORMATS:
uint8_t carrier_ind ; // 1 CARRIER_IND: 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213]
uint8_t sul_ind_0_1 ; // 2 SUL_IND_0_1:
uint8_t slot_format_ind ; // 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213]
uint8_t pre_emption_ind ; // 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits
uint8_t block_number ; // 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3
uint8_t close_loop_ind ; // 6 CLOSE_LOOP_IND:
uint8_t bandwidth_part_ind ; // 7 BANDWIDTH_PART_IND:
uint8_t short_message_ind ; // 8 SHORT_MESSAGE_IND:
uint8_t short_messages ; // 9 SHORT_MESSAGES:
uint16_t freq_dom_resource_assignment_UL; // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
// (NOTE 1) If DCI format 0_0 is monitored in common search space
// and if the number of information bits in the DCI format 0_0 prior to padding
// is larger than the payload size of the DCI format 1_0 monitored in common search space
// the bitwidth of the frequency domain resource allocation field in the DCI format 0_0
// is reduced such that the size of DCI format 0_0 equals to the size of the DCI format 1_0
uint16_t freq_dom_resource_assignment_DL; // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
uint8_t time_dom_resource_assignment ; // 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
// where I the number of entries in the higher layer parameter pusch-AllocationList
uint8_t vrb_to_prb_mapping ; // 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
uint8_t prb_bundling_size_ind ; // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214]
uint8_t rate_matching_ind ; // 15 RATE_MATCHING_IND: 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set
uint8_t zp_csi_rs_trigger ; // 16 ZP_CSI_RS_TRIGGER:
uint8_t freq_hopping_flag ; // 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
uint8_t tb1_mcs ; // 18 TB1_MCS:
uint8_t tb1_ndi ; // 19 TB1_NDI:
uint8_t tb1_rv ; // 20 TB1_RV:
uint8_t tb2_mcs ; // 21 TB2_MCS:
uint8_t tb2_ndi ; // 22 TB2_NDI:
uint8_t tb2_rv ; // 23 TB2_RV:
uint8_t mcs ; // 24 MCS:
uint8_t ndi ; // 25 NDI:
uint8_t rv ; // 26 RV:
uint8_t harq_process_number ; // 27 HARQ_PROCESS_NUMBER:
uint8_t dai ; // 28 DAI: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
// 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI
// 0 otherwise
uint8_t first_dai ; // 29 FIRST_DAI: (1 or 2 bits) 1 bit for semi-static HARQ-ACK
uint8_t second_dai ; // 30 SECOND_DAI: (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks
uint8_t tb_scaling ; // 31 TB_SCALING:
uint8_t tpc_pusch ; // 32 TPC_PUSCH:
uint8_t tpc_pucch ; // 33 TPC_PUCCH:
uint8_t pucch_resource_ind ; // 34 PUCCH_RESOURCE_IND:
uint8_t pdsch_to_harq_feedback_time_ind ; // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
uint8_t srs_resource_ind ; // 36 SRS_RESOURCE_IND:
uint8_t precod_nbr_layers ; // 37 PRECOD_NBR_LAYERS:
uint8_t antenna_ports ; // 38 ANTENNA_PORTS:
uint8_t tci ; // 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits
uint8_t srs_request ; // 40 SRS_REQUEST:
uint8_t tpc_cmd ; // 41 TPC_CMD:
uint8_t csi_request ; // 42 CSI_REQUEST:
uint8_t cbgti ; // 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH
uint8_t cbgfi ; // 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator
uint8_t ptrs_dmrs ; // 45 PTRS_DMRS:
uint8_t beta_offset_ind ; // 46 BETA_OFFSET_IND:
uint8_t dmrs_seq_ini ; // 47 DMRS_SEQ_INI: 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding
// is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise
uint8_t ul_sch_ind ; // 48 UL_SCH_IND: value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH
uint16_t padding_nr_dci ; // 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
// and if the number of information bits in the DCI format 0_0 prior to padding
// is less than the payload size of the DCI format 1_0 monitored in common search space
// zeros shall be appended to the DCI format 0_0
// until the payload size equals that of the DCI format 1_0
uint8_t sul_ind_0_0 ; // 50 SUL_IND_0_0:
uint8_t ra_preamble_index ; // 51 RA_PREAMBLE_INDEX:
uint8_t sul_ind_1_0 ; // 52 SUL_IND_1_0:
uint8_t ss_pbch_index ; // 53 SS_PBCH_INDEX
uint8_t prach_mask_index ; // 54 PRACH_MASK_INDEX
uint8_t reserved_nr_dci ; // 55 RESERVED_NR_DCI
} fapi_nr_dci_pdu_rel15_t;
@@ -120,16 +50,14 @@ typedef struct {
typedef struct {
/// frequency_domain_resource;
//uint32_t rb_start;
//uint32_t rb_end;
uint64_t frequency_domain_resource;
uint16_t rb_offset;
uint8_t frequency_domain_resource[6];
uint8_t StartSymbolIndex;
uint8_t duration;
uint8_t cce_reg_mapping_type; // interleaved or noninterleaved
uint8_t cce_reg_interleaved_reg_bundle_size; // valid if CCE to REG mapping type is interleaved type
uint8_t cce_reg_interleaved_interleaver_size; // valid if CCE to REG mapping type is interleaved type
uint8_t cce_reg_interleaved_shift_index; // valid if CCE to REG mapping type is interleaved type
uint8_t CceRegMappingType; // interleaved or noninterleaved
uint8_t RegBundleSize; // valid if CCE to REG mapping type is interleaved type
uint8_t InterleaverSize; // valid if CCE to REG mapping type is interleaved type
uint8_t ShiftIndex; // valid if CCE to REG mapping type is interleaved type
uint8_t CoreSetType;
uint8_t precoder_granularity;
uint16_t pdcch_dmrs_scrambling_id;
@@ -154,13 +82,16 @@ typedef struct {
int n_CCE;
// N_CCE is L, or number of CCEs for DCI
int N_CCE;
fapi_nr_dci_pdu_rel15_t dci;
uint8_t payloadSize;
uint8_t payloadBits[16];
//fapi_nr_dci_pdu_rel15_t dci;
} fapi_nr_dci_indication_pdu_t;
///
typedef struct {
uint32_t sfn_slot;
uint16_t SFN;
uint8_t slot;
uint16_t number_of_dcis;
fapi_nr_dci_indication_pdu_t dci_list[10];
} fapi_nr_dci_indication_t;
@@ -381,16 +312,15 @@ typedef struct {
typedef struct {
uint16_t rnti;
uint16_t BWPSize;
uint16_t BWPStart;
uint8_t SubcarrierSpacing;
fapi_nr_coreset_t coreset;
uint16_t N_RB_BWP;
uint32_t duration;
uint8_t number_of_candidates[5]; // aggregation level 1, 2, 4, 8, 16
uint16_t monitoring_symbols_within_slot;
// DCI foramt-specific
uint8_t format_2_0_number_of_candidates[5]; // aggregation level 1, 2, 4, 8, 16
uint8_t format_2_3_monitorying_periodicity;
uint8_t format_2_3_number_of_candidates;
uint8_t number_of_candidates;
uint16_t CCE[64];
uint8_t L[64];
uint8_t dci_length;
uint8_t dci_format;
} fapi_nr_dl_config_dci_dl_pdu_rel15_t;
typedef struct {
@@ -403,12 +333,16 @@ typedef struct{
typedef enum{vrb_to_prb_mapping_non_interleaved = 0, vrb_to_prb_mapping_interleaved = 1} vrb_to_prb_mapping_t;
//typedef fapi_nr_dci_pdu_rel15_t fapi_nr_dl_config_dlsch_pdu_rel15_t;
typedef struct {
uint8_t bandwidth_part_ind;
uint16_t BWPSize;
uint16_t BWPStart;
uint8_t SubcarrierSpacing;
uint16_t number_rbs;
uint16_t start_rb;
uint8_t frame_offset;
uint16_t number_symbols;
uint16_t start_symbol;
uint16_t dlDmrsSymbPos;
uint8_t dmrsConfigType;
uint8_t prb_bundling_size_ind;
uint8_t rate_matching_ind;
uint8_t zp_csi_rs_trigger;
openair1/PHY/CODING/nrPolar_tools/nr_polar_defs.h
+2 -1
View File
@@ -188,7 +188,8 @@ void nr_polar_print_polarParams(t_nrPolar_params *polarParams);
t_nrPolar_params *nr_polar_params (int8_t messageType,
uint16_t messageLength,
uint8_t aggregation_level,
int decoder_flag);
int decoder_flag,
t_nrPolar_params **polarList_ext);
uint16_t nr_polar_aggregation_prime (uint8_t aggregation_level);
openair1/PHY/CODING/nr_polar_init.c
+5 -3
View File
@@ -185,10 +185,12 @@ void nr_polar_print_polarParams(t_nrPolar_params *polarParams) {
t_nrPolar_params *nr_polar_params (int8_t messageType,
uint16_t messageLength,
uint8_t aggregation_level,
int decoding_flag) {
int decoding_flag,
t_nrPolar_params **polarList_ext) {
static t_nrPolar_params *polarList = NULL;
nr_polar_init(&polarList, messageType,messageLength,aggregation_level,decoding_flag);
t_nrPolar_params *polarParams=polarList;
nr_polar_init(polarList_ext != NULL ? polarList_ext : &polarList,
messageType,messageLength,aggregation_level,decoding_flag);
t_nrPolar_params *polarParams=polarList_ext != NULL ? *polarList_ext : polarList;
const int tag=messageType * messageLength * nr_polar_aggregation_prime(aggregation_level);
while (polarParams != NULL) {
openair1/PHY/CODING/nr_segmentation.c
+1 -1
View File
@@ -63,7 +63,7 @@ int32_t nr_segmentation(unsigned char *input_buffer,
#endif
}
if ((*C)>MAX_NUM_DLSCH_SEGMENTS) {
if ((*C)>MAX_NUM_NR_DLSCH_SEGMENTS) {
LOG_E(PHY,"nr_segmentation.c: too many segments %d, B %d, L %d, Bprime %d\n",*C,B,L,Bprime);
return(-1);
}
openair1/PHY/INIT/nr_init.c
+40 -43
View File
@@ -86,14 +86,12 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
LTE_eNB_PRACH *const prach_vars = &gNB->prach_vars;*/
int i;
int P=cfg->carrier_config.num_tx_ant.value;
int Ptx=cfg->carrier_config.num_tx_ant.value;
int Prx=cfg->carrier_config.num_rx_ant.value;
AssertFatal(P>0 && P<9,"P %d is not supported\n",P);
AssertFatal(Ptx>0 && Ptx<9,"Ptx %d is not supported\n",Ptx);
AssertFatal(Prx>0 && Prx<9,"Prx %d is not supported\n",Prx);
LOG_I(PHY,"[gNB %d] %s() About to wait for gNB to be configured\n", gNB->Mod_id, __FUNCTION__);
gNB->total_dlsch_bitrate = 0;
gNB->total_transmitted_bits = 0;
gNB->total_system_throughput = 0;
gNB->check_for_MUMIMO_transmissions=0;
while(gNB->configured == 0) usleep(10000);
@@ -157,21 +155,24 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
/// Transport init necessary for NR synchro
init_nr_transport(gNB);
gNB->first_run_I0_measurements =
1; ///This flag used to be static. With multiple gNBs this does no longer work, hence we put it in the structure. However it has to be initialized with 1, which is performed here.
common_vars->rxdata = (int32_t **)malloc16(P*sizeof(int32_t*));
common_vars->txdataF = (int32_t **)malloc16(P*sizeof(int32_t*));
common_vars->rxdataF = (int32_t **)malloc16(P*sizeof(int32_t*));
gNB->first_run_I0_measurements = 1;
for (i=0;i<P;i++){
common_vars->rxdata = (int32_t **)malloc16(Prx*sizeof(int32_t*));
common_vars->txdataF = (int32_t **)malloc16(Ptx*sizeof(int32_t*));
common_vars->rxdataF = (int32_t **)malloc16(Prx*sizeof(int32_t*));
for (i=0;i<Ptx;i++){
common_vars->txdataF[i] = (int32_t*)malloc16_clear(fp->samples_per_frame_wCP*sizeof(int32_t)); // [hna] samples_per_frame without CP
common_vars->rxdataF[i] = (int32_t*)malloc16_clear(fp->samples_per_frame_wCP*sizeof(int32_t));
common_vars->rxdata[i] = (int32_t*)malloc16_clear(fp->samples_per_frame*sizeof(int32_t));
LOG_D(PHY,"[INIT] common_vars->txdataF[%d] = %p (%lu bytes)\n",
i,common_vars->txdataF[i],
fp->samples_per_frame_wCP*sizeof(int32_t));
i,common_vars->txdataF[i],
fp->samples_per_frame_wCP*sizeof(int32_t));
}
for (i=0;i<Prx;i++){
common_vars->rxdataF[i] = (int32_t*)malloc16_clear(fp->samples_per_frame_wCP*sizeof(int32_t));
common_vars->rxdata[i] = (int32_t*)malloc16_clear(fp->samples_per_frame*sizeof(int32_t));
}
// Channel estimates for SRS
/*
@@ -202,22 +203,24 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
int N_RB_UL = cfg->carrier_config.ul_grid_size[cfg->ssb_config.scs_common.value].value;
printf("Before ULSCH init : %p\n",gNB->dlsch[0][0]->harq_processes[0]);
for (int ULSCH_id=0; ULSCH_id<NUMBER_OF_NR_ULSCH_MAX; ULSCH_id++) {
printf("ULSCH_id %d : %p\n",ULSCH_id,gNB->dlsch[0][0]->harq_processes[0]);
pusch_vars[ULSCH_id] = (NR_gNB_PUSCH *)malloc16_clear( sizeof(NR_gNB_PUSCH) );
pusch_vars[ULSCH_id]->rxdataF_ext = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->rxdataF_ext2 = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_estimates = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_estimates_ext = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_estimates_time = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->rxdataF_comp = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_mag0 = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_magb0 = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_mag = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_magb = (int32_t **)malloc16( fp->nb_antennas_rx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->rho = (int32_t **)malloc16_clear( fp->nb_antennas_rx*sizeof(int32_t*) );
pusch_vars[ULSCH_id]->rxdataF_ext = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->rxdataF_ext2 = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_estimates = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_estimates_ext = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_estimates_time = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->rxdataF_comp = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_mag0 = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_magb0 = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_mag = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->ul_ch_magb = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->rho = (int32_t **)malloc16_clear(Prx*sizeof(int32_t*) );
for (i=0; i<fp->nb_antennas_rx; i++) {
printf("ULSCH_id %d (before rx antenna alloc) : %p\n",ULSCH_id,gNB->dlsch[0][0]->harq_processes[0]);
for (i=0; i<Prx; i++) {
pusch_vars[ULSCH_id]->rxdataF_ext[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->rxdataF_ext2[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->ul_ch_estimates[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot );
@@ -230,14 +233,15 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
pusch_vars[ULSCH_id]->ul_ch_magb[i] = (int32_t *)malloc16_clear( fp->symbols_per_slot*sizeof(int32_t)*N_RB_UL*12 );
pusch_vars[ULSCH_id]->rho[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*(fp->N_RB_UL*12*7*2) );
}
pusch_vars[ULSCH_id]->llr = (int16_t *)malloc16_clear( (8*((3*8*6144)+12))*sizeof(int16_t) ); // [hna] 6144 is LTE and (8*((3*8*6144)+12)) is not clear
printf("ULSCH_id %d (before llr alloc) : %p\n",ULSCH_id,gNB->dlsch[0][0]->harq_processes[0]);
pusch_vars[ULSCH_id]->llr = (int16_t *)malloc16_clear( (8*((3*8*6144)+12))*sizeof(int16_t) ); // [hna] 6144 is LTE and (8*((3*8*6144)+12)) is not clear
printf("ULSCH_id %d (after llr alloc) : %p\n",ULSCH_id,gNB->dlsch[0][0]->harq_processes[0]);
} //ulsch_id
/*
for (ulsch_id=0; ulsch_id<NUMBER_OF_UE_MAX; ulsch_id++)
gNB->UE_stats_ptr[ulsch_id] = &gNB->UE_stats[ulsch_id];
*/
gNB->pdsch_config_dedicated->p_a = dB0; //defaul value until overwritten by RRCConnectionReconfiguration
printf("After ULSCH init : %p\n",gNB->dlsch[0][0]->harq_processes[0]);
return (0);
}
@@ -249,9 +253,9 @@ void phy_free_nr_gNB(PHY_VARS_gNB *gNB)
/*LTE_eNB_SRS *const srs_vars = gNB->srs_vars;
LTE_eNB_PRACH *const prach_vars = &gNB->prach_vars;*/
uint32_t ***pdcch_dmrs = gNB->nr_gold_pdcch_dmrs;
int P=gNB->gNB_config.carrier_config.num_tx_ant.value;
int Ptx=gNB->gNB_config.carrier_config.num_tx_ant.value;
for (int i = 0; i < P; i++) {
for (int i = 0; i < Ptx; i++) {
free_and_zero(common_vars->txdataF[i]);
/* rxdataF[i] is not allocated -> don't free */
}
@@ -440,14 +444,7 @@ void init_nr_transport(PHY_VARS_gNB *gNB) {
for (j=0; j<2; j++) {
gNB->dlsch[i][j] = new_gNB_dlsch(fp,1,16,NSOFT,0,grid_size);
if (!gNB->dlsch[i][j]) {
LOG_E(PHY,"Can't get gNB dlsch structures for UE %d \n", i);
exit(-1);
}/* else {
gNB->dlsch[i][j]->rnti=0;
LOG_D(PHY,"dlsch[%d][%d] => %p rnti:%d\n",i,j,gNB->dlsch[i][j], gNB->dlsch[i][j]->rnti);
}*/
AssertFatal(gNB->dlsch[i][j]!=NULL,"Can't initialize dlsch %d \n", i);
}
}
openair1/PHY/INIT/nr_init_ru.c
+2 -2
View File
@@ -82,7 +82,7 @@ int nr_phy_init_RU(RU_t *ru) {
// allocate precoding input buffers (TX)
ru->common.txdataF = (int32_t **)malloc16(ru->nb_tx**sizeof(int32_t*));
ru->common.txdataF = (int32_t **)malloc16(ru->nb_tx*sizeof(int32_t*));
for(i=0; i< ru->nb_tx; ++i) ru->common.txdataF[i] = (int32_t*)malloc16_clear(fp->samples_per_frame_wCP*sizeof(int32_t)); // [hna] samples_per_frame without CP
// allocate IFFT input buffers (TX)
@@ -126,7 +126,7 @@ int nr_phy_init_RU(RU_t *ru) {
int l_ind = 0;
for (i=0; i<RC.nb_nr_L1_inst; i++) {
for (p=0;p<nb_logical_antennas;p++) {
for (p=0;p<ru->nb_log_antennas;p++) {
if ((fp->L_ssb >> p) & 0x01) {
ru->beam_weights[i][p] = (int32_t **)malloc16_clear(ru->nb_tx*sizeof(int32_t*));
for (j=0; j<ru->nb_tx; j++) {
openair1/PHY/MODULATION/nr_modulation.c
+4 -3
View File
@@ -51,9 +51,10 @@ void nr_modulation(uint32_t *in,
}
void nr_layer_mapping(int16_t **mod_symbs,
uint8_t n_layers,
uint16_t n_symbs,
int16_t **tx_layers) {
uint8_t n_layers,
uint16_t n_symbs,
int16_t **tx_layers) {
LOG_D(PHY,"Doing layer mapping for %d layers, %d symbols\n",n_layers,n_symbs);
switch (n_layers) {
openair1/PHY/NR_REFSIG/nr_gold.c
+2 -1
View File
@@ -65,7 +65,7 @@ void nr_init_pdcch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid)
for (uint8_t symb=0; symb<fp->symbols_per_slot; symb++) {
reset = 1;
x2 = ((1<<17) * (14*slot+symb+1) * ((Nid<<1)+1) + (Nid<<1));
x2 = ((1<<17) * (14*slot+symb+1) * ((Nid<<1)+1)) + (Nid<<1);
for (uint32_t n=0; n<NR_MAX_PDCCH_DMRS_INIT_LENGTH_DWORD; n++) {
pdcch_dmrs[slot][symb][n] = lte_gold_generic(&x1, &x2, reset);
@@ -91,6 +91,7 @@ void nr_init_pdsch_dmrs(PHY_VARS_gNB* gNB, uint32_t Nid)
for (uint8_t symb=0; symb<fp->symbols_per_slot; symb++) {
reset = 1;
x2 = ((1<<17) * (fp->symbols_per_slot*slot+symb+1) * ((N_n_scid[n_scid]<<1)+1) +((N_n_scid[n_scid]<<1)+n_scid));
LOG_D(PHY,"DMRS slot %d, symb %d x2 %x\n",slot,symb,x2);
for (uint32_t n=0; n<NR_MAX_PDSCH_DMRS_INIT_LENGTH_DWORD; n++) {
pdsch_dmrs[slot][symb][0][n] = lte_gold_generic(&x1, &x2, reset);
reset = 0;
openair1/PHY/NR_REFSIG/nr_gold_ue.c
+2 -2
View File
@@ -100,7 +100,7 @@ void nr_gold_pdcch(PHY_VARS_NR_UE* ue,
x2 = (x2>>1) ^ (x2>>2) ^ (x2>>3) ^ (x2>>4);
x2 = x2 ^ (x2<<31) ^ (x2<<30) ^ (x2<<29) ^ (x2<<28);
ue->nr_gold_pdcch[0][ns][l][n] = x1^x2;
//printf("n=%d : c %x\n",n,x1^x2);
// if (ns==1 && l==0) printf("n=%d : c %x\n",n,x1^x2);
}
}
}
@@ -133,7 +133,7 @@ void nr_gold_pdsch(PHY_VARS_NR_UE* ue,
x2tmp0 = ((14*ns+(lbar+l)+1)*((nid<<1)+1))<<17;
x2 = (x2tmp0+(nid<<1)+nscid)%(1<<31); //cinit
LOG_D(PHY,"UE DMRS slot %d, symb %d, lbar %d, x2 %x, nscid %d\n",ns,l,lbar,x2,nscid);
//printf("ns %d gold pdsch x2 %d\n",ns,x2);
x1 = 1+ (1<<31);
openair1/PHY/NR_TRANSPORT/nr_dci.c
+20 -66
View File
@@ -137,7 +137,6 @@ void nr_pdcch_scrambling(uint32_t *in,
uint32_t x1, x2, s=0;
reset = 1;
x2 = (n_RNTI<<16) + Nid;
for (int i=0; i<size; i++) {
if ((i&0x1f)==0) {
s = lte_gold_generic(&x1, &x2, reset);
@@ -150,10 +149,10 @@ void nr_pdcch_scrambling(uint32_t *in,
}
(*out) ^= ((((*in)>>(i&0x1f))&1) ^ ((s>>(i&0x1f))&1))<<(i&0x1f);
//printf("nr_pdcch_scrambling: in %d seq 0x%08x => out %d\n",((*in)>>(i&0x1f))&1,s,((*out)>>(i&0x1f))&1);
}
}
uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
nfapi_nr_ul_dci_request_pdus_t *ul_dci_pdu,
uint32_t **gold_pdcch_dmrs,
@@ -165,9 +164,6 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
uint16_t cset_start_sc;
uint8_t cset_start_symb, cset_nsymb;
int k,l,k_prime,dci_idx, dmrs_idx;
nr_cce_t cce;
nr_reg_t reg;
nr_reg_t reg_mapping_list[NR_MAX_PDCCH_AGG_LEVEL*NR_NB_REG_PER_CCE];
/*First iteration: single DCI*/
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15;
@@ -202,13 +198,15 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
cset_start_symb = pdcch_pdu_rel15->StartSymbolIndex;
cset_nsymb = pdcch_pdu_rel15->DurationSymbols;
dci_idx = 0;
LOG_D(PHY, "Coreset rb_offset %d\n",rb_offset);
LOG_D(PHY, "Coreset rb_offset %d, nb_rb %d\n",rb_offset,n_rb);
LOG_D(PHY, "Coreset starting subcarrier %d on symbol %d (%d symbols)\n", cset_start_sc, cset_start_symb, cset_nsymb);
// DMRS length is per OFDM symbol
uint32_t dmrs_length = (pdcch_pdu_rel15->precoderGranularity == NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS)?
AssertFatal(pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED,
"Interleaved CCE REG MAPPING not supported\n");
uint32_t dmrs_length = (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED)?
(n_rb*6) : (pdcch_pdu_rel15->AggregationLevel[d]*36/cset_nsymb); //2(QPSK)*3(per RB)*6(REG per CCE)
uint32_t encoded_length = pdcch_pdu_rel15->AggregationLevel[d]*108; //2(QPSK)*9(per RB)*6(REG per CCE)
LOG_D(PHY, "DMRS length per symbol %d\t DCI encoded length %d\n", dmrs_length, encoded_length);
LOG_D(PHY, "DMRS length per symbol %d\t DCI encoded length %d (precoder_granularity %d,reg_mapping %d)\n", dmrs_length, encoded_length,pdcch_pdu_rel15->precoderGranularity,pdcch_pdu_rel15->CceRegMappingType);
dmrs_length += rb_offset*6; // To accommodate more DMRS symbols in case of rb offset
/// DMRS QPSK modulation
@@ -234,12 +232,12 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE,
pdcch_pdu_rel15->PayloadSizeBits[d],
pdcch_pdu_rel15->AggregationLevel[d],
0);
polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->Payload[d], encoder_output, pdcch_pdu_rel15->RNTI[d],1,currentPtr);
0,NULL);
polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->Payload[d], encoder_output, n_RNTI,1,currentPtr);
#ifdef DEBUG_CHANNEL_CODING
printf("polar rnti %d\n",pdcch_pdu_rel15->RNTI[d]);
printf("polar rnti %x,length %d, L %d\n",n_RNTI, pdcch_pdu_rel15->PayloadSizeBits[d],pdcch_pdu_rel15->AggregationLevel[d]);
printf("DCI PDU: [0]->0x%lx \t [1]->0x%lx\n",
pdcch_pdu.Payload[d][0], pdcch_pdu.Payload[d][1]);
((uint64_t*)pdcch_pdu_rel15->Payload[d])[0], ((uint64_t*)pdcch_pdu_rel15->Payload[d])[1]);
printf("Encoded Payload (length:%d dwords):\n", encoded_length>>5);
for (int i=0; i<encoded_length>>5; i++)
@@ -274,74 +272,30 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
/*Reorder REG list for a freq first mapping*/
uint8_t nb_regs = pdcch_pdu_rel15->AggregationLevel[d]*NR_NB_REG_PER_CCE;
/*
for (int cce_idx=pdcch_pdu_rel15->CceIndex;
cce_idx<(pdcch_pdu_rel15->CceIndex+pdcch_pdu_rel15->AggregationLevel[d]);
cce_idx++) {
cce = gNB->cce_list[cce_idx];
for (int reg_idx=0; reg_idx<NR_NB_REG_PER_CCE; reg_idx++) {
reg = cce.reg_list[reg_idx];
reg_mapping_list[reg_idx+cce_idx*NR_NB_REG_PER_CCE] = reg;
}
}
*/
if (pdcch_pdu_rel15->precoderGranularity == NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS) {
/*in this case the DMRS are mapped on all the coreset*/
for (l=cset_start_symb; l<cset_start_symb+ cset_nsymb; l++) {
// dmrs index depends on reference point for k according to 38.211 7.4.1.3.2
if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG)
dmrs_idx = 0;
else
dmrs_idx = rb_offset*3;
k = cset_start_sc + 1;
while (dmrs_idx<3*n_rb) {
((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = ((amp>>1) * mod_dmrs[l][dmrs_idx<<1]) >> 15;
((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = ((amp>>1) * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15;
#ifdef DEBUG_PDCCH_DMRS
printf("symbol %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1],
((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]);
#endif
k+=4;
if (k >= frame_parms.ofdm_symbol_size)
k -= frame_parms.ofdm_symbol_size;
dmrs_idx++;
}
}
}
/*Now mapping the encoded DCI based on newly constructed REG list
* and the DMRS for the precoder granularity same as REG bundle*/
/*Mapping the encoded DCI along with the DMRS */
for (int reg_idx=0; reg_idx<nb_regs; reg_idx++) {
reg = reg_mapping_list[reg_idx];
k = cset_start_sc + reg.start_sc_idx;
k = cset_start_sc + (12*reg_idx/cset_nsymb);
if (k >= frame_parms.ofdm_symbol_size)
k -= frame_parms.ofdm_symbol_size;
l = cset_start_symb + reg.symb_idx;
l = cset_start_symb + ((reg_idx/cset_nsymb)%cset_nsymb);
// dmrs index depends on reference point for k according to 38.211 7.4.1.3.2
if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG)
dmrs_idx = (reg.reg_idx/cset_nsymb)*3;
dmrs_idx = (reg_idx/cset_nsymb)*3;
else
dmrs_idx = ((reg.reg_idx/cset_nsymb)+rb_offset)*3;
dmrs_idx = ((reg_idx/cset_nsymb)+rb_offset)*3;
k_prime = 0;
for (int m=0; m<NR_NB_SC_PER_RB; m++) {
if ( m == (k_prime<<2)+1) { // DMRS if not already mapped
if (pdcch_pdu_rel15->precoderGranularity == NFAPI_NR_CSET_SAME_AS_REG_BUNDLE) {
((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = ((amp>>1) * mod_dmrs[l][dmrs_idx<<1]) >> 15;
((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = ((amp>>1) * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15;
if (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED) {
((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = (2*amp * mod_dmrs[l][dmrs_idx<<1]) >> 15;
((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (2*amp * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15;
#ifdef DEBUG_PDCCH_DMRS
printf("l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1],
printf("PDCCH DMRS: l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1],
((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]);
#endif
dmrs_idx++;
@@ -352,7 +306,7 @@ uint8_t nr_generate_dci_top(nfapi_nr_dl_tti_pdcch_pdu *pdcch_pdu,
((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = (amp * mod_dci[dci_idx<<1]) >> 15;
((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (amp * mod_dci[(dci_idx<<1) + 1]) >> 15;
#ifdef DEBUG_DCI
printf("l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1],
printf("PDCCH: l %d position %d => (%d,%d)\n",l,k,((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1],
((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]);
#endif
dci_idx++;
openair1/PHY/NR_TRANSPORT/nr_dci_tools.c
+1 -1
View File
@@ -32,7 +32,7 @@
#include "nr_dci.h"
#define DEBUG_FILL_DCI
//#define DEBUG_FILL_DCI
#include "nr_dlsch.h"
openair1/PHY/NR_TRANSPORT/nr_dlsch.c
+48 -34
View File
@@ -76,7 +76,14 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
int xOverhead,
time_stats_t *dlsch_encoding_stats,
time_stats_t *dlsch_scrambling_stats,
time_stats_t *dlsch_modulation_stats) {
time_stats_t *dlsch_modulation_stats,
time_stats_t *tinput,
time_stats_t *tprep,
time_stats_t *tparity,
time_stats_t *toutput,
time_stats_t *dlsch_rate_matching_stats,
time_stats_t *dlsch_interleaving_stats,
time_stats_t *dlsch_segmentation_stats) {
int harq_pid = 0;
NR_DL_gNB_HARQ_t *harq = dlsch->harq_processes[harq_pid];
@@ -85,15 +92,23 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
int16_t **mod_symbs = (int16_t**)dlsch->mod_symbs;
int16_t **tx_layers = (int16_t**)dlsch->txdataF;
int8_t Wf[2], Wt[2], l0, l_prime[2], delta;
uint16_t nb_symbols = rel15->NrOfSymbols;
uint8_t Qm = rel15->qamModOrder[0];
uint32_t encoded_length = nb_symbols*Qm;
uint8_t dmrs_Type = rel15->dmrsConfigType;
int nb_re_dmrs = (dmrs_Type== NFAPI_NR_DMRS_TYPE1) ? 6:4;
uint16_t n_dmrs = ((rel15->rbSize+rel15->rbStart)*nb_re_dmrs)<<1;
int16_t mod_dmrs[n_dmrs<<1];
uint16_t nb_re = ((12*rel15->NrOfSymbols)-nb_re_dmrs-xOverhead)*rel15->rbSize*rel15->NrOfCodewords;
uint8_t Qm = rel15->qamModOrder[0];
uint32_t encoded_length = nb_re*Qm;
/// CRC, coding, interleaving and rate matching
AssertFatal(harq->pdu!=NULL,"harq->pdu is null\n");
start_meas(dlsch_encoding_stats);
nr_dlsch_encoding(harq->pdu, frame, slot, dlsch, frame_parms);
nr_dlsch_encoding(harq->pdu, frame, slot, dlsch, frame_parms,tinput,tprep,tparity,toutput,
dlsch_rate_matching_stats,
dlsch_interleaving_stats,
dlsch_segmentation_stats);
stop_meas(dlsch_encoding_stats);
#ifdef DEBUG_DLSCH
printf("PDSCH encoding:\nPayload:\n");
@@ -111,6 +126,8 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
printf("\n");
#endif
/// scrambling
start_meas(dlsch_scrambling_stats);
for (int q=0; q<rel15->NrOfCodewords; q++)
@@ -142,8 +159,8 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
mod_symbs[q]);
stop_meas(dlsch_modulation_stats);
#ifdef DEBUG_DLSCH
printf("PDSCH Modulation: Qm %d(%d)\n", Qm, nb_symbols);
for (int i=0; i<nb_symbols>>3; i++) {
printf("PDSCH Modulation: Qm %d(%d)\n", Qm, nb_re);
for (int i=0; i<nb_re>>3; i++) {
for (int j=0; j<8; j++) {
printf("%d %d\t", mod_symbs[0][((i<<3)+j)<<1], mod_symbs[0][(((i<<3)+j)<<1)+1]);
}
@@ -155,53 +172,50 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
/// Layer mapping
nr_layer_mapping(mod_symbs,
rel15->nrOfLayers,
nb_symbols,
nb_re,
tx_layers);
#ifdef DEBUG_DLSCH
printf("Layer mapping (%d layers):\n", rel15->nrOfLayers);
for (int l=0; l<rel15->nrOfLayers; l++)
for (int i=0; i<(nb_symbols/rel15->nrOfLayers)>>3; i++) {
for (int i=0; i<(nb_re/rel15->nrOfLayers)>>3; i++) {
printf("layer %d, Re %d..%d : ",l,i<<3,(i<<3)+7);
for (int j=0; j<8; j++) {
printf("%d %d\t", tx_layers[l][((i<<3)+j)<<1], tx_layers[l][(((i<<3)+j)<<1)+1]);
printf("l%d %d\t", tx_layers[l][((i<<3)+j)<<1], tx_layers[l][(((i<<3)+j)<<1)+1]);
}
printf("\n");
}
#endif
/// Antenna port mapping
//to be moved to init phase potentially, for now tx_layers 1-8 are mapped on antenna ports 1000-1007
//to be moved to init phase potentially, for now tx_layers 1-8 are mapped on antenna ports 1000-1007
/// DMRS QPSK modulation
uint8_t dmrs_Type = rel15->dmrsConfigType;
int nb_re_dmrs = (dmrs_Type==1) ? 6:4;
uint16_t n_dmrs = ((rel15->rbSize+rel15->rbStart)*nb_re_dmrs)<<1;
int16_t mod_dmrs[n_dmrs<<1];
l0 = get_l0(rel15->dlDmrsSymbPos);
nr_modulation(pdsch_dmrs[l0][0], n_dmrs, DMRS_MOD_ORDER, mod_dmrs); // currently only codeword 0 is modulated. Qm = 2 as DMRS is QPSK modulated
l0 = get_l0(rel15->dlDmrsSymbPos);
nr_modulation(pdsch_dmrs[l0][0], n_dmrs, DMRS_MOD_ORDER, mod_dmrs); // currently only codeword 0 is modulated. Qm = 2 as DMRS is QPSK modulated
#ifdef DEBUG_DLSCH
printf("DMRS modulation (single symbol %d, %d symbols, type %d):\n", l0, n_dmrs>>1, dmrs_Type);
for (int i=0; i<n_dmrs>>4; i++) {
for (int j=0; j<8; j++) {
printf("%d %d\t", mod_dmrs[((i<<3)+j)<<1], mod_dmrs[(((i<<3)+j)<<1)+1]);
printf("DMRS modulation (single symbol %d, %d symbols, type %d):\n", l0, n_dmrs>>1, dmrs_Type);
for (int i=0; i<n_dmrs>>4; i++) {
for (int j=0; j<8; j++) {
printf("%d %d\t", mod_dmrs[((i<<3)+j)<<1], mod_dmrs[(((i<<3)+j)<<1)+1]);
}
printf("\n");
}
printf("\n");
}
#endif
/// Resource mapping
// Non interleaved VRB to PRB mapping
uint16_t start_sc = frame_parms->first_carrier_offset + rel15->rbStart*NR_NB_SC_PER_RB;
if (start_sc >= frame_parms->ofdm_symbol_size)
start_sc -= frame_parms->ofdm_symbol_size;
#ifdef DEBUG_DLSCH_MAPPING
printf("PDSCH resource mapping started (start SC %d\tstart symbol %d\tN_PRB %d\tnb_symbols %d)\n",
start_sc, rel15->StartSymbolIndex, rel15->rbSize, rel15->NrOfSymbols);
printf("PDSCH resource mapping started (start SC %d\tstart symbol %d\tN_PRB %d\tnb_re %d,nb_layers %d)\n",
start_sc, rel15->StartSymbolIndex, rel15->rbSize, nb_re,rel15->nrOfLayers);
#endif
for (int ap=0; ap<rel15->nrOfLayers; ap++) {
@@ -212,8 +226,8 @@ for (int i=0; i<n_dmrs>>4; i++) {
l_prime[0] = 0; // single symbol ap 0
uint8_t dmrs_symbol = l0+l_prime[0];
#ifdef DEBUG_DLSCH_MAPPING
printf("DMRS params for ap %d: Wt %d %d \t Wf %d %d \t delta %d \t l_prime %d \t l0 %d\tDMRS symbol %d\n",
ap, Wt[0], Wt[1], Wf[0], Wf[1], delta, l_prime[0], l0, dmrs_symbol);
printf("DMRS Type %d params for ap %d: Wt %d %d \t Wf %d %d \t delta %d \t l_prime %d \t l0 %d\tDMRS symbol %d\n",
1+dmrs_Type,ap, Wt[0], Wt[1], Wf[0], Wf[1], delta, l_prime[0], l0, dmrs_symbol);
#endif
uint8_t k_prime=0;
uint16_t m=0, n=0, dmrs_idx=0, k=0;
openair1/PHY/NR_TRANSPORT/nr_dlsch.h
+18 -4
View File
@@ -79,7 +79,14 @@ uint8_t nr_generate_pdsch(NR_gNB_DLSCH_t *dlsch,
int xOverhead,
time_stats_t *dlsch_encoding_stats,
time_stats_t *dlsch_scrambling_stats,
time_stats_t *dlsch_modulation_stats);
time_stats_t *dlsch_modulation_stats,
time_stats_t *tinput,
time_stats_t *tprep,
time_stats_t *tparity,
time_stats_t *toutput,
time_stats_t *dlsch_rate_matching_stats,
time_stats_t *dlsch_interleaving_stats,
time_stats_t *dlsch_segmentation_stats);
void free_gNB_dlsch(NR_gNB_DLSCH_t *dlsch);
@@ -91,9 +98,16 @@ void clean_gNB_ulsch(NR_gNB_ULSCH_t *ulsch);
int16_t find_nr_dlsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type);
int nr_dlsch_encoding(unsigned char *a,int frame,
uint8_t slot,
NR_gNB_DLSCH_t *dlsch,
NR_DL_FRAME_PARMS* frame_parms);
uint8_t slot,
NR_gNB_DLSCH_t *dlsch,
NR_DL_FRAME_PARMS* frame_parms,
time_stats_t *tinput,
time_stats_t *tprep,
time_stats_t *tparity,
time_stats_t *toutput,
time_stats_t *dlsch_rate_matching_stats,
time_stats_t *dlsch_interleaving_stats,
time_stats_t *dlsch_segmentation_stats);
void nr_emulate_dlsch_payload(uint8_t* payload, uint16_t size);
openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c
+25 -26
View File
@@ -70,7 +70,7 @@ void free_gNB_dlsch(NR_gNB_DLSCH_t *dlsch)
#endif
if (dlsch->harq_processes[i]->b) {
free16(dlsch->harq_processes[i]->b,MAX_DLSCH_PAYLOAD_BYTES); //this should be MAX_NR_DLSCH_PAYLOAD_BYTES
free16(dlsch->harq_processes[i]->b,MAX_NR_DLSCH_PAYLOAD_BYTES); //this should be MAX_NR_DLSCH_PAYLOAD_BYTES
dlsch->harq_processes[i]->b = NULL;
#ifdef DEBUG_DLSCH_FREE
LOG_D(PHY,"Freeing dlsch process %d b (%p)\n",i,dlsch->harq_processes[i]->b);
@@ -81,7 +81,7 @@ void free_gNB_dlsch(NR_gNB_DLSCH_t *dlsch)
LOG_D(PHY,"Freeing dlsch process %d c (%p)\n",i,dlsch->harq_processes[i]->c);
#endif
for (r=0; r<MAX_NUM_DLSCH_SEGMENTS; r++) {
for (r=0; r<MAX_NUM_NR_DLSCH_SEGMENTS; r++) {
#ifdef DEBUG_DLSCH_FREE
LOG_D(PHY,"Freeing dlsch process %d c[%d] (%p)\n",i,r,dlsch->harq_processes[i]->c[r]);
@@ -121,17 +121,8 @@ NR_gNB_DLSCH_t *new_gNB_dlsch(NR_DL_FRAME_PARMS *frame_parms,
int re;
unsigned char bw_scaling =1;
switch (N_RB) {
case 106:
bw_scaling =2;
break;
default:
bw_scaling =1;
break;
}
if (N_RB <= 107) bw_scaling =2;
dlsch = (NR_gNB_DLSCH_t *)malloc16(sizeof(NR_gNB_DLSCH_t));
if (dlsch) {
@@ -260,7 +251,7 @@ void clean_gNB_dlsch(NR_gNB_DLSCH_t *dlsch)
dlsch->harq_processes[i]->round = 0;
for (j=0; j<96; j++)
for (r=0; r<MAX_NUM_DLSCH_SEGMENTS; r++)
for (r=0; r<MAX_NUM_NR_DLSCH_SEGMENTS; r++)
if (dlsch->harq_processes[i]->d[r])
dlsch->harq_processes[i]->d[r][j] = NR_NULL;
@@ -273,7 +264,10 @@ int nr_dlsch_encoding(unsigned char *a,
int frame,
uint8_t slot,
NR_gNB_DLSCH_t *dlsch,
NR_DL_FRAME_PARMS* frame_parms)
NR_DL_FRAME_PARMS* frame_parms,
time_stats_t *tinput,time_stats_t *tprep,time_stats_t *tparity,time_stats_t *toutput,
time_stats_t *dlsch_rate_matching_stats,time_stats_t *dlsch_interleaving_stats,
time_stats_t *dlsch_segmentation_stats)
{
unsigned int G;
@@ -293,7 +287,7 @@ int nr_dlsch_encoding(unsigned char *a,
uint32_t E;
uint8_t Ilbrm = 1;
uint32_t Tbslbrm = 950984; //max tbs
uint8_t nb_re_dmrs = rel15->dmrsConfigType==1 ? 6:4;
uint8_t nb_re_dmrs = rel15->dmrsConfigType==NFAPI_NR_DMRS_TYPE1 ? 6:4;
uint16_t length_dmrs = get_num_dmrs(rel15->dlDmrsSymbPos);
uint16_t R=rel15->targetCodeRate[0];
float Coderate = 0.0;
@@ -339,7 +333,7 @@ int nr_dlsch_encoding(unsigned char *a,
dlsch->harq_processes[harq_pid]->B = A+24;
// dlsch->harq_processes[harq_pid]->b = a;
AssertFatal((A/8)+4 <= MAX_DLSCH_PAYLOAD_BYTES,"A %d is too big (A/8+4 = %d > %d)\n",A,(A/8)+4,MAX_DLSCH_PAYLOAD_BYTES);
AssertFatal((A/8)+3 <= MAX_NR_DLSCH_PAYLOAD_BYTES,"A %d is too big (A/8+4 = %d > %d)\n",A,(A/8)+4,MAX_NR_DLSCH_PAYLOAD_BYTES);
memcpy(dlsch->harq_processes[harq_pid]->b,a,(A/8)+4); // why is this +4 if the CRC is only 3 bytes?
}
@@ -354,7 +348,7 @@ int nr_dlsch_encoding(unsigned char *a,
dlsch->harq_processes[harq_pid]->B = A+16;
// dlsch->harq_processes[harq_pid]->b = a;
AssertFatal((A/8)+3 <= MAX_DLSCH_PAYLOAD_BYTES,"A %d is too big (A/8+3 = %d > %d)\n",A,(A/8)+3,MAX_DLSCH_PAYLOAD_BYTES);
AssertFatal((A/8)+3 <= MAX_NR_DLSCH_PAYLOAD_BYTES,"A %d is too big (A/8+3 = %d > %d)\n",A,(A/8)+3,MAX_NR_DLSCH_PAYLOAD_BYTES);
memcpy(dlsch->harq_processes[harq_pid]->b,a,(A/8)+3); // using 3 bytes to mimic the case of 24 bit crc
}
@@ -368,6 +362,7 @@ int nr_dlsch_encoding(unsigned char *a,
else
BG = 1;
start_meas(dlsch_segmentation_stats);
Kb = nr_segmentation(dlsch->harq_processes[harq_pid]->b,
dlsch->harq_processes[harq_pid]->c,
dlsch->harq_processes[harq_pid]->B,
@@ -376,7 +371,7 @@ int nr_dlsch_encoding(unsigned char *a,
Zc,
&dlsch->harq_processes[harq_pid]->F,
BG);
stop_meas(dlsch_segmentation_stats);
F = dlsch->harq_processes[harq_pid]->F;
Kr = dlsch->harq_processes[harq_pid]->K;
@@ -405,7 +400,9 @@ int nr_dlsch_encoding(unsigned char *a,
}
for(int j=0;j<(dlsch->harq_processes[harq_pid]->C/8+1);j++) {
ldpc_encoder_optim_8seg_multi(dlsch->harq_processes[harq_pid]->c,dlsch->harq_processes[harq_pid]->d,*Zc,Kb,Kr,BG,dlsch->harq_processes[harq_pid]->C,j,NULL,NULL,NULL,NULL);
ldpc_encoder_optim_8seg_multi(dlsch->harq_processes[harq_pid]->c,dlsch->harq_processes[harq_pid]->d,*Zc,Kb,Kr,BG,
dlsch->harq_processes[harq_pid]->C,j,
tinput,tprep,tparity,toutput);
}
@@ -446,6 +443,7 @@ int nr_dlsch_encoding(unsigned char *a,
Tbslbrm = nr_compute_tbslbrm(rel15->mcsTable[0],nb_rb,Nl,dlsch->harq_processes[harq_pid]->C);
start_meas(dlsch_rate_matching_stats);
nr_rate_matching_ldpc(Ilbrm,
Tbslbrm,
BG,
@@ -455,17 +453,18 @@ int nr_dlsch_encoding(unsigned char *a,
dlsch->harq_processes[harq_pid]->C,
rel15->rvIndex[0],
E);
stop_meas(dlsch_rate_matching_stats);
#ifdef DEBUG_DLSCH_CODING
for (int i =0; i<16; i++)
LOG_D(PHY,"output ratematching e[%d]= %d r_offset %d\n", i,dlsch->harq_processes[harq_pid]->e[i+r_offset], r_offset);
#endif
nr_interleaving_ldpc(E,
mod_order,
dlsch->harq_processes[harq_pid]->e+r_offset,
dlsch->harq_processes[harq_pid]->f+r_offset);
start_meas(dlsch_interleaving_stats);
nr_interleaving_ldpc(E,
mod_order,
dlsch->harq_processes[harq_pid]->e+r_offset,
dlsch->harq_processes[harq_pid]->f+r_offset);
stop_meas(dlsch_interleaving_stats);
#ifdef DEBUG_DLSCH_CODING
for (int i =0; i<16; i++)
openair1/PHY/NR_TRANSPORT/nr_pbch.c
+1 -1
View File
@@ -299,7 +299,7 @@ int nr_generate_pbch(NR_gNB_PBCH *pbch,
/// CRC, coding and rate matching
polar_encoder_fast (&a_reversed, (uint32_t *)pbch->pbch_e, 0, 0,
nr_polar_params( NR_POLAR_PBCH_MESSAGE_TYPE, NR_POLAR_PBCH_PAYLOAD_BITS, NR_POLAR_PBCH_AGGREGATION_LEVEL,0)
nr_polar_params( NR_POLAR_PBCH_MESSAGE_TYPE, NR_POLAR_PBCH_PAYLOAD_BITS, NR_POLAR_PBCH_AGGREGATION_LEVEL,0,NULL)
);
#ifdef DEBUG_PBCH_ENCODING
printf("Channel coding:\n");
openair1/PHY/NR_TRANSPORT/nr_transport_common_proto.h
-3
View File
@@ -36,9 +36,6 @@
#include "PHY/defs_nr_common.h"
#define MAX_NUM_NR_DLSCH_SEGMENTS 16
#define MAX_NUM_NR_ULSCH_SEGMENTS MAX_NUM_NR_DLSCH_SEGMENTS
#define NR_PUSCH_x 2 // UCI placeholder bit TS 38.212 V15.4.0 subclause 5.3.3.1
#define NR_PUSCH_y 3 // UCI placeholder bit
openair1/PHY/NR_TRANSPORT/nr_transport_proto_common.h
-50
View File
@@ -1728,41 +1728,6 @@ void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8
uint32_t lte_gold_generic(uint32_t *x1, uint32_t *x2, uint8_t reset);
uint8_t nr_dci_decoding_procedure(int s,
int p,
PHY_VARS_NR_UE *ue,
NR_DCI_ALLOC_t *dci_alloc,
NR_SEARCHSPACE_TYPE_t searchSpacetype,
int16_t eNB_id,
uint8_t nr_tti_rx,
uint8_t dci_fields_sizes_cnt[MAX_NR_DCI_DECODED_SLOT][NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
uint16_t n_RB_ULBWP,
uint16_t n_RB_DLBWP,
crc_scrambled_t *crc_scrambled,
format_found_t *format_found,
uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES]);
int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue,
uint8_t eNB_id,
int frame,
uint8_t nr_tti_rx,
uint64_t dci_pdu[2],
uint16_t rnti,
uint8_t dci_length,
NR_DCI_format_t dci_format,
NR_UE_PDCCH *pdcch_vars,
NR_UE_PDSCH *pdsch_vars,
NR_UE_DLSCH_t **dlsch,
NR_UE_ULSCH_t *ulsch,
NR_DL_FRAME_PARMS *frame_parms,
PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated,
uint8_t beamforming_mode,
uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
uint16_t n_RB_ULBWP,
uint16_t n_RB_DLBWP,
uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES],
NR_DCI_INFO_EXTRACTED_t *nr_dci_info_extracted);
int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
PDSCH_t type,
unsigned char eNB_id,
@@ -1789,20 +1754,5 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
uint8_t is_crnti,
uint8_t llr8_flag);
int nr_extract_dci_info(PHY_VARS_NR_UE *ue,
uint8_t eNB_id,
lte_frame_type_t frame_type,
uint8_t dci_length,
uint16_t rnti,
uint64_t dci_pdu[2],
fapi_nr_dci_pdu_rel15_t *nr_pdci_info_extracted,
uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
NR_DCI_format_t dci_format,
uint8_t nr_tti_rx,
uint16_t n_RB_ULBWP,
uint16_t n_RB_DLBWP,
uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES]);
/**@}*/
#endif
openair1/PHY/NR_UE_ESTIMATION/nr_dl_channel_estimation.c
+6 -8
View File
@@ -475,7 +475,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
unsigned short coreset_start_subcarrier,
unsigned short nb_rb_coreset)
{
int pilot[200] __attribute__((aligned(16)));
unsigned char aarx;
unsigned short k;
unsigned int pilot_cnt;
@@ -484,12 +484,9 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
//uint16_t Nid_cell = (eNB_offset == 0) ? ue->frame_parms.Nid_cell : ue->measurements.adj_cell_id[eNB_offset-1];
uint8_t nushift;
int **dl_ch_estimates =ue->pdcch_vars[ue->current_thread_id[Ns]][eNB_offset]->dl_ch_estimates;
int **rxdataF=ue->common_vars.common_vars_rx_data_per_thread[ue->current_thread_id[Ns]].rxdataF;
nushift = 1;
ue->frame_parms.nushift = nushift;
if (ue->high_speed_flag == 0) // use second channel estimate position for temporary storage
ch_offset = ue->frame_parms.ofdm_symbol_size ;
@@ -510,14 +507,15 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
fr = filt16a_r1;
// generate pilot
// generate pilot
int pilot[nb_rb_coreset * 3] __attribute__((aligned(16)));
nr_pdcch_dmrs_rx(ue,eNB_offset,Ns,ue->nr_gold_pdcch[eNB_offset][Ns][symbol], &pilot[0],2000,nb_rb_coreset);
for (aarx=0; aarx<ue->frame_parms.nb_antennas_rx; aarx++) {
pil = (int16_t *)&pilot[0];
rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+k+nushift)];
rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+k+1)];
dl_ch = (int16_t *)&dl_ch_estimates[aarx][ch_offset];
memset(dl_ch,0,4*(ue->frame_parms.ofdm_symbol_size));
@@ -588,7 +586,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
if (k >= ue->frame_parms.ofdm_symbol_size){
k-=ue->frame_parms.ofdm_symbol_size;
rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+k+nushift)];}
rxF = (int16_t *)&rxdataF[aarx][(symbol_offset+k+1)];}
ch[0] = (int16_t)(((int32_t)pil[0]*rxF[0] - (int32_t)pil[1]*rxF[1])>>15);
ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15);
@@ -622,7 +620,7 @@ int nr_pdcch_channel_estimation(PHY_VARS_NR_UE *ue,
ch[1] = (int16_t)(((int32_t)pil[0]*rxF[1] + (int32_t)pil[1]*rxF[0])>>15);
#ifdef DEBUG_PDCCH
printf("pilot 1 : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]);
printf("pilot %d : rxF - > (%d,%d) ch -> (%d,%d), pil -> (%d,%d) \n",pilot_cnt+2,rxF[0],rxF[1],ch[0],ch[1],pil[0],pil[1]);
#endif
multadd_real_vector_complex_scalar(fr,
openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
+276 -1225
View File
File diff suppressed because it is too large Load Diff
openair1/PHY/NR_UE_TRANSPORT/dci_tools_nr.c
-914
View File
@@ -53,924 +53,11 @@
//#define DEBUG_DCI
#define NR_PDCCH_DCI_TOOLS
//#define NR_PDCCH_DCI_TOOLS_DEBUG
#ifdef NR_PDCCH_DCI_TOOLS_DEBUG
#define LOG_DCI_D(a...) printf("\t\t<-NR_PDCCH_DCI_TOOLS_DEBUG (nr_extract_dci_info) ->" a)
#else
#define LOG_DCI_D(a...)
#endif
#define LOG_DCI_PARM(a...) LOG_D(PHY,"\t<-NR_PDCCH_DCI_TOOLS_DEBUG (nr_generate_ue_ul_dlsch_params_from_dci)" a)
typedef unsigned __int128 uint128_t;
int8_t nr_delta_PUSCH_abs[4] = {-4,-1,1,4};
int8_t nr_delta_PUSCH_acc[4] = {-1,0,1,3};
int8_t *nr_delta_PUCCH_lut = nr_delta_PUSCH_acc;
#ifdef NR_PDCCH_DCI_TOOLS
uint16_t nr_dci_field(uint64_t dci_pdu[2],
uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS],
uint8_t dci_field) {
int dci_size=0;
for (int i=0; i<NBR_NR_DCI_FIELDS; i++) dci_size+=dci_fields_sizes[i];
AssertFatal(dci_size<65,"DCI has %d > 64 bits, not supported for now\n",
dci_size);
uint16_t first_bit_position = dci_size;
for (int i=0; i<=dci_field ; i++) {
first_bit_position = first_bit_position - dci_fields_sizes[i];
}
/*uint16_t tmp1 = ((*dci_pdu>>first_bit_position)&((1<<dci_fields_sizes[dci_field])-1));
uint16_t tmp2 = 0;
for (int i=0; i<dci_fields_sizes[dci_field]; i++)
tmp2 |= ((tmp1>>i)&1)<<(dci_fields_sizes[dci_field]-i-1);*/
return ((uint16_t)(*dci_pdu>>first_bit_position)&((1<<dci_fields_sizes[dci_field])-1));
}
int nr_extract_dci_info(PHY_VARS_NR_UE *ue,
uint8_t eNB_id,
lte_frame_type_t frame_type,
uint8_t dci_length,
uint16_t rnti,
uint64_t dci_pdu[2],
fapi_nr_dci_pdu_rel15_t *nr_pdci_info_extracted,
uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
NR_DCI_format_t dci_format,
uint8_t nr_tti_rx,
uint16_t n_RB_ULBWP,
uint16_t n_RB_DLBWP,
uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES]) {
/*
* This function will extract the different elements of the dci pdu and interpret the values extracted to update correctly the parameters in:
* NR_DL_UE_HARQ_t *pdlsch0_harq,
* NR_UE_DLSCH_t *pdlsch0,
*
* We need to know the dci length and the dci_fields_sizes (array containing each field size in number of bits)
* In order to get the value of a specific field we will proceed as follows (let's have a look to an example:
* If the length of the pdu is 38 bits and the content of the dci_pdu is 0x3A8900789A (pdu is 11 1010 1000 1001 0000 0000 0111 1000 1001 1010)
* If the dci_fields_sizes is {0 0 1 0 0 0 0 0 0 13 0 1 0 0 0 0 0 0 0 0 0 0 5 1 2 4 2 0 0 0 2 3 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...}
* This means:
* number bits for carrier_ind field is 0
* number bits for sul_ind_0_1 field is 0
* number bits for identifier_dci_formats field is 0
* number bits for slot_format_ind field is 0
* number bits for pre_emption_ind field is 0
* ...
* number bits for freq_dom_resource_assignment_DL field is 13
* ...
* number bits for padding is 0
* In order to extract the information of (e.g.) freq_dom_resource_assignment_DL field,
* we will do a left-shift of 1 position (because previous to this field, and according to the dci_fields_sizes array, there is only one non-empty field of size 1 bit) -> (1 1010 1000 1001 0000 0000 0111 1000 1001 1010 0)
* then we will do a right-shit of dci_length-13 positions -> (1 1010 1000 1001). And this is the content of the freq_dom_resource_assignment_DL field
*
*
* At the moment we have implemented the following formats:
*
* Format 0_0, that contains the following fields according to Specification 38.212 V15.1.1 Section 7.3.1
* with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI or TC-RNTI
* 0 IDENTIFIER_DCI_FORMATS:
* 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
* 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
* 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
* 24 MCS:
* 25 NDI:
* 26 RV:
* 27 HARQ_PROCESS_NUMBER:
* 32 TPC_PUSCH:
* 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
* 50 SUL_IND_0_0:
*
* Format 0_1, that contains the following fields
* with CRC scrambled by C-RNTI or CS-RNTI or SP-CSI-RNTI or new-RNTI
* 0 IDENTIFIER_DCI_FORMATS:
* 1 CARRIER_IND
* 2 SUL_IND_0_1
* 7 BANDWIDTH_PART_IND
* 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
* 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
* 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
* 24 MCS:
* 25 NDI:
* 26 RV:
* 27 HARQ_PROCESS_NUMBER:
* 29 FIRST_DAI
* 30 SECOND_DAI
* 32 TPC_PUSCH:
* 36 SRS_RESOURCE_IND:
* 37 PRECOD_NBR_LAYERS:
* 38 ANTENNA_PORTS:
* 40 SRS_REQUEST:
* 42 CSI_REQUEST:
* 43 CBGTI
* 45 PTRS_DMRS
* 46 BETA_OFFSET_IND
* 47 DMRS_SEQ_INI
* 48 UL_SCH_IND
* 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
*
* Format 1_0, that contains the following fields
* with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI
* 0 IDENTIFIER_DCI_FORMATS:
* 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
* 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
* 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
* 24 MCS:
* 25 NDI:
* 26 RV:
* 27 HARQ_PROCESS_NUMBER:
* 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
* 33 TPC_PUCCH:
* 34 PUCCH_RESOURCE_IND:
* 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
* 55 RESERVED_NR_DCI
*
* If the CRC of the DCI format 1_0 is scrambled by C-RNTI and the "Frequency domain resource assignment" field are of all ones,
* the DCI format 1_0 is for random access procedure initiated by a PDCCH order.
* This is not implemented, but the fields are already included: FIXME!!!
*
* with CRC scrambled by P-RNTI
* 8 SHORT_MESSAGE_IND
* 9 SHORT_MESSAGES
* 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
* 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
* 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
* 24 MCS:
* 31 TB_SCALING
* 55 RESERVED_NR_DCI
*
* with CRC scrambled by SI-RNTI
* 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
* 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
* 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
* 24 MCS:
* 26 RV:
* 55 RESERVED_NR_DCI
*
* with CRC scrambled by RA-RNTI
* 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
* 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
* 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
* 24 MCS:
* 31 TB_SCALING
* 55 RESERVED_NR_DCI
*
* with CRC scrambled by TC-RNTI
* 0 IDENTIFIER_DCI_FORMATS:
* 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
* 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
* 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
* 24 MCS:
* 25 NDI:
* 26 RV:
* 27 HARQ_PROCESS_NUMBER:
* 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
* 33 TPC_PUCCH:
*
* Format 1_1, that contains the following fields
* with CRC scrambled by C-RNTI or CS-RNTI or new-RNTI
* 0 IDENTIFIER_DCI_FORMATS:
* 1 CARRIER_IND:
* 7 BANDWIDTH_PART_IND:
* 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
* 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 5.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
* 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
* 14 PRB_BUNDLING_SIZE_IND:
* 15 RATE_MATCHING_IND:
* 16 ZP_CSI_RS_TRIGGER:
* 18 TB1_MCS:
* 19 TB1_NDI:
* 20 TB1_RV:
* 21 TB2_MCS:
* 22 TB2_NDI:
* 23 TB2_RV:
* 27 HARQ_PROCESS_NUMBER:
* 28 DAI_: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
* 33 TPC_PUCCH:
* 34 PUCCH_RESOURCE_IND:
* 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
* 38 ANTENNA_PORTS:
* 39 TCI:
* 40 SRS_REQUEST:
* 43 CBGTI:
* 44 CBGFI:
* 47 DMRS_SEQ_INI:
*
* We have not implemented the following formats:
*
* Format 2_0
* Used for notifying the slot format
*
* Format 2_1
* Used for notifying the PRB(s) and OFDM symbol(s) where UE may assume no transmission is intended for the UE
*
* Format 2_2
* This format supports power control commands for semi-persistent scheduling.
* As we can already support power control commands dynamically with formats 0_0/0_1 (TPC PUSCH) and 1_0/1_1 (TPC PUCCH)
* This format will be implemented in the future FIXME!!!
*
* Format 2_3
* This format is used for power control of uplink sounding reference signals for devices which have not coupled SRS power control to the PUSCH power control
* either because independent control is desirable or because the device is configured without PUCCH and PUSCH
* This format will be implemented in the future FIXME!!!
*
*/
uint8_t dci_fields_sizes_format[NBR_NR_DCI_FIELDS] = {0};
for (int m=0; m<NBR_NR_DCI_FIELDS; m++) dci_fields_sizes_format[m]=dci_fields_sizes[m][dci_format];
// uint64_t pdu_bitmap = 0xFFFFFFFFFFFFFFFF;
// uint128_t pdu_bitmap = 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
//#define DCI_MAX_SIZE 128
// pdu_bitmap = (pdu_bitmap << (DCI_MAX_SIZE - dci_length)) >> (DCI_MAX_SIZE - dci_length); // this variable will help to remove the bits of other fields when left-switching
uint8_t dci_field=0;
// uint8_t sizes_count=0;
// uint8_t left_shift=0;
LOG_DCI_D("Entering function nr_extract_dci_info() with dci_pdu=%lx %lx dci_length=%d\n",
dci_pdu[0],dci_pdu[1], dci_length);
LOG_DCI_D("for format %d, dci_fields_sizes {",dci_format);
#ifdef NR_PDCCH_DCI_TOOLS_DEBUG
for (int i=0; i<NBR_NR_DCI_FIELDS; i++) printf("%d ",dci_fields_sizes[i][dci_format]);
printf("}\n");
#endif
// uint8_t prev_ndi = pdlsch0_harq->DCINdi;
/*
* Some dci fields need to be interpreted before the others.
*/
if (dci_fields_sizes[HARQ_PROCESS_NUMBER][dci_format] != 0) { // E.g: 27 HARQ_PROCESS_NUMBER (27 is the position in dci_fields_sizes array for field HARQ_PROCESS_NUMBER)
//for (int i=0; i<=HARQ_PROCESS_NUMBER; i++) left_shift = left_shift + dci_fields_sizes[i][dci_format];
nr_pdci_info_extracted->harq_process_number = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,HARQ_PROCESS_NUMBER);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[HARQ_PROCESS_NUMBER][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[HARQ_PROCESS_NUMBER][dci_format]));
//left_shift = 0;
LOG_DCI_D("nr_pdci_info_extracted->harq_process_number=%x\n",nr_pdci_info_extracted->harq_process_number);
}
/*
if ((dci_format == format1_0) || (dci_format == format1_1)) {
if (rnti==crc_scrambled_values[_SI_RNTI_]) {
ue->dlsch_SI[eNB_id]->active = 1;
} else if (rnti==crc_scrambled_values[_P_RNTI_]) {
ue->dlsch_p[eNB_id]->active = 1;
} else if (rnti==crc_scrambled_values[_RA_RNTI_]) {
ue->dlsch_ra[eNB_id]->active = 1;
} else {
pdlsch0->active = 1;
}
pdlsch0->rnti = rnti;
pdlsch0_harq->codeword = 0;
pdlsch0_harq->Nl = 1;
// pdlsch0_harq->mimo_mode = frame_parms->mode1_flag == 1 ?SISO : ALAMOUTI;
pdlsch0_harq->dl_power_off = 1; //no power offset
if ((rnti==crc_scrambled_values[_SI_RNTI_]) || (rnti==crc_scrambled_values[_P_RNTI_]) || (rnti==crc_scrambled_values[_RA_RNTI_])) {
pdlsch0_harq->round = 0;
pdlsch0_harq->status = ACTIVE;
} else {
}
}
*/
for (dci_field=0; dci_field<NBR_NR_DCI_FIELDS; dci_field++) {
//left_shift = left_shift + dci_fields_sizes[dci_field][dci_format];
if (dci_fields_sizes[dci_field][dci_format] != 0) {
//sizes_count = dci_fields_sizes[dci_field][dci_format];
LOG_DCI_D("dci_fields_sizes[%d][%d] = %d\n",dci_field,dci_format,dci_fields_sizes[dci_field][dci_format]);
switch (dci_field) {
case IDENTIFIER_DCI_FORMATS: // 0 IDENTIFIER_DCI_FORMATS: (field defined for format0_0,format0_1,format1_0,format1_1,format2_0,format2_1,format2_2,format2_3)
// if format 0_0: The value of this bit field is always set to 0, indicating an UL DCI format (TS38.212 Section 7.3.1.1.1)
// if format 1_0: The value of this bit field is always set to 1, indicating a DL DCI format (TS38.212 Section 7.3.1.2.1)
nr_pdci_info_extracted->identifier_dci_formats = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->identifier_dci_formats=%x\n",nr_pdci_info_extracted->identifier_dci_formats);
break;
case CARRIER_IND: // 1 CARRIER_IND: (field defined for -,format0_1,-,format1_1,-,-,-,-)
// 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213]
nr_pdci_info_extracted->carrier_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->carrier_ind=%x\n",nr_pdci_info_extracted->carrier_ind);
break;
case SUL_IND_0_1: // 2 SUL_IND_0_1: (field defined for -,format0_1,-,-,-,-,-,-)
nr_pdci_info_extracted->sul_ind_0_1 = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->sul_ind_0_1=%x\n",nr_pdci_info_extracted->sul_ind_0_1);
break;
case SLOT_FORMAT_IND: // 3 SLOT_FORMAT_IND: (field defined for -,-,-,-,format2_0,-,-,-)
// size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213]
nr_pdci_info_extracted->slot_format_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->slot_format_ind=%x\n",nr_pdci_info_extracted->slot_format_ind);
break;
case PRE_EMPTION_IND: // 4 PRE_EMPTION_IND: (field defined for -,-,-,-,-,format2_1,-,-)
// size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits
nr_pdci_info_extracted->pre_emption_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->pre_emption_ind=%x\n",nr_pdci_info_extracted->pre_emption_ind);
break;
case BLOCK_NUMBER: // 5 BLOCK_NUMBER: (field defined for -,-,-,-,-,-,-,format2_3)
// starting position of a block is determined by the parameter startingBitOfFormat2_3
nr_pdci_info_extracted->block_number = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->block_number=%x\n",nr_pdci_info_extracted->block_number);
break;
case CLOSE_LOOP_IND: // 6 CLOSE_LOOP_IND: (field defined for -,-,-,-,-,-,format2_2,-)
// The parameter xxx provided by higher layers determines the index to the TPC command number for an UL of a cell. Each TPC command number is 2 bits
nr_pdci_info_extracted->close_loop_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->close_loop_ind=%x\n",nr_pdci_info_extracted->close_loop_ind);
break;
case BANDWIDTH_PART_IND: // 7 BANDWIDTH_PART_IND: (field defined for -,format0_1,-,format1_1,-,-,-,-)
nr_pdci_info_extracted->bandwidth_part_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->bandwidth_part_ind=%x\n",nr_pdci_info_extracted->bandwidth_part_ind);
break;
case SHORT_MESSAGE_IND: // 8 SHORT_MESSAGE_IND: (field defined for -,-,format1_0,format1_1,-,-,-,-)
nr_pdci_info_extracted->short_message_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->short_message_ind=%x\n",nr_pdci_info_extracted->short_message_ind);
break;
case SHORT_MESSAGES: // 9 SHORT_MESSAGES: (field defined for -,-,format1_0,format1_1,-,-,-,-)
nr_pdci_info_extracted->short_messages = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->short_messages=%x\n",nr_pdci_info_extracted->short_messages);
break;
case FREQ_DOM_RESOURCE_ASSIGNMENT_UL: // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: (field defined for format0_0,format0_1,-,-,-,-,-,-)
// PUSCH hopping with resource allocation type 1 not considered
// According to 38.214 V15.1.0 Section 6.1.2.2 Two uplink resource allocation schemes, type 0 and type 1, are supported.
// The UE shall assume that when the scheduling PDCCH is received with DCI format 0_0, then uplink resource allocation type 1 is used.
nr_pdci_info_extracted->freq_dom_resource_assignment_UL = (uint16_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
/*if (dci_format == format0_1){ // uplink resource allocation type 0 or 1 can be used
}
if (dci_format == format0_0){ // only uplink resource allocation type 1
// At the moment we are supporting only format 1_0 (and not format 1_1), so we only support resource allocation type 1 (and not type 0).
// For resource allocation type 1, the resource allocation field consists of a resource indication value (RIV):
// RIV = n_RB_ULBWP * (l_RB - 1) + start_RB if (l_RB - 1) <= floor (n_RB_ULBWP/2)
// RIV = n_RB_ULBWP * (n_RB_ULBWP - l_RB + 1) + (n_RB_ULBWP - 1 - start_RB) if (l_RB - 1) > floor (n_RB_ULBWP/2)
// the following two expressions apply only if (l_RB - 1) <= floor (n_RB_ULBWP/2)
l_RB = floor(nr_pdci_info_extracted->freq_dom_resource_assignment_DL/n_RB_ULBWP) + 1;
start_RB = nr_pdci_info_extracted->freq_dom_resource_assignment_DL%n_RB_ULBWP;
// if (l_RB - 1) > floor (n_RB_ULBWP/2) we need to recalculate them using the following lines
tmp_RIV = n_RB_ULBWP * (l_RB - 1) + start_RB;
if (tmp_RIV != nr_pdci_info_extracted->freq_dom_resource_assignment_DL) { // then (l_RB - 1) > floor (n_RB_ULBWP/2) and we need to recalculate l_RB and start_RB
l_RB = n_RB_ULBWP - l_RB + 2;
start_RB = n_RB_ULBWP - start_RB - 1;
}
ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->first_rb = start_RB;
ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->nb_rb = l_RB;
}*/
LOG_DCI_D("nr_pdci_info_extracted->freq_dom_resource_assignment_UL=%x\n",nr_pdci_info_extracted->freq_dom_resource_assignment_UL);
//LOG_DCI_D("l_RB=%d, start_RB=%d, n_RB_DLBWP=%d\n",l_RB,start_RB,n_RB_ULBWP);
break;
case FREQ_DOM_RESOURCE_ASSIGNMENT_DL: // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL: (field defined for -,-,format1_0,format1_1,-,-,-,-)
// According to 38.214 V15.1.0 Section 5.1.2.2 Two downlink resource allocation schemes, type 0 and type 1, are supported.
// The UE shall assume that when the scheduling grant is received with DCI format 1_0, then downlink resource allocation type 1 is used.
nr_pdci_info_extracted->freq_dom_resource_assignment_DL = (uint16_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
/*if (dci_format == format1_1){ // uplink resource allocation type 0 or 1 can be used
}
if (dci_format == format1_0){ // only uplink resource allocation type 1
// At the moment we are supporting only format 0_0 (and not format 0_1), so we only support resource allocation type 1 (and not type 0).
// For resource allocation type 1, the resource allocation field consists of a resource indication value (RIV):
// RIV = n_RB_DLBWP * (l_RB - 1) + start_RB if (l_RB - 1) <= floor (n_RB_DLBWP/2)
// RIV = n_RB_DLBWP * (n_RB_DLBWP - l_RB + 1) + (n_RB_DLBWP - 1 - start_RB) if (l_RB - 1) > floor (n_RB_DLBWP/2)
// the following two expressions apply only if (l_RB - 1) <= floor (n_RB_DLBWP/2)
l_RB = floor(nr_pdci_info_extracted->freq_dom_resource_assignment_DL/n_RB_DLBWP) + 1;
start_RB = nr_pdci_info_extracted->freq_dom_resource_assignment_DL%n_RB_DLBWP;
// if (l_RB - 1) > floor (n_RB_DLBWP/2) we need to recalculate them using the following lines
tmp_RIV = n_RB_DLBWP * (l_RB - 1) + start_RB;
if (tmp_RIV != nr_pdci_info_extracted->freq_dom_resource_assignment_DL) { // then (l_RB - 1) > floor (n_RB_DLBWP/2) and we need to recalculate l_RB and start_RB
l_RB = n_RB_DLBWP - l_RB + 2;
start_RB = n_RB_DLBWP - start_RB - 1;
}
pdlsch0_harq->nb_rb = l_RB;
pdlsch0->current_harq_pid = nr_pdci_info_extracted->harq_process_number;
pdlsch0->active = 1;
pdlsch0->rnti = rnti;
}*/
LOG_DCI_D("nr_pdci_info_extracted->freq_dom_resource_assignment_DL=%x, RIV = %d\n",nr_pdci_info_extracted->freq_dom_resource_assignment_DL,nr_pdci_info_extracted->freq_dom_resource_assignment_DL);
//LOG_DCI_D("l_RB=%d, start_RB=%d, n_RB_DLBWP=%d\n",l_RB,start_RB,n_RB_DLBWP);
/*
* According to TC 38.212 Subclause 7.3.1.2.1 (V15.2.0) (not implemented FIXME!!!)
* If the CRC of the DCI format 1_0 is scrambled by C-RNTI
* and the "Frequency domain resource assignment" field are of all ones,
* the DCI format 1_0 is for random access procedure initiated by a PDCCH order,
* with all remaining fields set as follows:
* - Random Access Preamble index (6 bits)
* - UL/SUL indicator (1 bit)
* - SS/PBCH index (6 bits)
* - PRACH Mask index (4 bits)
* - Reserved bits (10 bits)
*
*/
/*
* The following commented code is used to verify that l_RB and start_RB are correctly calculated
*
*
printf("\ns_RB\t");
n_RB_DLBWP = 20;
for (int k = 0 ; k < n_RB_DLBWP; k++) printf("%d\t",k);
printf("\nl_RB");
for (int j = 1 ; j <= n_RB_DLBWP; j++){ // l_RB
printf("\n%d\t",j);
for (int i = 0 ; i < n_RB_DLBWP; i++) { // start_RB
if ((j-1) <= (floor(n_RB_DLBWP/2)) && ((j+i) <= n_RB_DLBWP)) {
tmp_RIV = n_RB_DLBWP * (j - 1) + i;
l_RB = floor(tmp_RIV/n_RB_DLBWP) + 1;
start_RB = tmp_RIV%n_RB_DLBWP;
printf("%d(%d,%d) ",tmp_RIV,l_RB,start_RB);
}
if ((j-1) > (floor(n_RB_DLBWP/2)) && ((j+i) <= n_RB_DLBWP)) {
tmp_RIV = n_RB_DLBWP * (n_RB_DLBWP - j + 1) + (n_RB_DLBWP - 1 - i);
//l_RB = floor(tmp_RIV/n_RB_DLBWP) + 1;
//start_RB = tmp_RIV%n_RB_DLBWP;
l_RB = n_RB_DLBWP - (floor(tmp_RIV/n_RB_DLBWP) + 1) + 2;
start_RB = n_RB_DLBWP - (tmp_RIV%n_RB_DLBWP) - 1;
printf("%d*(%d,%d) ",tmp_RIV,l_RB,start_RB);
}
}
}*/
break;
case TIME_DOM_RESOURCE_ASSIGNMENT: // 12 TIME_DOM_RESOURCE_ASSIGNMENT: (field defined for format0_0,format0_1,format1_0,format1_1,-,-,-,-)
// 0, 1, 2, 3, or 4 bits as defined in:
// Subclause 6.1.2.1 of [6, TS 38.214] for formats format0_0,format0_1
// Subclause 5.1.2.1 of [6, TS 38.214] for formats format1_0,format1_1
// The bitwidth for this field is determined as log2(I) bits,
// where I the number of entries in the higher layer parameter pusch-AllocationList
nr_pdci_info_extracted->time_dom_resource_assignment = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
/*if (dci_format == format0_0 || dci_format == format0_1){ // Subclause 6.1.2.1 of [6, TS 38.214]
k_offset = table_6_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][0];
sliv_S = table_6_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][1];
sliv_L = table_6_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][2];
// k_offset = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][0];
// sliv_S = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][1];
// sliv_L = table_6_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][2];
}
if (dci_format == format1_0 || dci_format == format1_1){ // Subclause 5.1.2.1 of [6, TS 38.214]
// the Time domain resource assignment field of the DCI provides a row index of a higher layer configured table pdsch-symbolAllocation
// FIXME! To clarify which parameters to update after reception of row index
k_offset = table_5_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][0];
sliv_S = table_5_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][1];
sliv_L = table_5_1_2_1_1_2_time_dom_res_alloc_A[nr_pdci_info_extracted->time_dom_resource_assignment][2];
// k_offset = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][0];
// sliv_S = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][1];
// sliv_L = table_5_1_2_1_1_3_time_dom_res_alloc_A_extCP[nr_pdci_info_extracted->time_dom_resource_assignment][2];
// k_offset = table_5_1_2_1_1_4_time_dom_res_alloc_B[nr_pdci_info_extracted->time_dom_resource_assignment][0];
// sliv_S = table_5_1_2_1_1_4_time_dom_res_alloc_B[nr_pdci_info_extracted->time_dom_resource_assignment][1];
// sliv_L = table_5_1_2_1_1_4_time_dom_res_alloc_B[nr_pdci_info_extracted->time_dom_resource_assignment][2];
// k_offset = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][0];
// sliv_S = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][1];
// sliv_L = table_5_1_2_1_1_5_time_dom_res_alloc_C[nr_pdci_info_extracted->time_dom_resource_assignment][2];
}*/
LOG_DCI_D("nr_pdci_info_extracted->time_dom_resource_assignment=%x\n",nr_pdci_info_extracted->time_dom_resource_assignment);
break;
case VRB_TO_PRB_MAPPING: // 13 VRB_TO_PRB_MAPPING: (field defined for -,format0_1,format1_0,format1_1,-,-,-,-)
//0 bit if resource allocation type 0
//1 bit if resource allocation type 1
//Table 7.3.1.1.2-33: VRB-to-PRB mapping
// 0 Non-interleaved
// 1 Interleaved
nr_pdci_info_extracted->vrb_to_prb_mapping = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
//if (nr_pdci_info_extracted->vrb_to_prb_mapping == 0) { // Non-interleaved
//} else { // Interleaved
// format 0_1 defined in TS 38.211 Section 6.3.1.7
// formats 1_0 and 1_1 not defined yet
//}
LOG_DCI_D("nr_pdci_info_extracted->vrb_to_prb_mapping=%x\n",nr_pdci_info_extracted->vrb_to_prb_mapping);
break;
case PRB_BUNDLING_SIZE_IND: // 14 PRB_BUNDLING_SIZE_IND: (field defined for -,-,-,format1_1,-,-,-,-)
// 0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214]
nr_pdci_info_extracted->prb_bundling_size_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->prb_bundling_size_ind=%x\n",nr_pdci_info_extracted->prb_bundling_size_ind);
break;
case RATE_MATCHING_IND: // 15 RATE_MATCHING_IND: (field defined for -,-,-,format1_1,-,-,-,-)
// 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set
nr_pdci_info_extracted->rate_matching_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->rate_matching_ind=%x\n",nr_pdci_info_extracted->rate_matching_ind);
break;
case ZP_CSI_RS_TRIGGER: // 16 ZP_CSI_RS_TRIGGER: (field defined for -,-,-,format1_1,-,-,-,-)
nr_pdci_info_extracted->zp_csi_rs_trigger = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->zp_csi_rs_trigger=%x\n",nr_pdci_info_extracted->zp_csi_rs_trigger);
break;
case FREQ_HOPPING_FLAG: // 17 FREQ_HOPPING_FLAG: (field defined for format0_0,format0_1,-,-,-,-,-,-)
// 0 bit if only resource allocation type 0
// 1 bit otherwise, only applicable to resource allocation type 1, as defined in Subclause 6.3 of [6, TS 38.214]
nr_pdci_info_extracted->freq_hopping_flag = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
//if (nr_pdci_info_extracted->freq_hopping_flag != 0) { // PUSCH frequency hopping is performed (only resource allocation type 1)
//} else { // PUSCH frequency hopping is not performed (only resource allocation type 1)
// At the moment PUSCH hopping is not implemented. We are considering that the bit is present and the value is '0'
//}
LOG_DCI_D("nr_pdci_info_extracted->freq_hopping_flag=%x\n",nr_pdci_info_extracted->freq_hopping_flag);
break;
case TB1_MCS: // 18 TB1_MCS: (field defined for -,-,-,format1_1,-,-,-,-)
nr_pdci_info_extracted->tb1_mcs = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
//if (nr_pdci_info_extracted->mcs < 29) pdlsch0_harq->mcs = nr_pdci_info_extracted->tb1_mcs;
LOG_DCI_D("nr_pdci_info_extracted->tb1_mcs=%x\n",nr_pdci_info_extracted->tb1_mcs);
break;
case TB1_NDI: // 19 TB1_NDI: (field defined for -,-,-,format1_1,-,-,-,-)
nr_pdci_info_extracted->tb1_ndi = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
//pdlsch0_harq->DCINdi = nr_pdci_info_extracted->tb1_ndi;
LOG_DCI_D("nr_pdci_info_extracted->tb1_ndi=%x\n",nr_pdci_info_extracted->tb1_ndi);
break;
case TB1_RV: // 20 TB1_RV: (field defined for -,-,-,format1_1,-,-,-,-)
nr_pdci_info_extracted->tb1_rv = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
//pdlsch0_harq->rvidx = nr_pdci_info_extracted->tb1_rv;
LOG_DCI_D("nr_pdci_info_extracted->tb1_rv=%x\n",nr_pdci_info_extracted->tb1_rv);
break;
case TB2_MCS: // 21 TB2_MCS: (field defined for -,-,-,format1_1,-,-,-,-)
nr_pdci_info_extracted->tb2_mcs = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
//if (nr_pdci_info_extracted->mcs < 29) pdlsch0_harq->mcs = nr_pdci_info_extracted->tb2_mcs;
LOG_DCI_D("nr_pdci_info_extracted->tb2_mcs=%x\n",nr_pdci_info_extracted->tb2_mcs);
break;
case TB2_NDI: // 22 TB2_NDI: (field defined for -,-,-,format1_1,-,-,-,-)
nr_pdci_info_extracted->tb2_ndi = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
//pdlsch0_harq->DCINdi = nr_pdci_info_extracted->tb2_ndi;
LOG_DCI_D("nr_pdci_info_extracted->tb2_ndi=%x\n",nr_pdci_info_extracted->tb2_ndi);
break;
case TB2_RV: // 23 TB2_RV: (field defined for -,-,-,format1_1,-,-,-,-)
nr_pdci_info_extracted->tb2_rv = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
//pdlsch0_harq->rvidx = nr_pdci_info_extracted->tb2_rv;
LOG_DCI_D("nr_pdci_info_extracted->tb2_rv=%x\n",nr_pdci_info_extracted->tb2_rv);
break;
case MCS: // 24 MCS: (field defined for format0_0,format0_1,format1_0,-,-,-,-,-)
nr_pdci_info_extracted->mcs = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
//if (nr_pdci_info_extracted->mcs < 29) {
// if (dci_format == format0_0 || dci_format == format0_1)
// ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->mcs = nr_pdci_info_extracted->mcs;
// else
// pdlsch0_harq->mcs = nr_pdci_info_extracted->mcs;
//} else {
// return(0);
//}
LOG_DCI_D("nr_pdci_info_extracted->mcs=%x\n",nr_pdci_info_extracted->mcs);
break;
case NDI: // 25 NDI: (field defined for format0_0,format0_1,format1_0,-,-,-,-,-)
nr_pdci_info_extracted->ndi = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
//if (dci_format == format0_0 || dci_format == format0_1) {
// ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->DCINdi = nr_pdci_info_extracted->ndi;
// if (ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->first_tx==1) {
// ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->first_tx=0;
// ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->DCINdi= nr_pdci_info_extracted->ndi;
// ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->round = 0;
// } else {
// if (ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->DCINdi != nr_pdci_info_extracted->ndi) { // new SDU opportunity
// ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->DCINdi= nr_pdci_info_extracted->ndi;
// ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->round = 0;
// }
// }
//} else {
// if (rnti == crc_scrambled_values[_TC_RNTI_]) { //fix for standalone Contention Resolution Id
// pdlsch0_harq->DCINdi = (uint8_t)-1;
// } else {
// if ((prev_ndi != nr_pdci_info_extracted->ndi) || (pdlsch0_harq->first_tx==1)) {
// pdlsch0_harq->round = 0;
// pdlsch0_harq->first_tx = 0;
// pdlsch0_harq->status = ACTIVE;
// }
// pdlsch0_harq->DCINdi = nr_pdci_info_extracted->ndi;
// }
//}
LOG_DCI_D("nr_pdci_info_extracted->ndi=%x\n",nr_pdci_info_extracted->ndi);
break;
case RV: // 26 RV: (field defined for format0_0,format0_1,format1_0,-,-,-,-,-)
nr_pdci_info_extracted->rv = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
//if (dci_format == format0_0 || dci_format == format0_1)
// ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->rvidx = nr_pdci_info_extracted->rv;
//else
// pdlsch0_harq->rvidx = nr_pdci_info_extracted->rv;
//if ((prev_ndi == nr_pdci_info_extracted->ndi) && (pdlsch0_harq->rvidx != 0)) { // NDI has not been toggled but rv was increased by eNB: retransmission
// if (pdlsch0_harq->status == SCH_IDLE) {
// packet was actually decoded in previous transmission (ACK was missed by eNB)
// however, the round is not a good check as it might have been decoded in a retransmission prior to this one.
// skip pdsch decoding and report ack
// pdlsch0->harq_processes[pdlsch0->current_harq_pid]->harq_ack.ack = 1;
// pdlsch0->harq_processes[pdlsch0->current_harq_pid]->harq_ack.send_harq_status;
#if 0
// pdlsch0->active = 0;
// pdlsch0->harq_ack[nr_tti_rx].ack = 1;
// pdlsch0->harq_ack[nr_tti_rx].harq_id = nr_pdci_info_extracted->harq_process_number;
// pdlsch0->harq_ack[nr_tti_rx].send_harq_status = 1;
#endif
// } else { // normal retransmission, nothing special to do
// }
//} else {
// pdlsch0_harq->status = ACTIVE;
//}
LOG_DCI_D("nr_pdci_info_extracted->rv=%x\n",nr_pdci_info_extracted->rv);
break;
case HARQ_PROCESS_NUMBER: // 27 HARQ_PROCESS_NUMBER: (field defined for format0_0,format0_1,format1_0,format1_1,-,-,-,-)
nr_pdci_info_extracted->harq_process_number = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
//pdlsch0->current_harq_pid = nr_pdci_info_extracted->harq_process_number;
LOG_DCI_D("nr_pdci_info_extracted->harq_process_number=%x\n",nr_pdci_info_extracted->harq_process_number);
break;
case DAI_: // 28 DAI_: (field defined for -,-,format1_0,format1_1,-,-,-,-)
// For format1_0: 2 bits as defined in Subclause 9.1.3 at TS 38.213
// For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
// 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI
// 0 otherwise
nr_pdci_info_extracted->dai = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
//pdlsch0->harq_processes[pdlsch0->current_harq_pid]->harq_ack.vDAI_DL = nr_pdci_info_extracted->dai+1;
//pdlsch0->harq_ack[nr_tti_rx].vDAI_DL = nr_pdci_info_extracted->dai+1;
LOG_DCI_D("nr_pdci_info_extracted->dai=%x\n",nr_pdci_info_extracted->dai);
break;
case FIRST_DAI: // 29 FIRST_DAI: (field defined for -,format0_1,-,-,-,-,-,-)
// (1 or 2 bits) 1 bit for semi-static HARQ-ACK
nr_pdci_info_extracted->first_dai = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->first_dai=%x\n",nr_pdci_info_extracted->first_dai);
break;
case SECOND_DAI: // 30 SECOND_DAI: (field defined for -,format0_1,-,-,-,-,-,-)
// (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks
nr_pdci_info_extracted->second_dai = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->second_dai=%x\n",nr_pdci_info_extracted->second_dai);
break;
case TB_SCALING: // 31 TB_SCALING: (field defined for -,format0_1,-,-,-,-,-,-)
// (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks
nr_pdci_info_extracted->tb_scaling = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->tb_scaling=%x\n",nr_pdci_info_extracted->tb_scaling);
break;
case TPC_PUSCH: // 32 TPC_PUSCH: (field defined for format0_0,format0_1,-,-,-,-,-,-)
// defined in Subclause 7.1.1 TS 38.213
nr_pdci_info_extracted->tpc_pusch = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
//ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->TPC = nr_pdci_info_extracted->tpc_pusch;
//if (ue->ul_power_control_dedicated[eNB_id].accumulationEnabled == 1) {
// ulsch0->f_pusch += nr_delta_PUSCH_acc[ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->TPC];
//} else {
// ulsch0->f_pusch = nr_delta_PUSCH_abs[ulsch0->harq_processes[nr_pdci_info_extracted->harq_process_number]->TPC];
//}
LOG_DCI_D("nr_pdci_info_extracted->tpc_pusch=%x\n",nr_pdci_info_extracted->tpc_pusch);
break;
case TPC_PUCCH: // 33 TPC_PUCCH: (field defined for -,-,format1_0,format1_1,-,-,-,-)
// defined in Subclause 7.2.1 TS 38.213
nr_pdci_info_extracted->tpc_pucch = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
//pdlsch0_harq->delta_PUCCH = nr_delta_PUCCH_lut[nr_pdci_info_extracted->tpc_pucch &3];
LOG_DCI_D("nr_pdci_info_extracted->tpc_pucch=%x\n",nr_pdci_info_extracted->tpc_pucch);
break;
case PUCCH_RESOURCE_IND: // 34 PUCCH_RESOURCE_IND: (field defined for -,-,format1_0,format1_1,-,-,-,-)
// defined in Subclause 9.2.3 TS 38.213
// PUCCH_RESOURCE_IND points to PUCCH-ResourceId, but PUCCH-ResourceId is not defined yet
nr_pdci_info_extracted->pucch_resource_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->pucch_resource_ind=%x\n",nr_pdci_info_extracted->pucch_resource_ind);
break;
case PDSCH_TO_HARQ_FEEDBACK_TIME_IND: // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND: (field defined for -,-,format1_0,format1_1,-,-,-,-)
// defined in Subclause 9.2.3 TS 38.213
// PDSCH_TO_HARQ_FEEDBACK_TIME_IND points to DL-data-DL-acknowledgement, but DL-data-DL-acknowledgement is not defined yet
nr_pdci_info_extracted->pdsch_to_harq_feedback_time_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->pdsch_to_harq_feedback_time_ind=%x\n",nr_pdci_info_extracted->pdsch_to_harq_feedback_time_ind);
break;
case SRS_RESOURCE_IND: // 36 SRS_RESOURCE_IND: (field defined for -,format0_1,-,-,-,-,-,-)
nr_pdci_info_extracted->srs_resource_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->srs_resource_ind=%x\n",nr_pdci_info_extracted->srs_resource_ind);
break;
case PRECOD_NBR_LAYERS: // 37 PRECOD_NBR_LAYERS: (field defined for -,format0_1,-,-,-,-,-,-)
nr_pdci_info_extracted->precod_nbr_layers = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->precod_nbr_layers=%x\n",nr_pdci_info_extracted->precod_nbr_layers);
break;
case ANTENNA_PORTS: // 38 ANTENNA_PORTS: (field defined for -,format0_1,-,format1_1,-,-,-,-)
nr_pdci_info_extracted->antenna_ports = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->antenna_ports=%x\n",nr_pdci_info_extracted->antenna_ports);
break;
case TCI: // 39 TCI: (field defined for -,-,-,format1_1,-,-,-,-)
// 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits
nr_pdci_info_extracted->tci = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->tci=%x\n",nr_pdci_info_extracted->tci);
break;
case SRS_REQUEST: // 40 SRS_REQUEST: (field defined for -,format0_1,-,format1_1,-,-,-,format2_3)
nr_pdci_info_extracted->srs_request = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->srs_request=%x\n",nr_pdci_info_extracted->srs_request);
break;
case TPC_CMD: // 41 TPC_CMD: (field defined for -,-,-,-,-,-,-,format2_3)
nr_pdci_info_extracted->tpc_cmd = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->tpc_cmd=%x\n",nr_pdci_info_extracted->tpc_cmd);
break;
case CSI_REQUEST: // 42 CSI_REQUEST: (field defined for -,format0_1,-,-,-,-,-,-)
nr_pdci_info_extracted->csi_request = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->csi_request=%x\n",nr_pdci_info_extracted->csi_request);
break;
case CBGTI: // 43 CBGTI: (field defined for -,format0_1,-,format1_1,-,-,-,-)
// 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH
nr_pdci_info_extracted->cbgti = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->cbgti=%x\n",nr_pdci_info_extracted->cbgti);
break;
case CBGFI: // 44 CBGFI: (field defined for -,-,-,format1_1,-,-,-,-)
// 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator
nr_pdci_info_extracted->cbgfi = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->cbgfi=%x\n",nr_pdci_info_extracted->cbgfi);
break;
case PTRS_DMRS: // 45 PTRS_DMRS: (field defined for -,format0_1,-,-,-,-,-,-)
nr_pdci_info_extracted->ptrs_dmrs = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->ptrs_dmrs=%x\n",nr_pdci_info_extracted->ptrs_dmrs);
break;
case BETA_OFFSET_IND: // 46 BETA_OFFSET_IND: (field defined for -,format0_1,-,-,-,-,-,-)
nr_pdci_info_extracted->beta_offset_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->beta_offset_ind=%x\n",nr_pdci_info_extracted->beta_offset_ind);
break;
case DMRS_SEQ_INI: // 47 DMRS_SEQ_INI: (field defined for -,format0_1,-,format1_1,-,-,-,-)
// 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise
nr_pdci_info_extracted->dmrs_seq_ini = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->dmrs_seq_ini=%x\n",nr_pdci_info_extracted->dmrs_seq_ini);
break;
case UL_SCH_IND: // 48 UL_SCH_IND: (field defined for -,format0_1,-,-,-,-,-,-)
// value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH
nr_pdci_info_extracted->ul_sch_ind = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->dmrs_seq_ini=%x\n",nr_pdci_info_extracted->ul_sch_ind);
break;
case PADDING_NR_DCI: // 49 PADDING_NR_DCI: (field defined for format0_0,-,format1_0,-,-,-,-,-)
// (Note 2) If DCI format 0_0 is monitored in common search space
nr_pdci_info_extracted->padding_nr_dci = (uint16_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->padding=%x\n",nr_pdci_info_extracted->padding_nr_dci);
break;
case SUL_IND_0_0: // 50 SUL_IND_0_0: (field defined for format0_0,-,-,-,-,-,-,-)
nr_pdci_info_extracted->sul_ind_0_0 = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->sul_ind_0_0=%x\n",nr_pdci_info_extracted->sul_ind_0_0);
break;
case RA_PREAMBLE_INDEX: // 51 RA_PREAMBLE_INDEX: (field defined for format0_0,-,-,-,-,-,-,-)
nr_pdci_info_extracted->ra_preamble_index = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->ra_preamble_index=%x\n",nr_pdci_info_extracted->ra_preamble_index);
break;
case SUL_IND_1_0: // 52 SUL_IND_1_0: (field defined for -,-,format1_0,-,-,-,-,-)
nr_pdci_info_extracted->sul_ind_1_0 = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->sul_ind_1_0=%x\n",nr_pdci_info_extracted->sul_ind_1_0);
break;
case SS_PBCH_INDEX: // 53 SS_PBCH_INDEX: (field defined for -,-,format1_0,-,-,-,-,-)
nr_pdci_info_extracted->ss_pbch_index = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->ss_pbch_index=%x\n",nr_pdci_info_extracted->ss_pbch_index);
break;
case PRACH_MASK_INDEX: // 54 PRACH_MASK_INDEX: (field defined for -,-,-,format1_0,-,-,-,-)
nr_pdci_info_extracted->prach_mask_index = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->prach_mask_index=%x\n",nr_pdci_info_extracted->prach_mask_index);
break;
case RESERVED_NR_DCI: // 55 RESERVED_NR_DCI: (field defined for -,-,-,format1_0,-,-,-,-)
nr_pdci_info_extracted->reserved_nr_dci = (uint8_t)nr_dci_field(dci_pdu,dci_fields_sizes_format,dci_field);
//(((((*(uint128_t *)dci_pdu) << (left_shift - dci_fields_sizes[dci_field][dci_format]))) & pdu_bitmap) >> (dci_length - dci_fields_sizes[dci_field][dci_format]));
LOG_DCI_D("nr_pdci_info_extracted->reserved_nr_dci=%x\n",nr_pdci_info_extracted->reserved_nr_dci);
break;
}
}
}
LOG_DCI_D("Ending function nr_extract_dci_info()\n");
return(1);
}
#endif
#ifdef NR_PDCCH_DCI_TOOLS
int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue,
uint8_t eNB_id,
int frame,
uint8_t nr_tti_rx,
uint64_t dci_pdu[2],
uint16_t rnti,
uint8_t dci_length,
NR_DCI_format_t dci_format,
NR_DL_FRAME_PARMS *frame_parms,
PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated,
uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
uint16_t n_RB_ULBWP,
uint16_t n_RB_DLBWP,
uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES],
fapi_nr_dci_pdu_rel15_t *nr_dci_info_extracted) {
/*
* Note only format0_0 and format1_0 are implemented
*/
uint8_t frame_type=frame_parms->frame_type;
uint8_t status=0;
LOG_DCI_PARM("dci_format=%d, rnti=%d, dci_length=%d, dci_pdu[0]=0x%lx, dci_pdu[1]=0x%lx\n",dci_format,rnti,dci_length,dci_pdu[0],
dci_pdu[1]);
memset(nr_dci_info_extracted,0,sizeof(*nr_dci_info_extracted));
LOG_DCI_PARM("Entering function nr_extract_dci_info(dci_format=%d) \n",dci_format);
status = nr_extract_dci_info(ue,
eNB_id,
frame_type,
dci_length,
rnti,
dci_pdu,
nr_dci_info_extracted,//&nr_dci_info_extracted,
dci_fields_sizes,
dci_format,
nr_tti_rx,
n_RB_ULBWP,
n_RB_DLBWP,
crc_scrambled_values);
if(status == 0) {
LOG_DCI_PARM("bad DCI %d !!! \n",dci_format);
return(-1);
}
LOG_DCI_PARM("Ending function nr_extract_dci_info()\n");
//fill
return(0);
}
#endif
uint8_t nr_subframe2harq_pid(NR_DL_FRAME_PARMS *frame_parms,uint32_t frame,uint8_t nr_tti_rx) {
/*
@@ -1000,7 +87,6 @@ uint8_t nr_subframe2harq_pid(NR_DL_FRAME_PARMS *frame_parms,uint32_t frame,uint8
return ret;
}
uint8_t nr_pdcch_alloc2ul_subframe(NR_DL_FRAME_PARMS *frame_parms,uint8_t n) {
uint8_t ul_subframe = 255;
openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c
+45 -29
View File
@@ -65,7 +65,7 @@ void free_nr_ue_dlsch(NR_UE_DLSCH_t **dlschptr)
for (i=0; i<dlsch->Mdlharq; i++) {
if (dlsch->harq_processes[i]) {
if (dlsch->harq_processes[i]->b) {
free16(dlsch->harq_processes[i]->b,MAX_DLSCH_PAYLOAD_BYTES);
free16(dlsch->harq_processes[i]->b,MAX_NR_DLSCH_PAYLOAD_BYTES);
dlsch->harq_processes[i]->b = NULL;
}
@@ -140,10 +140,10 @@ NR_UE_DLSCH_t *new_nr_ue_dlsch(uint8_t Kmimo,uint8_t Mdlharq,uint32_t Nsoft,uint
if (dlsch->harq_processes[i]) {
memset(dlsch->harq_processes[i],0,sizeof(NR_DL_UE_HARQ_t));
dlsch->harq_processes[i]->first_tx=1;
dlsch->harq_processes[i]->b = (uint8_t*)malloc16(MAX_DLSCH_PAYLOAD_BYTES/bw_scaling);
dlsch->harq_processes[i]->b = (uint8_t*)malloc16(MAX_NR_DLSCH_PAYLOAD_BYTES/bw_scaling);
if (dlsch->harq_processes[i]->b)
memset(dlsch->harq_processes[i]->b,0,MAX_DLSCH_PAYLOAD_BYTES/bw_scaling);
memset(dlsch->harq_processes[i]->b,0,MAX_NR_DLSCH_PAYLOAD_BYTES/bw_scaling);
else
exit_flag=3;
@@ -238,6 +238,8 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
return(dlsch->max_ldpc_iterations + 1);
}
t_nrLDPC_procBuf** p_nrLDPC_procBuf = harq_process->p_nrLDPC_procBuf;
AssertFatal(p_nrLDPC_procBuf[0]->llrProcBuf!=NULL,"Entry. llProcBuf is null!\n");
int16_t z [68*384];
int8_t l [68*384];
@@ -251,11 +253,10 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
double Coderate;// = 0.0;
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *dl_config_pdu = &harq_process->dl_config_pdu;
uint8_t dmrs_Type = dl_config_pdu->dmrsConfigType;
uint8_t dmrs_Type = harq_process->dmrsConfigType;
AssertFatal(dmrs_Type == 1 || dmrs_Type == 2,"Illegal dmrs_type %d\n",dmrs_Type);
uint8_t nb_re_dmrs = (dmrs_Type==1)?6:4;
uint16_t dmrs_length = get_num_dmrs(dl_config_pdu->dlDmrsSymbPos);
uint16_t dmrs_length = get_num_dmrs(harq_process->dlDmrsSymbPos);
AssertFatal(dmrs_length == 1 || dmrs_length == 2,"Illegal dmrs_length %d\n",dmrs_length);
uint32_t i,j;
@@ -315,7 +316,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
harq_process->G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, dmrs_length, harq_process->Qm,harq_process->Nl);
G = harq_process->G;
LOG_I(PHY,"DLSCH Decoding, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb);
LOG_D(PHY,"DLSCH Decoding, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb);
vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_SEGMENTATION, VCD_FUNCTION_IN);
@@ -431,11 +432,15 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_DEINTERLEAVING, VCD_FUNCTION_IN);
AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"10. llProcBuf is null!\n");
nr_deinterleaving_ldpc(E,
harq_process->Qm,
harq_process->w[r], // [hna] w is e
dlsch_llr+r_offset);
AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"11. llProcBuf is null!\n");
vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_DEINTERLEAVING, VCD_FUNCTION_OUT);
//for (int i =0; i<16; i++)
@@ -468,6 +473,8 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
else
Tbslbrm = nr_compute_tbslbrm(harq_process->mcs_table,nb_rb,4,harq_process->C);
AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"0. llProcBuf is null!\n");
if (nr_rate_matching_ldpc_rx(Ilbrm,
Tbslbrm,
p_decParams->BG,
@@ -492,6 +499,8 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
#endif
}
AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"1. llProcBuf is null!\n");
//for (int i =0; i<16; i++)
// printf("rx output ratematching d[%d]= %d r_offset %d\n", i,harq_process->d[r][i], r_offset);
@@ -558,27 +567,29 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
}
vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_LDPC, VCD_FUNCTION_IN);
AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"2. llProcBuf is null!\n");
no_iteration_ldpc = nrLDPC_decoder(p_decParams,
(int8_t*)&pl[0],
llrProcBuf,
p_nrLDPC_procBuf[r],
p_procTime);
AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"3. llProcBuf is null!\n");
vcd_signal_dumper_dump_function_by_name(VCD_SIGNAL_DUMPER_FUNCTIONS_DLSCH_LDPC, VCD_FUNCTION_OUT);
// Fixme: correct type is unsigned, but nrLDPC_decoder and all called behind use signed int
if (check_crc((uint8_t*)llrProcBuf,length_dec,harq_process->F,crc_type)) {
printf("\x1B[34m" "Segment %u CRC OK\n\033[0m",r);
LOG_D(PHY,"Segment %u CRC OK\n\033[0m",r);
//Temporary hack
no_iteration_ldpc = dlsch->max_ldpc_iterations;
ret = no_iteration_ldpc;
}
else {
printf("\x1B[33m" "CRC NOK\n\033[0m");
LOG_D(PHY,"CRC NOK\n\033[0m");
ret = 1 + dlsch->max_ldpc_iterations;
}
AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"4. llProcBuf is null!\n");
nb_total_decod++;
if (no_iteration_ldpc > dlsch->max_ldpc_iterations){
nb_error_decod++;
@@ -594,6 +605,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
{
harq_process->c[r][m]= (uint8_t) llrProcBuf[m];
}
AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"5. llProcBuf is null!\n");
#ifdef DEBUG_DLSCH_DECODING
//printf("output decoder %d %d %d %d %d \n", harq_process->c[r][0], harq_process->c[r][1], harq_process->c[r][2],harq_process->c[r][3], harq_process->c[r][4]);
@@ -620,7 +632,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
if ((err_flag == 0) && (ret>=(1+dlsch->max_ldpc_iterations))) {// a Code segment is in error so break;
LOG_I(PHY,"AbsSubframe %d.%d CRC failed, segment %d/%d \n",frame%1024,nr_tti_rx,r,harq_process->C-1);
LOG_D(PHY,"AbsSubframe %d.%d CRC failed, segment %d/%d \n",frame%1024,nr_tti_rx,r,harq_process->C-1);
err_flag = 1;
}
}
@@ -635,7 +647,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
if (err_flag == 1) {
//#if UE_DEBUG_TRACE
LOG_I(PHY,"[UE %d] DLSCH: Setting NAK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d) Kr %d r %d harq_process->round %d\n",
LOG_D(PHY,"[UE %d] DLSCH: Setting NAK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d) Kr %d r %d harq_process->round %d\n",
phy_vars_ue->Mod_id, frame, nr_tti_rx, harq_pid,harq_process->status, harq_process->round,harq_process->TBS,harq_process->mcs,Kr,r,harq_process->round);
//#endif
harq_process->harq_ack.ack = 0;
@@ -652,15 +664,16 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
if(is_crnti)
{
LOG_I(PHY,"[UE %d] DLSCH: Setting NACK for nr_tti_rx %d (pid %d, pid status %d, round %d/Max %d, TBS %d)\n",
LOG_D(PHY,"[UE %d] DLSCH: Setting NACK for nr_tti_rx %d (pid %d, pid status %d, round %d/Max %d, TBS %d)\n",
phy_vars_ue->Mod_id,nr_tti_rx,harq_pid,harq_process->status,harq_process->round,dlsch->Mdlharq,harq_process->TBS);
}
AssertFatal(p_nrLDPC_procBuf[r]->llrProcBuf!=NULL,"Exit 1. llProcBuf is null!\n");
return((1 + dlsch->max_ldpc_iterations));
} else {
//#if UE_DEBUG_TRACE
LOG_I(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d TBS %d mcs %d nb_rb %d harq_process->round %d\n",
phy_vars_ue->Mod_id,nr_tti_rx,harq_process->TBS,harq_process->mcs,harq_process->nb_rb, harq_process->round);
LOG_D(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d TBS %d mcs %d nb_rb %d harq_process->round %d\n",
phy_vars_ue->Mod_id,nr_tti_rx,harq_process->TBS,harq_process->mcs,harq_process->nb_rb, harq_process->round);
//#endif
harq_process->status = SCH_IDLE;
@@ -669,12 +682,12 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
harq_process->harq_ack.harq_id = harq_pid;
harq_process->harq_ack.send_harq_status = 1;
//LOG_I(PHY,"[UE %d] DLSCH: Setting ACK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d)\n",
//LOG_D(PHY,"[UE %d] DLSCH: Setting ACK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d)\n",
// phy_vars_ue->Mod_id, frame, subframe, harq_pid, harq_process->status, harq_process->round,harq_process->TBS,harq_process->mcs);
if(is_crnti)
{
LOG_I(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d (pid %d, round %d, TBS %d)\n",phy_vars_ue->Mod_id,nr_tti_rx,harq_pid,harq_process->round,harq_process->TBS);
LOG_D(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d (pid %d, round %d, TBS %d)\n",phy_vars_ue->Mod_id,nr_tti_rx,harq_pid,harq_process->round,harq_process->TBS);
}
//LOG_D(PHY,"[UE %d] DLSCH: Setting ACK for subframe %d (pid %d, round %d)\n",phy_vars_ue->Mod_id,subframe,harq_pid,harq_process->round);
@@ -695,10 +708,12 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
for (r=0; r<harq_process->C; r++) {
AssertFatal(p_nrLDPC_procBuf[0]->llrProcBuf!=NULL,"7. llProcBuf is null (r %d)!\n",r);
memcpy(harq_process->b+offset,
harq_process->c[r],
Kr_bytes- - (harq_process->F>>3) -((harq_process->C>1)?3:0));
harq_process->c[r],
Kr_bytes- - (harq_process->F>>3) -((harq_process->C>1)?3:0));
offset += (Kr_bytes - (harq_process->F>>3) - ((harq_process->C>1)?3:0));
AssertFatal(p_nrLDPC_procBuf[0]->llrProcBuf!=NULL,"8. llProcBuf is null (r %d)!\n",r);
#ifdef DEBUG_DLSCH_DECODING
printf("Segment %u : Kr= %u bytes\n",r,Kr_bytes);
@@ -730,6 +745,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
dlsch->last_iteration_cnt = ret;
AssertFatal(p_nrLDPC_procBuf[0]->llrProcBuf!=NULL,"Exit 2. llProcBuf is null!\n");
return(ret);
}
@@ -850,7 +866,7 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue,
G = harq_process->G;
LOG_I(PHY,"DLSCH Decoding main, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb);
LOG_D(PHY,"DLSCH Decoding main, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb);
proc->decoder_main_available = 1;
@@ -1109,7 +1125,7 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue,
if (err_flag == 0) {
/*
LOG_I(PHY, "LDPC algo Kr=%d cb_cnt=%d C=%d nbRB=%d crc_type %d TBSInput=%d TBSHarq=%d TBSplus24=%d mcs=%d Qm=%d RIV=%d round=%d maxIter %d\n",
LOG_D(PHY, "LDPC algo Kr=%d cb_cnt=%d C=%d nbRB=%d crc_type %d TBSInput=%d TBSHarq=%d TBSplus24=%d mcs=%d Qm=%d RIV=%d round=%d maxIter %d\n",
Kr,r,harq_process->C,harq_process->nb_rb,crc_type,A,harq_process->TBS,
harq_process->B,harq_process->mcs,harq_process->Qm,harq_process->rvidx,harq_process->round,dlsch->max_ldpc_iterations);
*/
@@ -1222,7 +1238,7 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue,
if (err_flag == 1) {
#if UE_DEBUG_TRACE
LOG_I(PHY,"[UE %d] DLSCH: Setting NAK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d) Kr %d r %d harq_process->round %d\n",
LOG_D(PHY,"[UE %d] DLSCH: Setting NAK for SFN/SF %d/%d (pid %d, status %d, round %d, TBS %d, mcs %d) Kr %d r %d harq_process->round %d\n",
phy_vars_ue->Mod_id, frame, nr_tti_rx, harq_pid,harq_process->status, harq_process->round,harq_process->TBS,harq_process->mcs,Kr,r,harq_process->round);
#endif
harq_process->harq_ack.ack = 0;
@@ -1246,7 +1262,7 @@ uint32_t nr_dlsch_decoding_mthread(PHY_VARS_NR_UE *phy_vars_ue,
return((1+dlsch->max_ldpc_iterations));
} else {
#if UE_DEBUG_TRACE
LOG_I(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d TBS %d mcs %d nb_rb %d\n",
LOG_D(PHY,"[UE %d] DLSCH: Setting ACK for nr_tti_rx %d TBS %d mcs %d nb_rb %d\n",
phy_vars_ue->Mod_id,nr_tti_rx,harq_process->TBS,harq_process->mcs,harq_process->nb_rb);
#endif
@@ -1429,7 +1445,7 @@ void *nr_dlsch_decoding_process(void *arg)
harq_process->G = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, harq_process->Qm,harq_process->Nl);
G = harq_process->G;
LOG_I(PHY,"DLSCH Decoding process, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb);
LOG_D(PHY,"DLSCH Decoding process, harq_pid %d TBS %d G %d mcs %d Nl %d nb_symb_sch %d nb_rb %d\n",harq_pid,A,G, harq_process->mcs, harq_process->Nl, nb_symb_sch,nb_rb);
if ((harq_process->R)<1024)
Coderate = (float) (harq_process->R) /(float) 1024;
@@ -1646,7 +1662,7 @@ void *nr_dlsch_decoding_process(void *arg)
if (err_flag == 0) {
/*
LOG_I(PHY, "turbo algo Kr=%d cb_cnt=%d C=%d nbRB=%d crc_type %d TBSInput=%d TBSHarq=%d TBSplus24=%d mcs=%d Qm=%d RIV=%d round=%d maxIter %d\n",
LOG_D(PHY, "turbo algo Kr=%d cb_cnt=%d C=%d nbRB=%d crc_type %d TBSInput=%d TBSHarq=%d TBSplus24=%d mcs=%d Qm=%d RIV=%d round=%d maxIter %d\n",
Kr,r,harq_process->C,harq_process->nb_rb,crc_type,A,harq_process->TBS,
harq_process->B,harq_process->mcs,harq_process->Qm,harq_process->rvidx,harq_process->round,dlsch->max_ldpc_iterations);
*/
@@ -1690,16 +1706,16 @@ void *nr_dlsch_decoding_process(void *arg)
// Fixme: correct type is unsigned, but nrLDPC_decoder and all called behind use signed int
if (check_crc((uint8_t*)llrProcBuf,length_dec,harq_process->F,crc_type)) {
printf("Segment %u CRC OK\n",r);
LOG_D(PHY,"Segment %u CRC OK\n",r);
ret = 2;
}
else {
printf("CRC NOK\n");
LOG_D(PHY,"Segment %u CRC NOK\n",r);
ret = 1+dlsch->max_ldpc_iterations;
}
if (no_iteration_ldpc > 10)
printf("Error number of iteration LPDC %d\n", no_iteration_ldpc);
LOG_D(PHY,"Error number of iteration LPDC %d\n", no_iteration_ldpc);
//else
//printf("OK number of iteration LPDC %d\n", no_iteration_ldpc);
openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c
+52 -51
View File
@@ -101,16 +101,16 @@ static void nr_dlsch_layer_demapping(int16_t **llr_cw,
int16_t **llr_layers);
int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
PDSCH_t type,
unsigned char eNB_id,
unsigned char eNB_id_i, //if this == ue->n_connected_eNB, we assume MU interference
uint32_t frame,
uint8_t nr_tti_rx,
unsigned char symbol,
unsigned char first_symbol_flag,
RX_type_t rx_type,
unsigned char i_mod,
unsigned char harq_pid)
PDSCH_t type,
unsigned char eNB_id,
unsigned char eNB_id_i, //if this == ue->n_connected_eNB, we assume MU interference
uint32_t frame,
uint8_t nr_tti_rx,
unsigned char symbol,
unsigned char first_symbol_flag,
RX_type_t rx_type,
unsigned char i_mod,
unsigned char harq_pid)
{
NR_UE_COMMON *common_vars = &ue->common_vars;
@@ -151,7 +151,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
//int16_t *pllr_symbol_cw1_deint;
uint32_t llr_offset_symbol;
//uint16_t bundle_L = 2;
uint8_t l0 =2, pilots=0;
uint8_t pilots=0;
uint16_t n_tx=1, n_rx=1;
int32_t median[16];
uint32_t len;
@@ -234,7 +234,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
start_rb = dlsch0_harq->start_rb;
nb_rb_pdsch = dlsch0_harq->nb_rb;
l0 = dlsch0_harq->start_symbol;
int lbar;
DevAssert(dlsch0_harq);
round = dlsch0_harq->round;
@@ -286,7 +286,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
printf("Demod dlsch0_harq->pmi_alloc %d\n", dlsch0_harq->pmi_alloc);
#endif
pilots = (symbol==l0) ? 1 : 0;
pilots = ((1<<symbol)&dlsch0_harq->dlDmrsSymbPos)>0 ? 1 : 0;
if (frame_parms->nb_antenna_ports_eNB>1 && beamforming_mode==0) {
#ifdef DEBUG_DLSCH_MOD
@@ -297,19 +297,19 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
start_meas(&ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot]);
#endif
nb_rb = nr_dlsch_extract_rbs_dual(common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[nr_tti_rx]].rxdataF,
pdsch_vars[eNB_id]->dl_ch_estimates,
pdsch_vars[eNB_id]->rxdataF_ext,
pdsch_vars[eNB_id]->dl_ch_estimates_ext,
dlsch0_harq->pmi_alloc,
pdsch_vars[eNB_id]->pmi_ext,
symbol,
pilots,
start_rb,
nb_rb_pdsch,
nr_tti_rx,
ue->high_speed_flag,
frame_parms,
dlsch0_harq->mimo_mode);
pdsch_vars[eNB_id]->dl_ch_estimates,
pdsch_vars[eNB_id]->rxdataF_ext,
pdsch_vars[eNB_id]->dl_ch_estimates_ext,
dlsch0_harq->pmi_alloc,
pdsch_vars[eNB_id]->pmi_ext,
symbol,
pilots,
start_rb,
nb_rb_pdsch,
nr_tti_rx,
ue->high_speed_flag,
frame_parms,
dlsch0_harq->mimo_mode);
#ifdef DEBUG_DLSCH_MOD
printf("dlsch: using pmi %lx, pmi_ext ",pmi2hex_2Ar1(dlsch0_harq->pmi_alloc));
for (rb=0;rb<nb_rb;rb++)
@@ -352,18 +352,18 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
} else if (beamforming_mode==0) { //else if nb_antennas_ports_eNB==1 && beamforming_mode == 0
//printf("start nr dlsch extract nr_tti_rx %d thread id %d \n", nr_tti_rx, ue->current_thread_id[nr_tti_rx]);
nb_rb = nr_dlsch_extract_rbs_single(common_vars->common_vars_rx_data_per_thread[ue->current_thread_id[nr_tti_rx]].rxdataF,
pdsch_vars[eNB_id]->dl_ch_estimates,
pdsch_vars[eNB_id]->rxdataF_ext,
pdsch_vars[eNB_id]->dl_ch_estimates_ext,
dlsch0_harq->pmi_alloc,
pdsch_vars[eNB_id]->pmi_ext,
symbol,
pilots,
start_rb,
nb_rb_pdsch,
nr_tti_rx,
ue->high_speed_flag,
frame_parms);
pdsch_vars[eNB_id]->dl_ch_estimates,
pdsch_vars[eNB_id]->rxdataF_ext,
pdsch_vars[eNB_id]->dl_ch_estimates_ext,
dlsch0_harq->pmi_alloc,
pdsch_vars[eNB_id]->pmi_ext,
symbol,
pilots,
start_rb,
nb_rb_pdsch,
nr_tti_rx,
ue->high_speed_flag,
frame_parms);
} /*else if(beamforming_mode>7) {
LOG_W(PHY,"dlsch_demodulation: beamforming mode not supported yet.\n");
@@ -375,7 +375,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
return(-1);
}
len = (symbol==l0)? (nb_rb*6):(nb_rb*12);
len = (pilots==1)? (nb_rb*6):(nb_rb*12);
#if UE_TIMING_TRACE
stop_meas(&ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot]);
@@ -395,11 +395,11 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
n_rx = frame_parms->nb_antennas_rx;
nr_dlsch_scale_channel(pdsch_vars[eNB_id]->dl_ch_estimates_ext,
frame_parms,
dlsch,
symbol,
pilots,
nb_rb);
frame_parms,
dlsch,
symbol,
pilots,
nb_rb);
#if UE_TIMING_TRACE
stop_meas(&ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot]);
@@ -648,13 +648,14 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
#endif
#if UE_TIMING_TRACE
start_meas(&ue->generic_stat_bis[ue->current_thread_id[nr_tti_rx]][slot]);
#endif
//printf("LLR dlsch0_harq->Qm %d rx_type %d cw0 %d cw1 %d symbol %d \n",dlsch0_harq->Qm,rx_type,codeword_TB0,codeword_TB1,symbol);
// compute LLRs
// -> // compute @pointer where llrs should filled for this ofdm-symbol
pdsch_vars[eNB_id]->llr_offset[l0-1] = 0;
if (first_symbol_flag==1) pdsch_vars[eNB_id]->llr_offset[symbol-1] = 0;
llr_offset_symbol = pdsch_vars[eNB_id]->llr_offset[symbol-1];
//pllr_symbol_cw0_deint = (int8_t*)pdsch_vars[eNB_id]->llr[0];
//pllr_symbol_cw1_deint = (int8_t*)pdsch_vars[eNB_id]->llr[1];
@@ -1788,11 +1789,11 @@ void nr_dlsch_channel_compensation_core(int **rxdataF_ext,
void nr_dlsch_scale_channel(int **dl_ch_estimates_ext,
NR_DL_FRAME_PARMS *frame_parms,
NR_UE_DLSCH_t **dlsch_ue,
uint8_t symbol,
uint8_t pilots,
unsigned short nb_rb)
NR_DL_FRAME_PARMS *frame_parms,
NR_UE_DLSCH_t **dlsch_ue,
uint8_t symbol,
uint8_t pilots,
unsigned short nb_rb)
{
#if defined(__x86_64__)||defined(__i386__)
@@ -1808,7 +1809,7 @@ void nr_dlsch_scale_channel(int **dl_ch_estimates_ext,
// Determine scaling amplitude based the symbol
ch_amp = 1024*8; //((pilots) ? (dlsch_ue[0]->sqrt_rho_b) : (dlsch_ue[0]->sqrt_rho_a));
ch_amp = 1024*8; //((pilots) ? (dlsch_ue[0]->sqrt_rho_b) : (dlsch_ue[0]->sqrt_rho_a));
LOG_D(PHY,"Scaling PDSCH Chest in OFDM symbol %d by %d, pilots %d nb_rb %d NCP %d symbol %d\n",symbol,ch_amp,pilots,nb_rb,frame_parms->Ncp,symbol);
// printf("Scaling PDSCH Chest in OFDM symbol %d by %d\n",symbol_mod,ch_amp);
openair1/PHY/NR_UE_TRANSPORT/nr_pbch.c
+1 -1
View File
@@ -538,7 +538,7 @@ int nr_rx_pbch( PHY_VARS_NR_UE *ue,
uint32_t unscrambling_mask = (Lmax==64)?0x100006D:0x1000041;
nr_pbch_unscrambling(nr_ue_pbch_vars,frame_parms->Nid_cell,nushift,M,NR_POLAR_PBCH_E,0,0);
//polar decoding de-rate matching
const t_nrPolar_params *currentPtr = nr_polar_params( NR_POLAR_PBCH_MESSAGE_TYPE, NR_POLAR_PBCH_PAYLOAD_BITS, NR_POLAR_PBCH_AGGREGATION_LEVEL,1);
const t_nrPolar_params *currentPtr = nr_polar_params( NR_POLAR_PBCH_MESSAGE_TYPE, NR_POLAR_PBCH_PAYLOAD_BITS, NR_POLAR_PBCH_AGGREGATION_LEVEL,1,ue->polarList);
decoderState = polar_decoder_int16(pbch_e_rx,(uint64_t *)&nr_ue_pbch_vars->pbch_a_prime,0,currentPtr);
if(decoderState) return(decoderState);
openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h
+12 -62
View File
@@ -1113,6 +1113,7 @@ void *nr_dlsch_decoding_2thread0(void *arg);
void *nr_dlsch_decoding_2thread1(void *arg);
void nr_dlsch_unscrambling(int16_t* llr,
uint32_t size,
uint8_t q,
@@ -1124,17 +1125,10 @@ uint32_t dlsch_decoding_emul(PHY_VARS_NR_UE *phy_vars_ue,
PDSCH_t dlsch_id,
uint8_t eNB_id);
int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
uint32_t frame,
uint8_t nr_tti_rx,
uint8_t eNB_id,
MIMO_mode_t mimo_mode,
uint32_t high_speed_flag,
uint8_t is_secondary_ue,
int nb_coreset_active,
uint16_t symbol_mon,
NR_SEARCHSPACE_TYPE_t searchSpaceType);
uint32_t slot);
/*! \brief Extract PSS and SSS resource elements
@param phy_vars_ue Pointer to UE variables
@@ -1544,10 +1538,9 @@ uint8_t get_num_pdcch_symbols(uint8_t num_dci,DCI_ALLOC_t *dci_alloc,NR_DL_FRAME
void pdcch_interleaving(NR_DL_FRAME_PARMS *frame_parms,int32_t **z, int32_t **wbar,uint8_t n_symbols_pdcch,uint8_t mi);
void pdcch_unscrambling(NR_DL_FRAME_PARMS *frame_parms,
uint8_t subframe,
int8_t* llr,
uint32_t length);
void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t slot,
int16_t *z, uint32_t length, uint16_t pdcch_DMRS_scrambling_id);
@@ -1711,46 +1704,14 @@ uint8_t get_prach_prb_offset(NR_DL_FRAME_PARMS *frame_parms,
uint8_t n_ra_prboffset,
uint8_t tdd_mapindex, uint16_t Nf);
void nr_pdcch_unscrambling(uint16_t crnti, NR_DL_FRAME_PARMS *frame_parms, uint8_t nr_tti_rx,
int16_t *z, uint32_t length, uint16_t pdcch_DMRS_scrambling_id, int do_common);
uint32_t lte_gold_generic(uint32_t *x1, uint32_t *x2, uint8_t reset);
uint8_t nr_dci_decoding_procedure(int s,
int p,
PHY_VARS_NR_UE *ue,
NR_DCI_ALLOC_t *dci_alloc,
NR_SEARCHSPACE_TYPE_t searchSpacetype,
int16_t eNB_id,
uint8_t nr_tti_rx,
uint8_t dci_fields_sizes_cnt[MAX_NR_DCI_DECODED_SLOT][NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
uint16_t n_RB_ULBWP,
uint16_t n_RB_DLBWP,
crc_scrambled_t *crc_scrambled,
format_found_t *format_found,
uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES]);
uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
int frame,
int slot,
fapi_nr_dci_indication_t *dci_ind);
int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue,
uint8_t eNB_id,
int frame,
uint8_t nr_tti_rx,
uint64_t dci_pdu[2],
uint16_t rnti,
uint8_t dci_length,
NR_DCI_format_t dci_format,
NR_UE_PDCCH *pdcch_vars,
NR_UE_PDSCH *pdsch_vars,
NR_UE_DLSCH_t **dlsch,
NR_UE_ULSCH_t *ulsch,
NR_DL_FRAME_PARMS *frame_parms,
PDSCH_CONFIG_DEDICATED *pdsch_config_dedicated,
uint8_t beamforming_mode,
uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
uint16_t n_RB_ULBWP,
uint16_t n_RB_DLBWP,
uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES],
NR_DCI_INFO_EXTRACTED_t *nr_dci_info_extracted);
/** \brief This function is the top-level entry point to PDSCH demodulation, after frequency-domain transformation and channel estimation. It performs
- RB extraction (signal and channel estimates)
@@ -1794,22 +1755,11 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
uint8_t is_crnti,
uint8_t llr8_flag);
int nr_extract_dci_info(PHY_VARS_NR_UE *ue,
uint8_t eNB_id,
lte_frame_type_t frame_type,
uint8_t dci_length,
uint16_t rnti,
uint64_t dci_pdu[2],
fapi_nr_dci_pdu_rel15_t *nr_pdci_info_extracted,
uint8_t dci_fields_sizes[NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
NR_DCI_format_t dci_format,
uint8_t nr_tti_rx,
uint16_t n_RB_ULBWP,
uint16_t n_RB_DLBWP,
uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES]);
int32_t generate_nr_prach( PHY_VARS_NR_UE *ue, uint8_t eNB_id, uint8_t subframe, uint16_t Nf );
void *dlsch_thread(void *arg);
/**@}*/
#endif
openair1/PHY/NR_UE_TRANSPORT/nr_transport_ue.h
+8 -2
View File
@@ -255,8 +255,6 @@ typedef struct {
uint8_t DCINdi;
/// DLSCH status flag indicating
SCH_status_t status;
/// Dynamic Configuration from FAPI
nfapi_nr_dl_tti_pdsch_pdu_rel15_t dl_config_pdu;
/// Transport block size
uint32_t TBS;
/// The payload + CRC size in bits
@@ -301,12 +299,20 @@ typedef struct {
int8_t delta_PUCCH;
/// Number of soft channel bits
uint32_t G;
/// Start PRB of BWP
uint16_t BWPStart;
/// Number of PRBs in BWP
uint16_t BWPSize;
/// Current Number of RBs
uint16_t nb_rb;
/// Starting RB number
uint16_t start_rb;
/// Number of Symbols
uint16_t nb_symbols;
/// DMRS symbol positions
uint16_t dlDmrsSymbPos;
/// DMRS Configuration Type
uint8_t dmrsConfigType;
/// Starting Symbol number
uint16_t start_symbol;
/// Current subband PMI allocation
openair1/PHY/TOOLS/lte_dfts.c
+20 -16
View File
@@ -4836,22 +4836,22 @@ void idft4096(int16_t *x,int16_t *y,int scale)
if (scale>0) {
for (i=0; i<64; i++) {
y128[0] = shiftright_int16(y128[0],1);
y128[1] = shiftright_int16(y128[1],1);
y128[2] = shiftright_int16(y128[2],1);
y128[3] = shiftright_int16(y128[3],1);
y128[4] = shiftright_int16(y128[4],1);
y128[5] = shiftright_int16(y128[5],1);
y128[6] = shiftright_int16(y128[6],1);
y128[7] = shiftright_int16(y128[7],1);
y128[8] = shiftright_int16(y128[8],1);
y128[9] = shiftright_int16(y128[9],1);
y128[10] = shiftright_int16(y128[10],1);
y128[11] = shiftright_int16(y128[11],1);
y128[12] = shiftright_int16(y128[12],1);
y128[13] = shiftright_int16(y128[13],1);
y128[14] = shiftright_int16(y128[14],1);
y128[15] = shiftright_int16(y128[15],1);
y128[0] = shiftright_int16(y128[0],scale);
y128[1] = shiftright_int16(y128[1],scale);
y128[2] = shiftright_int16(y128[2],scale);
y128[3] = shiftright_int16(y128[3],scale);
y128[4] = shiftright_int16(y128[4],scale);
y128[5] = shiftright_int16(y128[5],scale);
y128[6] = shiftright_int16(y128[6],scale);
y128[7] = shiftright_int16(y128[7],scale);
y128[8] = shiftright_int16(y128[8],scale);
y128[9] = shiftright_int16(y128[9],scale);
y128[10] = shiftright_int16(y128[10],scale);
y128[11] = shiftright_int16(y128[11],scale);
y128[12] = shiftright_int16(y128[12],scale);
y128[13] = shiftright_int16(y128[13],scale);
y128[14] = shiftright_int16(y128[14],scale);
y128[15] = shiftright_int16(y128[15],scale);
y128+=16;
}
@@ -8591,6 +8591,8 @@ void dft1200(int16_t *x,int16_t *y,unsigned char scale_flag)
}
//#define round trunc
void init_rad4(int N,int16_t *tw) {
int16_t *twa = tw;
@@ -8760,6 +8762,8 @@ void init_dfts(void)
init_rad4_rep(1200,twa1200,twb1200,twc1200);
}
//#undef round
#ifdef MR_MAIN
#include <string.h>
#include <stdio.h>
openair1/PHY/TOOLS/tools_defs.h
-2
View File
@@ -32,8 +32,6 @@
#include <stdint.h>
#include "PHY/sse_intrin.h"
#define CEILIDIV(a,b) ((a+b-1)/b)
#define ROUNDIDIV(a,b) (((a<<1)+b)/(b<<1))
struct complex {
double x;
openair1/PHY/defs_gNB.h
+16 -104
View File
@@ -632,17 +632,12 @@ typedef struct PHY_VARS_gNB_s {
nr_cce_t cce_list[MAX_DCI_CORESET][NR_MAX_PDCCH_AGG_LEVEL];
NR_gNB_COMMON common_vars;
NR_gNB_PRACH prach_vars;
NR_gNB_PUSCH *pusch_vars[NUMBER_OF_UE_MAX];
NR_gNB_PUSCH *pusch_vars[NUMBER_OF_NR_ULSCH_MAX];
NR_gNB_DLSCH_t *dlsch[NUMBER_OF_NR_DLSCH_MAX][2]; // Nusers times two spatial streams
NR_gNB_ULSCH_t *ulsch[NUMBER_OF_NR_ULSCH_MAX][2]; // [Nusers times][2 codewords]
NR_gNB_DLSCH_t *dlsch_SI,*dlsch_ra,*dlsch_p;
NR_gNB_DLSCH_t *dlsch_PCH;
/*
LTE_eNB_UE_stats UE_stats[NUMBER_OF_UE_MAX];
LTE_eNB_UE_stats *UE_stats_ptr[NUMBER_OF_UE_MAX];
*/
uint8_t pbch_configured;
// uint8_t pbch_pdu[4]; //PBCH_PDU_SIZE
char gNB_generate_rar;
/// NR synchronization sequences
@@ -665,7 +660,7 @@ typedef struct PHY_VARS_gNB_s {
uint32_t nr_gold_pusch[2][20][2][NR_MAX_PUSCH_DMRS_INIT_LENGTH_DWORD];
/// Indicator set to 0 after first SR
uint8_t first_sr[NUMBER_OF_UE_MAX];
uint8_t first_sr[NUMBER_OF_NR_SR_MAX];
/// PRACH root sequence
uint32_t X_u[64][839];
@@ -679,7 +674,6 @@ typedef struct PHY_VARS_gNB_s {
/// N0 (used for abstraction)
double N0;
unsigned char first_run_timing_advance[NUMBER_OF_UE_MAX];
unsigned char first_run_I0_measurements;
@@ -697,89 +691,29 @@ typedef struct PHY_VARS_gNB_s {
/// counter to average prach energh over first 100 prach opportunities
int prach_energy_counter;
// PDSCH Variables
PDSCH_CONFIG_DEDICATED pdsch_config_dedicated[NUMBER_OF_UE_MAX];
// PUSCH Varaibles
PUSCH_CONFIG_DEDICATED pusch_config_dedicated[NUMBER_OF_UE_MAX];
// PUCCH variables
PUCCH_CONFIG_DEDICATED pucch_config_dedicated[NUMBER_OF_UE_MAX];
// UL-POWER-Control
UL_POWER_CONTROL_DEDICATED ul_power_control_dedicated[NUMBER_OF_UE_MAX];
// TPC
TPC_PDCCH_CONFIG tpc_pdcch_config_pucch[NUMBER_OF_UE_MAX];
TPC_PDCCH_CONFIG tpc_pdcch_config_pusch[NUMBER_OF_UE_MAX];
// CQI reporting
CQI_REPORT_CONFIG cqi_report_config[NUMBER_OF_UE_MAX];
// SRS Variables
SOUNDINGRS_UL_CONFIG_DEDICATED soundingrs_ul_config_dedicated[NUMBER_OF_UE_MAX];
uint8_t ncs_cell[20][7];
// Scheduling Request Config
SCHEDULING_REQUEST_CONFIG scheduling_request_config[NUMBER_OF_UE_MAX];
// Transmission mode per UE
uint8_t transmission_mode[NUMBER_OF_UE_MAX];
/// cba_last successful reception for each group, used for collision detection
uint8_t cba_last_reception[4];
// Pointers for active physicalConfigDedicated to be applied in current slot
struct PhysicalConfigDedicated *physicalConfigDedicated[NUMBER_OF_UE_MAX];
uint32_t rb_mask_ul[4];
/// Information regarding TM5
MU_MIMO_mode mu_mimo_mode[NUMBER_OF_UE_MAX];
/// target_ue_dl_mcs : only for debug purposes
uint32_t target_ue_dl_mcs;
/// target_ue_ul_mcs : only for debug purposes
uint32_t target_ue_ul_mcs;
/// target_ue_dl_rballoc : only for debug purposes
uint32_t ue_dl_rb_alloc;
/// target ul PRBs : only for debug
uint32_t ue_ul_nb_rb;
///check for Total Transmissions
uint32_t check_for_total_transmissions;
///check for MU-MIMO Transmissions
uint32_t check_for_MUMIMO_transmissions;
///check for SU-MIMO Transmissions
uint32_t check_for_SUMIMO_transmissions;
///check for FULL MU-MIMO Transmissions
uint32_t FULL_MUMIMO_transmissions;
/// Counter for total bitrate, bits and throughput in downlink
uint32_t total_dlsch_bitrate;
uint32_t total_transmitted_bits;
uint32_t total_system_throughput;
int hw_timing_advance;
/*
time_stats_t phy_proc;
*/
time_stats_t phy_proc_tx;
/*
time_stats_t phy_proc_rx;
*/
time_stats_t rx_prach;
/*
time_stats_t ofdm_mod_stats;
*/
time_stats_t dlsch_encoding_stats;
time_stats_t dlsch_modulation_stats;
time_stats_t dlsch_scrambling_stats;
time_stats_t tinput;
time_stats_t tprep;
time_stats_t tparity;
time_stats_t toutput;
time_stats_t dlsch_rate_matching_stats;
time_stats_t dlsch_turbo_encoding_stats;
time_stats_t dlsch_interleaving_stats;
time_stats_t dlsch_segmentation_stats;
/*
time_stats_t rx_dft_stats;
time_stats_t ulsch_channel_estimation_stats;
time_stats_t ulsch_freq_offset_estimation_stats;
@@ -790,29 +724,7 @@ typedef struct PHY_VARS_gNB_s {
time_stats_t ulsch_deinterleaving_stats;
time_stats_t ulsch_demultiplexing_stats;
time_stats_t ulsch_llr_stats;
time_stats_t ulsch_tc_init_stats;
time_stats_t ulsch_tc_alpha_stats;
time_stats_t ulsch_tc_beta_stats;
time_stats_t ulsch_tc_gamma_stats;
time_stats_t ulsch_tc_ext_stats;
time_stats_t ulsch_tc_intl1_stats;
time_stats_t ulsch_tc_intl2_stats;
#ifdef LOCALIZATION
/// time state for localization
time_stats_t localization_stats;
#endif
int32_t pucch1_stats_cnt[NUMBER_OF_UE_MAX][10];
int32_t pucch1_stats[NUMBER_OF_UE_MAX][10*1024];
int32_t pucch1_stats_thres[NUMBER_OF_UE_MAX][10*1024];
int32_t pucch1ab_stats_cnt[NUMBER_OF_UE_MAX][10];
int32_t pucch1ab_stats[NUMBER_OF_UE_MAX][2*10*1024];
int32_t pusch_stats_rb[NUMBER_OF_UE_MAX][10240];
int32_t pusch_stats_round[NUMBER_OF_UE_MAX][10240];
int32_t pusch_stats_mcs[NUMBER_OF_UE_MAX][10240];
int32_t pusch_stats_bsr[NUMBER_OF_UE_MAX][10240];
int32_t pusch_stats_BO[NUMBER_OF_UE_MAX][10240];
*/
} PHY_VARS_gNB;
#endif
openair1/PHY/defs_nr_UE.h
+7 -66
View File
@@ -45,6 +45,7 @@
#include <math.h>
#include "common_lib.h"
#include "msc.h"
#include "fapi_nr_ue_interface.h"
//#include <complex.h>
#include "assertions.h"
@@ -470,65 +471,7 @@ typedef struct {
#ifdef NR_PDCCH_DEFS_NR_UE
#define MAX_NR_DCI_DECODED_SLOT 10 // This value is not specified
#define NBR_NR_FORMATS 8 // The number of formats is 8 (0_0, 0_1, 1_0, 1_1, 2_0, 2_1, 2_2, 2_3)
#define NBR_NR_DCI_FIELDS 56 // The number of different dci fields defined in TS 38.212 subclause 7.3.1
#define IDENTIFIER_DCI_FORMATS 0
#define CARRIER_IND 1
#define SUL_IND_0_1 2
#define SLOT_FORMAT_IND 3
#define PRE_EMPTION_IND 4
#define BLOCK_NUMBER 5
#define CLOSE_LOOP_IND 6
#define BANDWIDTH_PART_IND 7
#define SHORT_MESSAGE_IND 8
#define SHORT_MESSAGES 9
#define FREQ_DOM_RESOURCE_ASSIGNMENT_UL 10
#define FREQ_DOM_RESOURCE_ASSIGNMENT_DL 11
#define TIME_DOM_RESOURCE_ASSIGNMENT 12
#define VRB_TO_PRB_MAPPING 13
#define PRB_BUNDLING_SIZE_IND 14
#define RATE_MATCHING_IND 15
#define ZP_CSI_RS_TRIGGER 16
#define FREQ_HOPPING_FLAG 17
#define TB1_MCS 18
#define TB1_NDI 19
#define TB1_RV 20
#define TB2_MCS 21
#define TB2_NDI 22
#define TB2_RV 23
#define MCS 24
#define NDI 25
#define RV 26
#define HARQ_PROCESS_NUMBER 27
#define DAI_ 28
#define FIRST_DAI 29
#define SECOND_DAI 30
#define TB_SCALING 31
#define TPC_PUSCH 32
#define TPC_PUCCH 33
#define PUCCH_RESOURCE_IND 34
#define PDSCH_TO_HARQ_FEEDBACK_TIME_IND 35
#define SRS_RESOURCE_IND 36
#define PRECOD_NBR_LAYERS 37
#define ANTENNA_PORTS 38
#define TCI 39
#define SRS_REQUEST 40
#define TPC_CMD 41
#define CSI_REQUEST 42
#define CBGTI 43
#define CBGFI 44
#define PTRS_DMRS 45
#define BETA_OFFSET_IND 46
#define DMRS_SEQ_INI 47
#define UL_SCH_IND 48
#define PADDING_NR_DCI 49
#define SUL_IND_0_0 50
#define RA_PREAMBLE_INDEX 51
#define SUL_IND_1_0 52
#define SS_PBCH_INDEX 53
#define PRACH_MASK_INDEX 54
#define RESERVED_NR_DCI 55
typedef enum {
@@ -759,12 +702,6 @@ typedef struct {
/// \brief PDCCH/DCI e-sequence (input to rate matching).
/// - first index: ? [0..96*N_RB_DL[
int16_t *e_rx;
/// number of PDCCH symbols in current subframe
uint8_t num_pdcch_symbols;
/// Allocated CRNTI for UE
uint16_t crnti;
/// 1: the allocated crnti is Temporary C-RNTI / 0: otherwise
uint8_t crnti_is_temporary;
/// Total number of PDU errors (diagnostic mode)
uint32_t dci_errors;
/// Total number of PDU received
@@ -773,11 +710,14 @@ typedef struct {
uint32_t dci_false;
/// Total number of DCI missed (diagnostic mode)
uint32_t dci_missed;
/// nCCE for PUCCH per subframe
/// nCCE for PDCCH per subframe
uint8_t nCCE[10];
//Check for specific DCIFormat and AgregationLevel
uint8_t dciFormat;
uint8_t agregationLevel;
int nb_search_space;
fapi_nr_dl_config_dci_dl_pdu_rel15_t pdcch_config[FAPI_NR_MAX_SS_PER_CORESET];
/*
#ifdef NR_PDCCH_DEFS_NR_UE
int nb_searchSpaces;
// CORESET structure, where maximum number of CORESETs to be handled is 3 (according to 38.331 V15.1.0)
@@ -788,7 +728,7 @@ typedef struct {
int n_RB_BWP[NR_NBR_SEARCHSPACE_ACT_BWP];
uint32_t nb_search_space;
#endif
#endif*/
} NR_UE_PDCCH;
#define PBCH_A 24
@@ -949,6 +889,7 @@ typedef struct {
// point to the current rxTx thread index
uint8_t current_thread_id[40];
t_nrPolar_params *polarList;
NR_UE_PDSCH *pdsch_vars[RX_NB_TH_MAX][NUMBER_OF_CONNECTED_eNB_MAX+1]; // two RxTx Threads
NR_UE_PDSCH_FLP *pdsch_vars_flp[NUMBER_OF_CONNECTED_eNB_MAX+1];
NR_UE_PDSCH *pdsch_vars_SI[NUMBER_OF_CONNECTED_eNB_MAX+1];
openair1/PHY/defs_nr_common.h
+1 -1
View File
@@ -102,7 +102,7 @@
#define NR_MAX_PUSCH_ENCODED_LENGTH NR_MAX_PDSCH_ENCODED_LENGTH
#define NR_MAX_PDSCH_TBS 3824
#define MAX_NUM_NR_DLSCH_SEGMENTS 16
#define MAX_NUM_NR_DLSCH_SEGMENTS 24
#define MAX_NR_DLSCH_PAYLOAD_BYTES (MAX_NUM_NR_DLSCH_SEGMENTS*1056)
#define MAX_NUM_NR_ULSCH_SEGMENTS MAX_NUM_NR_DLSCH_SEGMENTS
openair1/SCHED_NR/phy_procedures_nr_gNB.c
+8 -1
View File
@@ -207,7 +207,14 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB,
AMP, frame, slot, fp, 0,
&gNB->dlsch_encoding_stats,
&gNB->dlsch_scrambling_stats,
&gNB->dlsch_modulation_stats);
&gNB->dlsch_modulation_stats,
&gNB->tinput,
&gNB->tprep,
&gNB->tparity,
&gNB->toutput,
&gNB->dlsch_rate_matching_stats,
&gNB->dlsch_interleaving_stats,
&gNB->dlsch_segmentation_stats);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,0);
}
openair1/SCHED_NR_UE/fapi_nr_ue_l1.c
+12 -35
View File
@@ -54,7 +54,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response)
// Note: we have to handle the thread IDs for this. To be revisited completely.
uint8_t thread_id = PHY_vars_UE_g[module_id][cc_id]->current_thread_id[slot];
NR_UE_PDCCH *pdcch_vars2 = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[thread_id][0];
NR_UE_PDCCH *pdcch_vars = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[thread_id][0];
NR_UE_DLSCH_t *dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[thread_id][0][0];
NR_UE_ULSCH_t *ulsch0 = PHY_vars_UE_g[module_id][cc_id]->ulsch[thread_id][0][0];
//NR_DL_FRAME_PARMS frame_parms = PHY_vars_UE_g[module_id][cc_id]->frame_parms;
@@ -66,40 +66,14 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response)
if(scheduled_response->dl_config != NULL){
fapi_nr_dl_config_request_t *dl_config = scheduled_response->dl_config;
LOG_D(PHY,"Received %d DL pdus\n",dl_config->number_pdus);
pdcch_vars->nb_search_space = 0;
for(i=0; i<dl_config->number_pdus; ++i){
if(dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_DCI){
pdcch_vars2->nb_search_space = pdcch_vars2->nb_search_space + 1;
fapi_nr_dl_config_dci_dl_pdu_rel15_t *dci_config = &dl_config->dl_config_list[i].dci_config_pdu.dci_config_rel15;
pdcch_vars2->n_RB_BWP[i] = dci_config->N_RB_BWP;
pdcch_vars2->searchSpace[i].monitoringSymbolWithinSlot = dci_config->monitoring_symbols_within_slot;
pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel1 = dci_config->number_of_candidates[0];
pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel2 = dci_config->number_of_candidates[1];
pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel4 = dci_config->number_of_candidates[2];
pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel8 = dci_config->number_of_candidates[3];
pdcch_vars2->searchSpace[i].nrofCandidates_aggrlevel16 = dci_config->number_of_candidates[4];
pdcch_vars2->coreset[i].duration = dci_config->coreset.duration;
pdcch_vars2->coreset[i].frequencyDomainResources = dci_config->coreset.frequency_domain_resource;
pdcch_vars2->coreset[i].rb_offset = dci_config->coreset.rb_offset;
if(dci_config->coreset.cce_reg_mapping_type == CCE_REG_MAPPING_TYPE_INTERLEAVED){
pdcch_vars2->coreset[i].cce_reg_mappingType.shiftIndex = dci_config->coreset.cce_reg_interleaved_shift_index;
pdcch_vars2->coreset[i].cce_reg_mappingType.reg_bundlesize = dci_config->coreset.cce_reg_interleaved_reg_bundle_size;
pdcch_vars2->coreset[i].cce_reg_mappingType.interleaversize = dci_config->coreset.cce_reg_interleaved_interleaver_size;
}else{ //CCE_REG_MAPPING_TYPE_NON_INTERLEAVED
pdcch_vars2->coreset[i].cce_reg_mappingType.shiftIndex = 0;
pdcch_vars2->coreset[i].cce_reg_mappingType.reg_bundlesize = 6;
pdcch_vars2->coreset[i].cce_reg_mappingType.interleaversize = 1;
}
pdcch_vars2->coreset[i].precoderGranularity = dci_config->coreset.precoder_granularity;
//pdcch_vars2->coreset[i].tciStatesPDCCH;
//pdcch_vars2->coreset[i].tciPresentInDCI;
pdcch_vars2->coreset[i].pdcchDMRSScramblingID = dci_config->coreset.pdcch_dmrs_scrambling_id;
fapi_nr_dl_config_dci_dl_pdu_rel15_t *pdcch_config = &dl_config->dl_config_list[i].dci_config_pdu.dci_config_rel15;
memcpy((void*)&pdcch_vars->pdcch_config[pdcch_vars->nb_search_space],(void*)pdcch_config,sizeof(*pdcch_config));
pdcch_vars->nb_search_space = pdcch_vars->nb_search_space + 1;
LOG_D(PHY,"Number of DCI SearchSpaces %d\n",pdcch_vars->nb_search_space);
}else{ //FAPI_NR_DL_CONFIG_TYPE_DLSCH
// dlsch config pdu
@@ -113,11 +87,14 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response)
NR_DL_UE_HARQ_t *dlsch0_harq = dlsch0->harq_processes[current_harq_pid];
dlsch0_harq->BWPStart = dlsch_config_pdu->BWPStart;
dlsch0_harq->BWPSize = dlsch_config_pdu->BWPSize;
dlsch0_harq->nb_rb = dlsch_config_pdu->number_rbs;
dlsch0_harq->start_rb = dlsch_config_pdu->start_rb;
dlsch0_harq->nb_symbols = dlsch_config_pdu->number_symbols;
dlsch0_harq->start_symbol = dlsch_config_pdu->start_symbol;
dlsch0_harq->dlDmrsSymbPos = dlsch_config_pdu->dlDmrsSymbPos;
dlsch0_harq->dmrsConfigType = dlsch_config_pdu->dmrsConfigType;
dlsch0_harq->mcs = dlsch_config_pdu->mcs;
dlsch0_harq->DCINdi = dlsch_config_pdu->ndi;
dlsch0_harq->rvidx = dlsch_config_pdu->rv;
@@ -132,7 +109,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response)
}
}
}else{
pdcch_vars2->nb_search_space = 0;
pdcch_vars->nb_search_space = 0;
}
if(scheduled_response->ul_config != NULL){
openair1/SCHED_NR_UE/phy_procedures_nr_ue.c
+129 -209
View File
@@ -94,30 +94,15 @@ char mode_string[4][20] = {"NOT SYNCHED","PRACH","RAR","PUSCH"};
extern double cpuf;
int32_t nr_rx_pdcch(PHY_VARS_NR_UE *ue,
uint32_t frame,
uint8_t nr_tti_rx,
uint8_t eNB_id,
MIMO_mode_t mimo_mode,
uint32_t high_speed_flag,
uint8_t is_secondary_ue,
int nb_coreset_active,
uint16_t symbol_mon,
NR_SEARCHSPACE_TYPE_t searchSpaceType);
uint32_t slot);
uint8_t nr_dci_decoding_procedure(int s,
int p,
PHY_VARS_NR_UE *ue,
NR_DCI_ALLOC_t *dci_alloc,
NR_SEARCHSPACE_TYPE_t searchSpacetype,
int16_t eNB_id,
uint8_t nr_tti_rx,
uint8_t dci_fields_sizes_cnt[MAX_NR_DCI_DECODED_SLOT][NBR_NR_DCI_FIELDS][NBR_NR_FORMATS],
uint16_t n_RB_ULBWP,
uint16_t n_RB_DLBWP,
crc_scrambled_t *crc_scrambled,
format_found_t *format_found,
uint16_t crc_scrambled_values[TOTAL_NBR_SCRAMBLED_VALUES]);
uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
int frame,
int nr_tti_rx,
fapi_nr_dci_indication_t *dci_ind);
/*
int nr_generate_ue_ul_dlsch_params_from_dci(PHY_VARS_NR_UE *ue,
@@ -2803,10 +2788,15 @@ unsigned int get_tx_amp(int power_dBm, int power_max_dBm, int N_RB_UL, int nb_rb
#ifdef NR_PDCCH_SCHED
int nr_ue_pdcch_procedures(uint8_t eNB_id,
PHY_VARS_NR_UE *ue,
UE_nr_rxtx_proc_t *proc)
int nr_ue_pdcch_procedures(uint8_t gNB_id,
PHY_VARS_NR_UE *ue,
UE_nr_rxtx_proc_t *proc)
{
int frame_rx = proc->frame_rx;
int nr_tti_rx = proc->nr_tti_rx;
unsigned int dci_cnt=0;
/*
// unsigned int dci_cnt=0, i; //removed for nr_ue_pdcch_procedures and added in the loop for nb_coreset_active
#ifdef NR_PDCCH_SCHED_DEBUG
printf("<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Entering function nr_ue_pdcch_procedures() \n");
@@ -2815,10 +2805,10 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,
int frame_rx = proc->frame_rx;
int nr_tti_rx = proc->nr_tti_rx;
NR_DCI_ALLOC_t dci_alloc_rx[8];
/*
uint8_t next1_thread_id = ue->current_thread_id[nr_tti_rx]== (RX_NB_TH-1) ? 0:(ue->current_thread_id[nr_tti_rx]+1);
uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1);
*/
//uint8_t next1_thread_id = ue->current_thread_id[nr_tti_rx]== (RX_NB_TH-1) ? 0:(ue->current_thread_id[nr_tti_rx]+1);
//uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1);
// table dci_fields_sizes_cnt contains dci_fields_sizes for each time a dci is decoded in the slot
// each element represents the size in bits for each dci field, for each decoded dci -> [dci_cnt-1]
@@ -2871,22 +2861,22 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,
for (nb_searchspace_active=0; nb_searchspace_active<nb_searchspace_total; nb_searchspace_active++){
int nb_coreset_active=nb_searchspace_active;
//int do_pdcch_monitoring_current_slot=1; // this variable can be removed and fapi is handling
/*
* The following code has been removed as it is handled by higher layers (fapi)
*
// The following code has been removed as it is handled by higher layers (fapi)
//
// Verify that monitoring is required at the slot nr_tti_rx. We will run pdcch procedure only if do_pdcch_monitoring_current_slot=1
// For Type0-PDCCH searchspace, we need to calculate the monitoring slot from Tables 13-1 .. 13-15 in TS 38.213 Subsection 13
NR_UE_SLOT_PERIOD_OFFSET_t sl_period_offset_mon = pdcch_vars2->searchSpace[nb_searchspace_active].monitoringSlotPeriodicityAndOffset;
if (sl_period_offset_mon == nr_sl1) {
do_pdcch_monitoring_current_slot=1; // PDCCH monitoring in every slot
} else if (nr_tti_rx%(uint16_t)sl_period_offset_mon == pdcch_vars2->searchSpace[nb_searchspace_active].monitoringSlotPeriodicityAndOffset_offset) {
do_pdcch_monitoring_current_slot=1; // PDCCH monitoring in every monitoringSlotPeriodicityAndOffset slot with offset
}*/
/*
* FIXME
* For PDCCH monitoring when overlap with SS/PBCH according to 38.213 v15.1.0 Section 10
* To be implemented LATER !!!
*/
//NR_UE_SLOT_PERIOD_OFFSET_t sl_period_offset_mon = pdcch_vars2->searchSpace[nb_searchspace_active].monitoringSlotPeriodicityAndOffset;
//if (sl_period_offset_mon == nr_sl1) {
//do_pdcch_monitoring_current_slot=1; // PDCCH monitoring in every slot
//} else if (nr_tti_rx%(uint16_t)sl_period_offset_mon == pdcch_vars2->searchSpace[nb_searchspace_active].monitoringSlotPeriodicityAndOffset_offset) {
//do_pdcch_monitoring_current_slot=1; // PDCCH monitoring in every monitoringSlotPeriodicityAndOffset slot with offset
//}
// FIXME
// For PDCCH monitoring when overlap with SS/PBCH according to 38.213 v15.1.0 Section 10
// To be implemented LATER !!!
//int _offset,_index,_M;
//int searchSpace_id = pdcch_vars2->searchSpace[nb_searchspace_active].searchSpaceId;
@@ -2906,11 +2896,11 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,
// at the moment we will not take into consideration this variable and we will consider that the OFDM symbol offset is always the first OFDM in a symbol
uint16_t symbol_within_slot_mon = pdcch_vars2->searchSpace[nb_searchspace_active].monitoringSymbolWithinSlot;
// get the remaining parameters describing the current SEARCHSPACE: // FIXME! To be defined where we get this information from
/*NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L1 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel1;
NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L2 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel2;
NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L4 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel4;
NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L8 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel8;
NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L16 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel16;*/
//NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L1 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel1;
//NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L2 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel2;
//NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L4 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel4;
//NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L8 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel8;
//NR_UE_SEARCHSPACE_nbrCAND_t num_cand_L16 = pdcch_vars2->searchSpace[nb_searchspace_active].nrofCandidates_aggrlevel16;
// FIXME! A table of five enum elements
// searchSpaceType indicates whether this is a common search space or a UE-specific search space
//int searchSpaceType = pdcch_vars2->searchSpace[nb_searchspace_active].searchSpaceType.type;
@@ -2920,27 +2910,27 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,
searchSpaceType);
#endif
/*while ((searchSpace_coreset_id != pdcch_vars2->coreset[nb_coreset_active].controlResourceSetId) && (nb_coreset_active<nb_coreset_total)) {
//while ((searchSpace_coreset_id != pdcch_vars2->coreset[nb_coreset_active].controlResourceSetId) && (nb_coreset_active<nb_coreset_total)) {
// we need to identify the CORESET associated to the active searchSpace
nb_coreset_active++;
//nb_coreset_active++;
if (nb_coreset_active >= nb_coreset_total) return 0; // the coreset_id could not be found. There is a problem
}*/
}
/*
* we do not need these parameters yet
*
//we do not need these parameters yet
// get the parameters describing the current CORESET
int coreset_duration = pdcch_vars2->coreset[nb_coreset_active].duration;
uint64_t coreset_freq_dom = pdcch_vars2->coreset[nb_coreset_active].frequencyDomainResources;
int coreset_shift_index = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.shiftIndex;
NR_UE_CORESET_REG_bundlesize_t coreset_bundlesize = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.reg_bundlesize;
NR_UE_CORESET_interleaversize_t coreset_interleaversize = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.interleaversize;
NR_UE_CORESET_precoder_granularity_t precoder_granularity = pdcch_vars2->coreset[nb_coreset_active].precoderGranularity;
int tci_statesPDCCH = pdcch_vars2->coreset[nb_coreset_active].tciStatesPDCCH;
int tci_present = pdcch_vars2->coreset[nb_coreset_active].tciPresentInDCI;
uint16_t pdcch_DMRS_scrambling_id = pdcch_vars2->coreset[nb_coreset_active].pdcchDMRSScramblingID;
*/
//int coreset_duration = pdcch_vars2->coreset[nb_coreset_active].duration;
//uint64_t coreset_freq_dom = pdcch_vars2->coreset[nb_coreset_active].frequencyDomainResources;
//int coreset_shift_index = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.shiftIndex;
// NR_UE_CORESET_REG_bundlesize_t coreset_bundlesize = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.reg_bundlesize;
// NR_UE_CORESET_interleaversize_t coreset_interleaversize = pdcch_vars2->coreset[nb_coreset_active].cce_reg_mappingType.interleaversize;
// NR_UE_CORESET_precoder_granularity_t precoder_granularity = pdcch_vars2->coreset[nb_coreset_active].precoderGranularity;
// int tci_statesPDCCH = pdcch_vars2->coreset[nb_coreset_active].tciStatesPDCCH;
// int tci_present = pdcch_vars2->coreset[nb_coreset_active].tciPresentInDCI;
// uint16_t pdcch_DMRS_scrambling_id = pdcch_vars2->coreset[nb_coreset_active].pdcchDMRSScramblingID;
// A set of PDCCH candidates for a UE to monitor is defined in terms of PDCCH search spaces.
// Searchspace types:
@@ -2987,108 +2977,53 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,
searchSpaceType);
#endif
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RX_PDCCH, VCD_FUNCTION_OUT);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DCI_DECODING, VCD_FUNCTION_IN);
*/
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RX_PDCCH, VCD_FUNCTION_IN);
nr_rx_pdcch(ue,
proc->frame_rx,
nr_tti_rx);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_RX_PDCCH, VCD_FUNCTION_OUT);
crc_scrambled_t crc_scrambled;
format_found_t format_found=255;
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DCI_DECODING, VCD_FUNCTION_IN);
#ifdef NR_PDCCH_SCHED_DEBUG
printf("<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Entering function nr_dci_decoding_procedure with eNB_id=%d (n_RB_ULBWP=%d, n_RB_DLBWP=%d, searchSpaceType=%d, nb_searchspace_active=%d, nb_coreset_active=%d)\n",
eNB_id,
pdcch_vars2->n_RB_BWP[nb_searchspace_active],
pdcch_vars2->n_RB_BWP[nb_searchspace_active],
searchSpaceType,
nb_searchspace_active,
nb_coreset_active);
printf("<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Entering function nr_dci_decoding_procedure with (nb_searchspace_active=%d)\n",
pdcch_vars->nb_search_space);
#endif
dci_cnt += nr_dci_decoding_procedure(nb_searchspace_active,
nb_coreset_active,
ue,
&dci_alloc_rx[dci_cnt],
searchSpaceType, // if we're in PUSCH don't listen to common search space,
// later when we need paging or RA during connection, update this ...
eNB_id,
nr_tti_rx,
dci_fields_sizes_cnt,
pdcch_vars2->n_RB_BWP[nb_searchspace_active],
pdcch_vars2->n_RB_BWP[nb_searchspace_active],
&crc_scrambled,
&format_found,
crc_scrambled_values);
fapi_nr_dci_indication_t dci_ind;
nr_downlink_indication_t dl_indication;
memset((void*)&dci_ind,0,sizeof(dci_ind));
memset((void*)&dl_indication,0,sizeof(dl_indication));
dci_cnt = nr_dci_decoding_procedure(ue,
proc->frame_rx,
nr_tti_rx,
&dci_ind);
#ifdef NR_PDCCH_SCHED_DEBUG
printf("<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Ending function nr_dci_decoding_procedure() -> dci_cnt=%u\n",dci_cnt);
LOG_I(PHY,"<-NR_PDCCH_PHY_PROCEDURES_LTE_UE (nr_ue_pdcch_procedures)-> Ending function nr_dci_decoding_procedure() -> dci_cnt=%u\n",dci_cnt);
#endif
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DCI_DECODING, VCD_FUNCTION_OUT);
//LOG_D(PHY,"[UE %d][PUSCH] Frame %d nr_tti_rx %d PHICH RX\n",ue->Mod_id,frame_rx,nr_tti_rx);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_DCI_DECODING, VCD_FUNCTION_OUT);
//LOG_D(PHY,"[UE %d][PUSCH] Frame %d nr_tti_rx %d PHICH RX\n",ue->Mod_id,frame_rx,nr_tti_rx);
for (int i=0; i<dci_cnt; i++) {
LOG_D(PHY,"[UE %d] AbsSubFrame %d.%d, Mode %s: DCI found %i --> rnti %x : format %d\n",
ue->Mod_id,frame_rx%1024,nr_tti_rx,mode_string[ue->UE_mode[0]],
i,
dci_ind.dci_list[i].rnti,
dci_ind.dci_list[i].dci_format);
}
ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][gNB_id]->dci_received += dci_cnt;
/*
uint8_t *nCCE_current = &ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->nCCE[nr_tti_rx];
uint8_t *nCCE_dest = &ue->pdcch_vars[next1_thread_id][eNB_id]->nCCE[nr_tti_rx];
uint8_t *nCCE_dest1 = &ue->pdcch_vars[next2_thread_id][eNB_id]->nCCE[nr_tti_rx];
memcpy(nCCE_dest, nCCE_current, sizeof(uint8_t));
memcpy(nCCE_dest1, nCCE_current, sizeof(uint8_t));
LOG_D(PHY,"current_thread %d next1_thread %d next2_thread %d \n", ue->current_thread_id[nr_tti_rx], next1_thread_id, next2_thread_id);
*/
LOG_D(PHY,"[UE %d] AbsSubFrame %d.%d, Mode %s: DCI found %i --> rnti %x / crnti %x : format %d\n",
ue->Mod_id,frame_rx%1024,nr_tti_rx,mode_string[ue->UE_mode[eNB_id]],
dci_cnt,
dci_alloc_rx[0].rnti,
ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->crnti,
dci_alloc_rx[0].format );
ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->dci_received += dci_cnt;
#ifdef EMOS
//emos_dump_UE.dci_cnt[nr_tti_rx] = dci_cnt;
#endif
dci_ind.number_of_dcis = dci_cnt;
/*
for (int i=0; i<dci_cnt; i++) {
/*
* This is the NR part
*/
if ((dci_alloc_rx[i].format == format0_0)){
}
if (dci_alloc_rx[i].format == format1_0) {
if ((dci_alloc_rx[i].rnti != crc_scrambled_values[_P_RNTI_]) &&
(dci_alloc_rx[i].rnti != crc_scrambled_values[_SI_RNTI_]) &&
(dci_alloc_rx[i].rnti != crc_scrambled_values[_RA_RNTI_]))
ue->dlsch_received[eNB_id]++;
if (dci_alloc_rx[i].rnti == crc_scrambled_values[_SI_RNTI_])
ue->dlsch_SI_received[eNB_id]++;
if (dci_alloc_rx[i].rnti == crc_scrambled_values[_P_RNTI_])
ue->dlsch_p_received[eNB_id]++;
if (dci_alloc_rx[i].rnti == crc_scrambled_values[_RA_RNTI_])
ue->dlsch_ra_received[eNB_id]++;
}
if ((dci_alloc_rx[i].format == format2_0)){
}
if ((dci_alloc_rx[i].format == format2_1)){
}
if ((dci_alloc_rx[i].format == format2_2)){
}
if ((dci_alloc_rx[i].format == format2_3)){
}
if ((dci_alloc_rx[i].format == format0_1)){ // This format not implemented at a first time. FIXME
}
if ((dci_alloc_rx[i].format == format1_1)){ // This format not implemented at a first time. FIXME
}
uint8_t status=0;
LOG_D(PHY,"<-NR_PDCCH_PHY_PROCEDURES_UE (nr_ue_pdcch_procedures)-> dci_format=%d, rnti=%d, dci_length=%d, dci_pdu[0]=0x%lx, dci_pdu[1]=0x%lx\n",dci_alloc_rx[i].format,dci_alloc_rx[i].rnti,dci_alloc_rx[i].dci_length,dci_alloc_rx[i].dci_pdu[0],dci_alloc_rx[i].dci_pdu[1]);
memset(&dci_ind.dci_list[i].dci,0,sizeof(fapi_nr_dci_pdu_rel15_t));
dci_ind.dci_list[i].rnti = dci_alloc_rx[i].rnti;
@@ -3117,36 +3052,15 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,
LOG_D(PHY,"<-NR_PDCCH_PHY_PROCEDURES_UE (nr_ue_pdcch_procedures)-> Ending function nr_extract_dci_info()\n");
/*
nr_generate_ue_ul_dlsch_params_from_dci(ue,
eNB_id,
frame_rx,
nr_tti_rx,
dci_alloc_rx[i].dci_pdu,
dci_alloc_rx[i].rnti,
dci_alloc_rx[i].dci_length,
dci_alloc_rx[i].format,
ue->pdcch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id],
ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id],
ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id],
ue->ulsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0],
&ue->frame_parms,
ue->pdsch_config_dedicated,
ue->transmission_mode[eNB_id]<7?0:ue->transmission_mode[eNB_id],
dci_fields_sizes_cnt[i],
pdcch_vars2->n_RB_BWP[nb_searchspace_active],
pdcch_vars2->n_RB_BWP[nb_searchspace_active],
crc_scrambled_values,
&nr_dci_info_extracted);
*/
} // end for loop dci_cnt
*/
// fill dl_indication message
dl_indication.module_id = ue->Mod_id;
dl_indication.cc_id = ue->CC_id;
dl_indication.gNB_index = eNB_id;
dl_indication.gNB_index = gNB_id;
dl_indication.frame = frame_rx;
dl_indication.slot = nr_tti_rx;
dl_indication.rx_ind = NULL; //no data, only dci for now
@@ -3158,10 +3072,11 @@ int nr_ue_pdcch_procedures(uint8_t eNB_id,
#if UE_TIMING_TRACE
stop_meas(&ue->dlsch_rx_pdcch_stats);
#endif
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_PDCCH_PROCEDURES, VCD_FUNCTION_OUT);
} // end for loop nb_searchspace_active
return(dci_cnt);
}
#endif // NR_PDCCH_SCHED
@@ -3355,25 +3270,31 @@ void nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB
if (dlsch0 && (!dlsch1)) {
int harq_pid = dlsch0->current_harq_pid;
uint16_t BWPStart = dlsch0->harq_processes[harq_pid]->BWPStart;
uint16_t BWPSize = dlsch0->harq_processes[harq_pid]->BWPSize;
uint16_t pdsch_start_rb = dlsch0->harq_processes[harq_pid]->start_rb;
uint16_t pdsch_nb_rb = dlsch0->harq_processes[harq_pid]->nb_rb;
uint16_t s0 = dlsch0->harq_processes[harq_pid]->start_symbol;
uint16_t s1 = dlsch0->harq_processes[harq_pid]->nb_symbols;
LOG_D(PHY,"[UE %d] PDSCH type %d active in nr_tti_rx %d, harq_pid %d, rb_start %d, nb_rb %d, symbol_start %d, nb_symbols %d\n",ue->Mod_id,pdsch,nr_tti_rx,harq_pid,pdsch_start_rb,pdsch_nb_rb,s0,s1);
LOG_D(PHY,"[UE %d] PDSCH type %d active in nr_tti_rx %d, harq_pid %d, rb_start %d, nb_rb %d, symbol_start %d, nb_symbols %d, DMRS mask %x\n",ue->Mod_id,pdsch,nr_tti_rx,harq_pid,pdsch_start_rb,pdsch_nb_rb,s0,s1,dlsch0->harq_processes[harq_pid]->dlDmrsSymbPos);
for (m = s0; m < (s1 + s0); m++) {
if (m==s0)
// do channel estimation for first DMRS only
for (m = s0; m < 3; m++) {
if (((1<<m)&dlsch0->harq_processes[harq_pid]->dlDmrsSymbPos) > 0) {
nr_pdsch_channel_estimation(ue,
0 /*eNB_id*/,
nr_tti_rx,
0 /*p*/,
m,
ue->frame_parms.first_carrier_offset+pdsch_start_rb*12,
ue->frame_parms.first_carrier_offset+(BWPStart + pdsch_start_rb)*12,
pdsch_nb_rb);
LOG_D(PHY,"Channel Estimation in symbol %d\n",m);
break;
}
}
for (m = s0; m < (s1 + s0); m++) {
dual_stream_UE = 0;
eNB_id_i = eNB_id+1;
i_mod = 0;
@@ -3773,7 +3694,7 @@ void nr_ue_dlsch_procedures(PHY_VARS_NR_UE *ue,
LOG_D(PHY," ------ end ldpc decoder for AbsSubframe %d.%d ------ \n", frame_rx, nr_tti_rx);
LOG_I(PHY, "harq_pid: %d, TBS expected dlsch0: %d, TBS expected dlsch1: %d \n",harq_pid, dlsch0->harq_processes[harq_pid]->TBS, dlsch1->harq_processes[harq_pid]->TBS);
LOG_D(PHY, "harq_pid: %d, TBS expected dlsch0: %d, TBS expected dlsch1: %d \n",harq_pid, dlsch0->harq_processes[harq_pid]->TBS, dlsch1->harq_processes[harq_pid]->TBS);
if(ret<dlsch0->max_ldpc_iterations+1){
// fill dl_indication message
@@ -4140,7 +4061,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
NR_DL_UE_HARQ_t *dlsch0_harq = dlsch[0]->harq_processes[harq_pid];
uint16_t nb_symb_sch = dlsch0_harq->nb_symbols;
uint16_t start_symb_sch = dlsch0_harq->start_symbol;
uint8_t nb_symb_pdcch = pdcch_vars->coreset[0].duration;
uint8_t nb_symb_pdcch = pdcch_vars->nb_search_space > 0 ? pdcch_vars->pdcch_config[0].coreset.duration : 0;
uint8_t ssb_periodicity = 10;// ue->ssb_periodicity; // initialized to 5ms in nr_init_ue for scenarios where UE is not configured (otherwise acquired by cell configuration from gNB or LTE)
uint8_t dci_cnt = 0;
fapi_nr_pbch_config_t *pbch_config = &ue->nrUE_config.pbch_config;
@@ -4152,20 +4073,11 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
uint8_t next2_thread_id = next1_thread_id== (RX_NB_TH-1) ? 0:(next1_thread_id+1);
*/
uint8_t coreset_start=0, coreset_start_set=0;
uint16_t coreset_count = 0;
uint64_t coreset_freq_dom = pdcch_vars->coreset[0].frequencyDomainResources;
for (int i = 0; i < 45; i++) {
if (((coreset_freq_dom & 0x1FFFFFFFFFFF) >> (44-i)) & 0x1) {
if (!coreset_start_set) {
coreset_start = i;
coreset_start_set = 1;
}
coreset_count++;
}
}
uint16_t coreset_nb_rb = 6 * coreset_count;
uint16_t coreset_start_rb = 6 * coreset_start;
int coreset_nb_rb=0;
int coreset_start_rb=0;
if (pdcch_vars->nb_search_space > 0)
get_coreset_rballoc(pdcch_vars->pdcch_config[0].coreset.frequency_domain_resource,&coreset_nb_rb,&coreset_start_rb);
slot_pbch = is_pbch_in_slot(pbch_config, frame_rx, nr_tti_rx, ssb_periodicity, ue->frame_parms.slots_per_frame);
@@ -4220,12 +4132,16 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
0,
0);
nr_pdcch_channel_estimation(ue,
0,
nr_tti_rx,
l,
ue->frame_parms.first_carrier_offset+coreset_start_rb*12,
coreset_nb_rb);
// note: this only works if RBs for PDCCH are contigous!
LOG_D(PHY,"pdcch_channel_estimation: first_carrier_offset %d, BWPStart %d, coreset_start_rb %d\n",
ue->frame_parms.first_carrier_offset,pdcch_vars->pdcch_config[0].BWPStart,coreset_start_rb);
if (coreset_nb_rb > 0)
nr_pdcch_channel_estimation(ue,
0,
nr_tti_rx,
l,
ue->frame_parms.first_carrier_offset+(pdcch_vars->pdcch_config[0].BWPStart + coreset_start_rb)*12,
coreset_nb_rb);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_UE_SLOT_FEP, VCD_FUNCTION_OUT);
#if UE_TIMING_TRACE
@@ -4241,7 +4157,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
if (dci_cnt > 0) {
LOG_I(PHY,"[UE %d] Frame %d, nr_tti_rx %d: found %d DCIs\n",ue->Mod_id,frame_rx,nr_tti_rx,dci_cnt);
LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: found %d DCIs\n",ue->Mod_id,frame_rx,nr_tti_rx,dci_cnt);
} else {
LOG_D(PHY,"[UE %d] Frame %d, nr_tti_rx %d: No DCIs found\n",ue->Mod_id,frame_rx,nr_tti_rx);
@@ -4253,7 +4169,11 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
LOG_D(PHY," ------ --> PDSCH ChannelComp/LLR Frame.slot %d.%d ------ \n", frame_rx%1024, nr_tti_rx);
//to update from pdsch config
start_symb_sch = dlsch0_harq->start_symbol;
nr_gold_pdsch(ue,start_symb_sch,0, 1);
int symb_dmrs=-1;
for (int i=0;i<4;i++) if (((1<<i)&dlsch0_harq->dlDmrsSymbPos) > 0) {symb_dmrs=i;break;}
AssertFatal(symb_dmrs>=0,"no dmrs in 0..3\n");
LOG_D(PHY,"Initializing dmrs for symb %d DMRS mask %x\n",symb_dmrs,dlsch0_harq->dlDmrsSymbPos);
nr_gold_pdsch(ue,symb_dmrs,0, 1);
nb_symb_sch = dlsch0_harq->nb_symbols;
@@ -4342,7 +4262,7 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
// do procedures for C-RNTI
if (ue->dlsch[ue->current_thread_id[nr_tti_rx]][eNB_id][0]->active == 1) {
LOG_I(PHY, "DLSCH data reception at nr_tti_rx: %d \n \n", nr_tti_rx);
LOG_D(PHY, "DLSCH data reception at nr_tti_rx: %d \n \n", nr_tti_rx);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_PDSCH_PROC, VCD_FUNCTION_IN);
#if UE_TIMING_TRACE
openair1/SCHED_NR_UE/pucch_uci_ue_nr.c
+7 -7
View File
@@ -211,11 +211,11 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
/* sr_payload = 1 means that this is a positive SR, sr_payload = 0 means that it is a negative SR */
sr_payload = nr_ue_get_SR(Mod_id,
CC_id,
frame_tx,
gNB_id,
ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti,
nr_tti_tx); // nr_tti_rx used for meas gap
CC_id,
frame_tx,
gNB_id,
0,//ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti,
nr_tti_tx); // nr_tti_rx used for meas gap
}
else {
sr_payload = 1;
@@ -590,7 +590,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
case pucch_format2_nr:
{
nr_generate_pucch2(ue,
ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti,
0,//ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti,
ue->common_vars.txdataF,
&ue->frame_parms,
&ue->pucch_config_dedicated[gNB_id],
@@ -608,7 +608,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
case pucch_format4_nr:
{
nr_generate_pucch3_4(ue,
ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti,
0,//ue->pdcch_vars[ue->current_thread_id[proc->nr_tti_rx]][gNB_id]->crnti,
ue->common_vars.txdataF,
&ue->frame_parms,
format,
openair1/SIMULATION/NR_PHY/dlsim.c
+270 -263
View File
@@ -64,6 +64,10 @@
//#include "openair1/SIMULATION/NR_PHY/nr_dummy_functions.c"
#include "NR_RRCReconfiguration.h"
#define inMicroS(a) (((double)(a))/(cpu_freq_GHz*1000.0))
#include "SIMULATION/LTE_PHY/common_sim.h"
PHY_VARS_gNB *gNB;
PHY_VARS_NR_UE *UE;
@@ -204,7 +208,6 @@ int main(int argc, char **argv)
uint16_t ssb_periodicity = 10;
//unsigned char frame_type = 0;
unsigned char pbch_phase = 0;
int frame=0,slot=1;
int frame_length_complex_samples;
@@ -234,8 +237,10 @@ int main(int argc, char **argv)
randominit(0);
int mcsIndex_set=0,rbStart_set=0,rbSize_set=0,StartSymbolIndex_set=0,NrOfSymbols_set=0;
int print_perf = 0;
while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:s:S:t:x:y:z:M:N:F:GR:dP:IL:Eo:a:b:c:j:e:")) != -1) {
while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:s:S:t:x:y:z:M:N:F:GR:dPIL:Eo:a:b:c:j:e:")) != -1) {
switch (c) {
/*case 'f':
write_output_file=1;
@@ -384,11 +389,8 @@ int main(int argc, char **argv)
break;
case 'P':
pbch_phase = atoi(optarg);
if (pbch_phase>3)
printf("Illegal PBCH phase (0-3) got %d\n",pbch_phase);
print_perf=1;
opp_enabled=1;
break;
case 'I':
@@ -411,22 +413,27 @@ int main(int argc, char **argv)
case 'a':
dlsch_config.rbStart = atoi(optarg);
rbStart_set=1;
break;
case 'b':
dlsch_config.rbSize = atoi(optarg);
rbSize_set=1;
break;
case 'c':
dlsch_config.StartSymbolIndex = atoi(optarg);
StartSymbolIndex_set=1;
break;
case 'j':
dlsch_config.NrOfSymbols = atoi(optarg);
NrOfSymbols_set=1;
break;
case 'e':
dlsch_config.mcsIndex[0] = atoi(optarg);
mcsIndex_set=1;
break;
@@ -442,11 +449,10 @@ int main(int argc, char **argv)
printf("-S Ending SNR, runs from SNR0 to SNR1\n");
printf("-t Delay spread for multipath channel\n");
printf("-g [A,B,C,D,E,F,G] Use 3GPP SCM (A,B,C,D) or 36-101 (E-EPA,F-EVA,G-ETU) models (ignores delay spread and Ricean factor)\n");
printf("-x Transmission mode (1,2,6 for the moment)\n");
printf("-y Number of TX antennas used in eNB\n");
printf("-y Number of TX antennas used in gNB\n");
printf("-z Number of RX antennas used in UE\n");
//printf("-i Relative strength of first intefering eNB (in dB) - cell_id mod 3 = 1\n");
//printf("-j Relative strength of second intefering eNB (in dB) - cell_id mod 3 = 2\n");
//printf("-i Relative strength of first intefering gNB (in dB) - cell_id mod 3 = 1\n");
//printf("-j Relative strength of second intefering gNB (in dB) - cell_id mod 3 = 2\n");
printf("-M Multiple SSB positions in burst\n");
printf("-N Nid_cell\n");
printf("-R N_RB_DL\n");
@@ -544,9 +550,9 @@ int main(int argc, char **argv)
// common configuration
rrc_mac_config_req_gNB(0,0,scc,0,0,NULL);
// UE dedicated configuration
rrc_mac_config_req_gNB(0,0,NULL,1,0x1234,secondaryCellGroup);
rrc_mac_config_req_gNB(0,0,NULL,1,secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity,secondaryCellGroup);
phy_init_nr_gNB(gNB,0,0);
N_RB_DL = gNB->frame_parms.N_RB_DL;
// stub to configure frame_parms
// nr_phy_config_request_sim(gNB,N_RB_DL,N_RB_DL,mu,Nid_cell,SSB_positions);
// call MAC to configure common parameters
@@ -649,8 +655,6 @@ int main(int argc, char **argv)
nr_l2_init_ue();
UE_mac = get_mac_inst(0);
UE->pdcch_vars[0][0]->crnti = 0x1234;
UE->if_inst = nr_ue_if_module_init(0);
UE->if_inst->scheduled_response = nr_ue_scheduled_response;
UE->if_inst->phy_config_request = nr_ue_phy_config_request;
@@ -666,87 +670,19 @@ int main(int argc, char **argv)
unsigned int errors_bit = 0;
uint32_t errors_scrambling = 0;
test_input_bit = (unsigned char *) malloc16(sizeof(unsigned char) * 16 * 68 * 384);
estimated_output_bit = (unsigned char *) malloc16(sizeof(unsigned char) * 16 * 68 * 384);
// generate signal
if (input_fd==NULL) {
gNB->pbch_configured = 1;
gNB->ssb_pdu.ssb_pdu_rel15.bchPayload=0x001234;
if (css_flag == 0) nr_schedule_uss_dlsch_phytest(0,frame,slot,&dlsch_config);
else nr_schedule_css_dlsch_phytest(0,frame,slot);
Sched_INFO.module_id = 0;
Sched_INFO.CC_id = 0;
Sched_INFO.frame = frame;
Sched_INFO.slot = slot;
Sched_INFO.DL_req = &gNB_mac->DL_req[0];
Sched_INFO.UL_tti_req = &gNB_mac->UL_tti_req[0];
Sched_INFO.UL_dci_req = NULL;
Sched_INFO.TX_req = &gNB_mac->TX_req[0];
nr_schedule_response(&Sched_INFO);
phy_procedures_gNB_TX(gNB,frame,slot,0);
//nr_common_signal_procedures (gNB,frame,subframe);
int txdataF_offset = (slot%2) * frame_parms->samples_per_slot_wCP;
LOG_M("txsigF0.m","txsF0", gNB->common_vars.txdataF[0],frame_length_complex_samples_no_prefix,1,1);
if (gNB->frame_parms.nb_antennas_tx>1)
LOG_M("txsigF1.m","txsF1", gNB->common_vars.txdataF[1],frame_length_complex_samples_no_prefix,1,1);
int tx_offset = slot*frame_parms->samples_per_slot;
printf("samples_per_slot_wCP = %d\n", frame_parms->samples_per_slot_wCP);
//TODO: loop over slots
for (aa=0; aa<gNB->frame_parms.nb_antennas_tx; aa++) {
if (cyclic_prefix_type == 1) {
PHY_ofdm_mod(&gNB->common_vars.txdataF[aa][txdataF_offset],
&txdata[aa][tx_offset],
frame_parms->ofdm_symbol_size,
12,
frame_parms->nb_prefix_samples,
CYCLIC_PREFIX);
} else {
nr_normal_prefix_mod(&gNB->common_vars.txdataF[aa][txdataF_offset],
&txdata[aa][tx_offset],
14,
frame_parms);
}
}
} else {
printf("Reading %d samples from file to antenna buffer %d\n",frame_length_complex_samples,0);
if (fread(txdata[0],
sizeof(int32_t),
frame_length_complex_samples,
input_fd) != frame_length_complex_samples) {
printf("error reading from file\n");
//exit(-1);
}
}
LOG_M("txsig0.m","txs0", txdata[0],frame_length_complex_samples,1,1);
if (gNB->frame_parms.nb_antennas_tx>1)
LOG_M("txsig1.m","txs1", txdata[1],frame_length_complex_samples,1,1);
if (output_fd)
fwrite(txdata[0],sizeof(int32_t),frame_length_complex_samples,output_fd);
int txlev = signal_energy(&txdata[0][5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0],
frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples);
// printf("txlev %d (%f)\n",txlev,10*log10(txlev));
for (i=0; i<frame_length_complex_samples; i++) {
for (aa=0; aa<frame_parms->nb_antennas_tx; aa++) {
r_re[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)]);
r_im[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)+1]);
}
}
AssertFatal(input_fd==NULL,"Not ready for input signal file\n");
gNB->pbch_configured = 1;
gNB->ssb_pdu.ssb_pdu_rel15.bchPayload=0x001234;
if (mcsIndex_set==0) dlsch_config.mcsIndex[0]=9;
if (rbSize_set==0) dlsch_config.rbSize=N_RB_DL;
if (rbStart_set==0) dlsch_config.rbStart=0;
//Configure UE
@@ -755,207 +691,221 @@ int main(int argc, char **argv)
rrc.carrier.MIB = (uint8_t*) malloc(4);
rrc.carrier.sizeof_MIB = do_MIB_NR(&rrc,0);
nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,scc,NULL,NULL,NULL);
nr_rrc_mac_config_req_ue(0,0,0,rrc.carrier.mib.message.choice.mib,scc,secondaryCellGroup->spCellConfig);
// Initial bandwidth part configuration -- full carrier bandwidth
UE_mac->initial_bwp_dl.bwp_id = 0;
UE_mac->initial_bwp_dl.location = 0;
UE_mac->initial_bwp_dl.scs = UE->frame_parms.subcarrier_spacing;
UE_mac->initial_bwp_dl.N_RB = UE->frame_parms.N_RB_DL;
UE_mac->initial_bwp_dl.cyclic_prefix = UE->frame_parms.Ncp;
fapi_nr_dl_config_request_t *dl_config = &UE_mac->dl_config_request;
// Type0 PDCCH search space
dl_config->number_pdus = 1;
dl_config->dl_config_list[0].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.rnti = 0x1234;
uint64_t mask = 0x0;
uint16_t num_rbs;
uint16_t rb_offset;
get_coreset_rballoc(gNB->pdcch_pdu->pdcch_pdu_rel15.FreqDomainResource,&num_rbs,&rb_offset);
uint16_t cell_id=0;
uint16_t num_symbols=2;
for(i=0; i<(num_rbs/6); ++i){ // 38.331 Each bit corresponds a group of 6 RBs
mask = mask >> 1;
mask = mask | 0x100000000000;
}
uint16_t UE_rb_offset_count = rb_offset/6;
mask = mask >> UE_rb_offset_count;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.frequency_domain_resource = mask;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.rb_offset = rb_offset; // additional parameter other than coreset
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.duration = num_symbols;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_mapping_type =CCE_REG_MAPPING_TYPE_NON_INTERLEAVED;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_reg_bundle_size = 0; // L 38.211 7.3.2.2
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_interleaver_size = 0; // R 38.211 7.3.2.2
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_shift_index = cell_id;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.precoder_granularity = PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.pdcch_dmrs_scrambling_id = cell_id;
uint32_t number_of_search_space_per_slot=1;
uint32_t first_symbol_index=0;
uint32_t search_space_duration=0; // element of search space
uint32_t coreset_duration; // element of coreset
coreset_duration = num_symbols * number_of_search_space_per_slot;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[0] = table_38213_10_1_1_c2[0];
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[1] = table_38213_10_1_1_c2[1];
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[2] = table_38213_10_1_1_c2[2]; // CCE aggregation level = 4
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[3] = table_38213_10_1_1_c2[3]; // CCE aggregation level = 8
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[4] = table_38213_10_1_1_c2[4]; // CCE aggregation level = 16
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.duration = search_space_duration;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.monitoring_symbols_within_slot = (0x3fff << first_symbol_index) & (0x3fff >> (14-coreset_duration-first_symbol_index)) & 0x3fff;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.N_RB_BWP = N_RB_DL;
UE_mac->scheduled_response.dl_config = dl_config;
UE_mac->scheduled_response.ul_config = NULL;
UE_mac->scheduled_response.tx_request = NULL;
UE_mac->scheduled_response.module_id = 0;
UE_mac->scheduled_response.CC_id = 0;
UE_mac->scheduled_response.frame = frame;
UE_mac->scheduled_response.slot = slot;
nr_dcireq_t dcireq;
nr_scheduled_response_t scheduled_response;
memset((void*)&dcireq,0,sizeof(dcireq));
memset((void*)&scheduled_response,0,sizeof(scheduled_response));
dcireq.module_id = 0;
dcireq.gNB_index = 0;
dcireq.cc_id = 0;
scheduled_response.dl_config = &dcireq.dl_config_req;
scheduled_response.ul_config = &dcireq.ul_config_req;
scheduled_response.tx_request = NULL;
scheduled_response.module_id = 0;
scheduled_response.CC_id = 0;
scheduled_response.frame = frame;
scheduled_response.slot = slot;
nr_ue_phy_config_request(&UE_mac->phy_config);
for (SNR = snr0; SNR < snr1; SNR += .2) {
varArray_t *table_tx=initVarArray(1000,sizeof(double));
varArray_t *table_tx_ifft=initVarArray(1000,sizeof(double));
reset_meas(&gNB->phy_proc_tx); // total gNB tx
reset_meas(&gNB->dlsch_scrambling_stats);
reset_meas(&gNB->dlsch_interleaving_stats);
reset_meas(&gNB->dlsch_rate_matching_stats);
reset_meas(&gNB->dlsch_segmentation_stats);
reset_meas(&gNB->dlsch_modulation_stats);
reset_meas(&gNB->dlsch_encoding_stats);
reset_meas(&gNB->tinput);
reset_meas(&gNB->tprep);
reset_meas(&gNB->tparity);
reset_meas(&gNB->toutput);
n_errors = 0;
//n_errors2 = 0;
//n_alamouti = 0;
errors_scrambling=0;
n_false_positive = 0;
for (trial = 0; trial < n_trials; trial++) {
errors_bit = 0;
//multipath channel
//multipath_channel(gNB2UE,s_re,s_im,r_re,r_im,frame_length_complex_samples,0);
memset(RC.nrmac[0]->cce_list[1][0],0,MAX_NUM_CCE*sizeof(int));
clear_nr_nfapi_information(RC.nrmac[0], 0, frame, slot);
if (css_flag == 0) nr_schedule_uss_dlsch_phytest(0,frame,slot,&dlsch_config);
else nr_schedule_css_dlsch_phytest(0,frame,slot);
Sched_INFO.module_id = 0;
Sched_INFO.CC_id = 0;
Sched_INFO.frame = frame;
Sched_INFO.slot = slot;
Sched_INFO.DL_req = &gNB_mac->DL_req[0];
Sched_INFO.UL_tti_req = &gNB_mac->UL_tti_req[0];
Sched_INFO.UL_dci_req = NULL;
Sched_INFO.TX_req = &gNB_mac->TX_req[0];
nr_schedule_response(&Sched_INFO);
phy_procedures_gNB_TX(gNB,frame,slot,0);
//nr_common_signal_procedures (gNB,frame,subframe);
int txdataF_offset = (slot%2) * frame_parms->samples_per_slot_wCP;
if (n_trials==1) {
LOG_M("txsigF0.m","txsF0", gNB->common_vars.txdataF[0],frame_length_complex_samples_no_prefix,1,1);
if (gNB->frame_parms.nb_antennas_tx>1)
LOG_M("txsigF1.m","txsF1", gNB->common_vars.txdataF[1],frame_length_complex_samples_no_prefix,1,1);
}
int tx_offset = slot*frame_parms->samples_per_slot;
if (n_trials==1) printf("samples_per_slot_wCP = %d\n", frame_parms->samples_per_slot_wCP);
//TODO: loop over slots
for (aa=0; aa<gNB->frame_parms.nb_antennas_tx; aa++) {
if (cyclic_prefix_type == 1) {
PHY_ofdm_mod(&gNB->common_vars.txdataF[aa][txdataF_offset],
&txdata[aa][tx_offset],
frame_parms->ofdm_symbol_size,
12,
frame_parms->nb_prefix_samples,
CYCLIC_PREFIX);
} else {
nr_normal_prefix_mod(&gNB->common_vars.txdataF[aa][txdataF_offset],
&txdata[aa][tx_offset],
14,
frame_parms);
}
}
if (n_trials==1) {
LOG_M("txsig0.m","txs0", txdata[0],frame_length_complex_samples,1,1);
if (gNB->frame_parms.nb_antennas_tx>1)
LOG_M("txsig1.m","txs1", txdata[1],frame_length_complex_samples,1,1);
}
if (output_fd)
fwrite(txdata[0],sizeof(int32_t),frame_length_complex_samples,output_fd);
int txlev = signal_energy(&txdata[0][(slot*frame_parms->samples_per_slot)+5*frame_parms->ofdm_symbol_size + 4*frame_parms->nb_prefix_samples + frame_parms->nb_prefix_samples0],
frame_parms->ofdm_symbol_size + frame_parms->nb_prefix_samples);
// if (n_trials==1) printf("txlev %d (%f)\n",txlev,10*log10((double)txlev));
for (i=0; i<frame_length_complex_samples; i++) {
for (aa=0; aa<frame_parms->nb_antennas_tx; aa++) {
r_re[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)]);
r_im[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)+1]);
}
}
NR_gNB_DLSCH_t *gNB_dlsch = gNB->dlsch[0][0];
nfapi_nr_dl_tti_pdsch_pdu_rel15_t rel15 = gNB_dlsch->harq_processes[0]->pdsch_pdu.pdsch_pdu_rel15;
//AWGN
sigma2_dB = 10 * log10((double)txlev) - SNR;
sigma2_dB = 10 * log10((double)txlev * (N_RB_DL/rel15.rbSize)) - SNR;
sigma2 = pow(10, sigma2_dB/10);
// printf("sigma2 %f (%f dB)\n",sigma2,sigma2_dB);
if (n_trials==1) printf("sigma2 %f (%f dB), txlev %f (factor %f)\n",sigma2,sigma2_dB,10*log10((double)txlev* (N_RB_DL/rel15.rbSize)),(double)N_RB_DL/rel15.rbSize);
for (i=0; i<frame_length_complex_samples; i++) {
for (aa=0; aa<frame_parms->nb_antennas_rx; aa++) {
((short*) UE->common_vars.rxdata[aa])[2*i] = (short) ((r_re[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0)));
((short*) UE->common_vars.rxdata[aa])[2*i+1] = (short) ((r_im[aa][i] + sqrt(sigma2/2)*gaussdouble(0.0,1.0)));
}
}
if (n_trials == 1) {
LOG_M("rxsig0.m","rxs0", UE->common_vars.rxdata[0], frame_length_complex_samples, 1, 1);
if (UE->frame_parms.nb_antennas_rx>1)
LOG_M("rxsig1.m","rxs1", UE->common_vars.rxdata[1], frame_length_complex_samples, 1, 1);
}
if (UE->is_synchronized == 0) {
UE_nr_rxtx_proc_t proc={0};
ret = nr_initial_sync(&proc, UE, normal_txrx,1);
printf("nr_initial_sync1 returns %d\n",ret);
if (ret<0) n_errors++;
}
else {
UE->rx_offset=0;
UE_proc.frame_rx = frame;
UE_proc.nr_tti_rx= slot;
UE_proc.subframe_rx = slot;
nr_ue_scheduled_response(&UE_mac->scheduled_response);
printf("Running phy procedures UE RX %d.%d\n",frame,slot);
phy_procedures_nrUE_RX(UE,
&UE_proc,
0,
do_pdcch_flag,
normal_txrx);
if (n_trials==1) {
LOG_M("rxsigF0.m","rxsF0", UE->common_vars.common_vars_rx_data_per_thread[0].rxdataF[0],slot_length_complex_samples_no_prefix,1,1);
if (UE->frame_parms.nb_antennas_rx>1)
LOG_M("rxsigF1.m","rxsF1", UE->common_vars.common_vars_rx_data_per_thread[0].rxdataF[1],slot_length_complex_samples_no_prefix,1,1);
}
if (UE->dlsch[UE->current_thread_id[slot]][0][0]->last_iteration_cnt >=
UE->dlsch[UE->current_thread_id[slot]][0][0]->max_ldpc_iterations+1)
n_errors++;
//----------------------------------------------------------
//---------------------- count errors ----------------------
//----------------------------------------------------------
NR_gNB_DLSCH_t *gNB_dlsch = gNB->dlsch[0][0];
NR_UE_DLSCH_t *dlsch0 = UE->dlsch[UE->current_thread_id[UE_proc.nr_tti_rx]][0][0];
int harq_pid = dlsch0->current_harq_pid;
NR_DL_UE_HARQ_t *UE_harq_process = dlsch0->harq_processes[harq_pid];
NR_UE_PDSCH **pdsch_vars = UE->pdsch_vars[UE->current_thread_id[UE_proc.nr_tti_rx]];
int16_t *UE_llr = pdsch_vars[0]->llr[0];
nfapi_nr_dl_tti_pdsch_pdu_rel15_t rel15 = gNB_dlsch->harq_processes[harq_pid]->pdsch_pdu.pdsch_pdu_rel15;
uint32_t TBS = rel15.TBSize[0];
uint16_t length_dmrs = 1;
uint16_t nb_rb = rel15.rbSize;
uint8_t nb_re_dmrs = rel15.dmrsConfigType == 1 ? 6 : 4;
uint8_t mod_order = rel15.qamModOrder[0];
uint8_t nb_symb_sch = rel15.NrOfSymbols;
available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, rel15.nrOfLayers);
UE->rx_offset=0;
UE_proc.frame_rx = frame;
UE_proc.nr_tti_rx= slot;
UE_proc.subframe_rx = slot;
dcireq.frame = frame;
dcireq.slot = slot;
nr_ue_dcireq(&dcireq); //to be replaced with function pointer later
nr_ue_scheduled_response(&scheduled_response);
phy_procedures_nrUE_RX(UE,
&UE_proc,
0,
do_pdcch_flag,
normal_txrx);
if (UE->dlsch[UE->current_thread_id[slot]][0][0]->last_iteration_cnt >=
UE->dlsch[UE->current_thread_id[slot]][0][0]->max_ldpc_iterations+1)
n_errors++;
//----------------------------------------------------------
//---------------------- count errors ----------------------
//----------------------------------------------------------
NR_UE_DLSCH_t *dlsch0 = UE->dlsch[UE->current_thread_id[UE_proc.nr_tti_rx]][0][0];
int harq_pid = dlsch0->current_harq_pid;
NR_DL_UE_HARQ_t *UE_harq_process = dlsch0->harq_processes[harq_pid];
NR_UE_PDSCH **pdsch_vars = UE->pdsch_vars[UE->current_thread_id[UE_proc.nr_tti_rx]];
int16_t *UE_llr = pdsch_vars[0]->llr[0];
uint32_t TBS = rel15.TBSize[0];
uint16_t length_dmrs = 1;
uint16_t nb_rb = rel15.rbSize;
uint8_t nb_re_dmrs = rel15.dmrsConfigType == NFAPI_NR_DMRS_TYPE1 ? 6 : 4;
uint8_t mod_order = rel15.qamModOrder[0];
uint8_t nb_symb_sch = rel15.NrOfSymbols;
available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, rel15.nrOfLayers);
for (i = 0; i < available_bits; i++) {
printf("\n");
printf("available_bits = %u\n", available_bits);
for (i = 0; i < available_bits; i++) {
if(((gNB_dlsch->harq_processes[harq_pid]->f[i] == 0) && (UE_llr[i] <= 0)) ||
((gNB_dlsch->harq_processes[harq_pid]->f[i] == 1) && (UE_llr[i] >= 0)))
{
if(errors_scrambling == 0) {
printf("\n");
printf("First bit in error in unscrambling = %d\n",i);
}
errors_scrambling++;
if(((gNB_dlsch->harq_processes[harq_pid]->f[i] == 0) && (UE_llr[i] <= 0)) ||
((gNB_dlsch->harq_processes[harq_pid]->f[i] == 1) && (UE_llr[i] >= 0)))
{
if(errors_scrambling == 0) {
LOG_D(PHY,"\n");
LOG_D(PHY,"First bit in error in unscrambling = %d\n",i);
}
}
for (i = 0; i < TBS; i++) {
estimated_output_bit[i] = (UE_harq_process->b[i/8] & (1 << (i & 7))) >> (i & 7);
test_input_bit[i] = (gNB_dlsch->harq_processes[harq_pid]->b[i / 8] & (1 << (i & 7))) >> (i & 7); // Further correct for multiple segments
if (estimated_output_bit[i] != test_input_bit[i]) {
if(errors_bit == 0)
printf("First bit in error in decoding = %d\n",i);
errors_bit++;
errors_scrambling++;
}
}
for (i = 0; i < TBS; i++) {
estimated_output_bit[i] = (UE_harq_process->b[i/8] & (1 << (i & 7))) >> (i & 7);
test_input_bit[i] = (gNB_dlsch->harq_processes[harq_pid]->b[i / 8] & (1 << (i & 7))) >> (i & 7); // Further correct for multiple segments
if (estimated_output_bit[i] != test_input_bit[i]) {
if(errors_bit == 0)
LOG_D(PHY,"First bit in error in decoding = %d (errors scrambling %d)\n",i,errors_scrambling);
errors_bit++;
}
////////////////////////////////////////////////////////////
if (errors_scrambling > 0) {
if (n_trials == 1)
printf("errors_scrambling = %d (trial %d)\n", errors_scrambling, trial);
}
if (errors_bit > 0) {
n_false_positive++;
if (n_trials == 1)
printf("errors_bit = %u (trial %d)\n", errors_bit, trial);
}
printf("\n");
} // if (UE->is_synchronized == 0)
}
////////////////////////////////////////////////////////////
if (errors_scrambling > 0) {
if (n_trials == 1)
printf("errors_scrambling = %d (trial %d)\n", errors_scrambling, trial);
}
if (errors_bit > 0) {
n_false_positive++;
if (n_trials == 1)
printf("errors_bit = %u (trial %d)\n", errors_bit, trial);
}
} // noise trials
@@ -964,14 +914,71 @@ int main(int argc, char **argv)
(float) n_errors / (float) n_trials);
printf("*****************************************\n");
printf("\n");
printf("SNR %f : n_errors (negative CRC) = %d/%d\n", SNR, n_errors, n_trials);
printf("SNR %f : n_errors (negative CRC) = %d/%d, Channel BER %e\n", SNR, n_errors, n_trials,(double)errors_scrambling/available_bits/n_trials);
printf("\n");
if (n_trials == 1) {
LOG_M("rxsig0.m","rxs0", UE->common_vars.rxdata[0], frame_length_complex_samples, 1, 1);
if (UE->frame_parms.nb_antennas_rx>1)
LOG_M("rxsig1.m","rxs1", UE->common_vars.rxdata[1], frame_length_complex_samples, 1, 1);
LOG_M("chestF0.m","chF0",UE->pdsch_vars[0][0]->dl_ch_estimates_ext,N_RB_DL*12*14,1,1);
write_output("rxF_comp.m","rxFc",&UE->pdsch_vars[0][0]->rxdataF_comp0[0][0],N_RB_DL*12*14,1,1);
break;
}
if ((float)n_errors/(float)n_trials <= target_error_rate) {
printf("PDSCH test OK\n");
break;
}
if (print_perf==1) {
printf("\ngNB TX function statistics (per %d us slot)\n",1000>>*scc->ssbSubcarrierSpacing);
printDistribution(&gNB->phy_proc_tx,table_tx,"PHY proc tx");
printStatIndent2(&gNB->dlsch_encoding_stats,"DLSCH encoding time");
printStatIndent3(&gNB->dlsch_segmentation_stats,"DLSCH segmentation time");
printStatIndent3(&gNB->tinput,"DLSCH LDPC input processing time");
printStatIndent3(&gNB->tprep,"DLSCH LDPC input preparation time");
printStatIndent3(&gNB->tparity,"DLSCH LDPC parity generation time");
printStatIndent3(&gNB->toutput,"DLSCH LDPC output generation time");
printStatIndent3(&gNB->dlsch_rate_matching_stats,"DLSCH Rate Mataching time");
printStatIndent3(&gNB->dlsch_interleaving_stats, "DLSCH Interleaving time");
printStatIndent2(&gNB->dlsch_modulation_stats,"DLSCH modulation time");
printStatIndent2(&gNB->dlsch_scrambling_stats, "DLSCH scrambling time");
printf("\nUE RX function statistics (per %d us slot)\n",1000>>*scc->ssbSubcarrierSpacing);
/*
printDistribution(&phy_proc_rx_tot, table_rx,"Total PHY proc rx");
printStatIndent(&ue_front_end_tot,"Front end processing");
printStatIndent(&dlsch_llr_tot,"rx_pdsch processing");
printStatIndent2(&pdsch_procedures_tot,"pdsch processing");
printStatIndent2(&dlsch_procedures_tot,"dlsch processing");
printStatIndent2(&UE->crnti_procedures_stats,"C-RNTI processing");
printStatIndent(&UE->ofdm_demod_stats,"ofdm demodulation");
printStatIndent(&UE->dlsch_channel_estimation_stats,"DLSCH channel estimation time");
printStatIndent(&UE->dlsch_freq_offset_estimation_stats,"DLSCH frequency offset estimation time");
printStatIndent(&dlsch_decoding_tot, "DLSCH Decoding time ");
printStatIndent(&UE->dlsch_unscrambling_stats,"DLSCH unscrambling time");
printStatIndent(&UE->dlsch_rate_unmatching_stats,"DLSCH Rate Unmatching");
printf("|__ DLSCH Turbo Decoding(%d bits), avg iterations: %.1f %.2f us (%d cycles, %d trials)\n",
UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Cminus ?
UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Kminus :
UE->dlsch[UE->current_thread_id[subframe]][0][0]->harq_processes[0]->Kplus,
UE->dlsch_tc_intl1_stats.trials/(double)UE->dlsch_tc_init_stats.trials,
(double)UE->dlsch_turbo_decoding_stats.diff/UE->dlsch_turbo_decoding_stats.trials*timeBase,
(int)((double)UE->dlsch_turbo_decoding_stats.diff/UE->dlsch_turbo_decoding_stats.trials),
UE->dlsch_turbo_decoding_stats.trials);
printStatIndent2(&UE->dlsch_tc_init_stats,"init");
printStatIndent2(&UE->dlsch_tc_alpha_stats,"alpha");
printStatIndent2(&UE->dlsch_tc_beta_stats,"beta");
printStatIndent2(&UE->dlsch_tc_gamma_stats,"gamma");
printStatIndent2(&UE->dlsch_tc_ext_stats,"ext");
printStatIndent2(&UE->dlsch_tc_intl1_stats,"turbo internal interleaver");
printStatIndent2(&UE->dlsch_tc_intl2_stats,"intl2+HardDecode+CRC");
*/
}
} // NSR
for (i = 0; i < 2; i++) {
openair2/COMMON/platform_constants.h
+1
View File
@@ -99,6 +99,7 @@
#define NUMBER_OF_NR_DLSCH_MAX 2//16
#define NUMBER_OF_NR_ULSCH_MAX 2//16
#define NUMBER_OF_NR_SR_MAX 16
#define MAX_MANAGED_ENB_PER_MOBILE 2
openair2/LAYER2/NR_MAC_UE/config_ue.c
+78 -114
View File
@@ -135,8 +135,8 @@ int nr_rrc_mac_config_req_ue(
uint8_t gNB_index,
NR_MIB_t *mibP,
NR_ServingCellConfigCommon_t *sccP,
NR_MAC_CellGroupConfig_t *mac_cell_group_configP,
NR_PhysicalCellGroupConfig_t *phy_cell_group_configP,
// NR_MAC_CellGroupConfig_t *mac_cell_group_configP,
// NR_PhysicalCellGroupConfig_t *phy_cell_group_configP,
NR_SpCellConfig_t *spCell_ConfigP ){
NR_UE_MAC_INST_t *mac = get_mac_inst(module_id);
@@ -147,123 +147,87 @@ int nr_rrc_mac_config_req_ue(
NR_ServingCellConfigCommon_t *scc;
if(mibP != NULL){
mac->mib = mibP; // update by every reception
mac->mib = mibP; // update by every reception
}
if(mac_cell_group_configP != NULL){
if(mac_cell_group_configP->drx_Config != NULL ){
switch(mac_cell_group_configP->drx_Config->present){
case NR_SetupRelease_DRX_Config_PR_NOTHING:
break;
case NR_SetupRelease_DRX_Config_PR_release:
mac->drx_Config = NULL;
break;
case NR_SetupRelease_DRX_Config_PR_setup:
mac->drx_Config = mac_cell_group_configP->drx_Config->choice.setup;
break;
default:
break;
}
}
if(mac_cell_group_configP->schedulingRequestConfig != NULL ){
mac->schedulingRequestConfig = mac_cell_group_configP->schedulingRequestConfig;
}
if(mac_cell_group_configP->bsr_Config != NULL ){
mac->bsr_Config = mac_cell_group_configP->bsr_Config;
}
if(mac_cell_group_configP->tag_Config != NULL ){
mac->tag_Config = mac_cell_group_configP->tag_Config;
}
if(mac_cell_group_configP->phr_Config != NULL ){
switch(mac_cell_group_configP->phr_Config->present){
case NR_SetupRelease_PHR_Config_PR_NOTHING:
break;
case NR_SetupRelease_PHR_Config_PR_release:
mac->phr_Config = NULL;
break;
case NR_SetupRelease_PHR_Config_PR_setup:
mac->phr_Config = mac_cell_group_configP->phr_Config->choice.setup;
break;
default:
break;
}
}
if(phy_cell_group_configP->cs_RNTI != NULL ){
switch(phy_cell_group_configP->cs_RNTI->present){
case NR_SetupRelease_RNTI_Value_PR_NOTHING:
break;
case NR_SetupRelease_RNTI_Value_PR_release:
mac->cs_RNTI = NULL;
break;
case NR_SetupRelease_RNTI_Value_PR_setup:
mac->cs_RNTI = &phy_cell_group_configP->cs_RNTI->choice.setup;
break;
default:
break;
}
}
}
if(phy_cell_group_configP != NULL ){
//config_phy(phy_cell_group_config, NULL);
}
// TODO check
if(spCell_ConfigP != NULL ){
mac->servCellIndex = spCell_ConfigP->servCellIndex;
if (spCell_ConfigP->reconfigurationWithSync) {
mac->scc = spCell_ConfigP->reconfigurationWithSync->spCellConfigCommon;
config_common_ue(mac);
mac->servCellIndex = spCell_ConfigP->servCellIndex;
if (spCell_ConfigP->reconfigurationWithSync) {
mac->scc = spCell_ConfigP->reconfigurationWithSync->spCellConfigCommon;
config_common_ue(mac);
mac->crnti = spCell_ConfigP->reconfigurationWithSync->newUE_Identity;
LOG_I(MAC,"Configuring CRNTI %x\n",mac->crnti);
}
mac->scd = spCell_ConfigP->spCellConfigDedicated;
/*
if(mac_cell_group_configP != NULL){
if(mac_cell_group_configP->drx_Config != NULL ){
switch(mac_cell_group_configP->drx_Config->present){
case NR_SetupRelease_DRX_Config_PR_NOTHING:
break;
case NR_SetupRelease_DRX_Config_PR_release:
mac->drx_Config = NULL;
break;
case NR_SetupRelease_DRX_Config_PR_setup:
mac->drx_Config = mac_cell_group_configP->drx_Config->choice.setup;
break;
default:
break;
}
}
mac->scd = spCell_ConfigP->spCellConfigDedicated;
}
#if 0
if(serving_cell_config != NULL ){
if(serving_cell_config->tdd_UL_DL_ConfigurationDedicated != NULL ){
mac->tdd_UL_DL_ConfigurationDedicated = serving_cell_config->tdd_UL_DL_ConfigurationDedicated;
}
if(spcell_config->initialDownlinkBWP != NULL ){
mac->init_DL_BWP = spcell_config->initialDownlinkBWP;
}
// storage list of DL BWP config. TODO should be modify to maintain(add/release) a list inside MAC instance, this implementation just use for one-shot RRC configuration setting.
if(spcell_config->downlinkBWP_ToAddModList != NULL ){
mac->BWP_Downlink_list = spcell_config->downlinkBWP_ToAddModList->list;
mac->BWP_Downlink_count = spcell_config->downlinkBWP_ToAddModList->count;
}
if(spcell_config->bwp_InactivityTimer != NULL ){
mac->bwp_InactivityTimer = spcell_config->bwp_InactivityTimer;
}
if(spcell_config->defaultDownlinkBWP_Id != NULL ){
mac->defaultDownlinkBWP_Id = spcell_config->defaultDownlinkBWP_Id;
}
if(spcell_config->pdsch_ServingCellConfig != NULL ){
mac->pdsch_ServingCellConfig = spcell_config->pdsch_ServingCellConfig;
}
if(spcell_config->csi_MeasConfig != NULL ){
mac->csi_MeasConfig = spcell_config->csi_MeasConfig;
}
spcell_config->tag_Id = spcell_config.tag_Id;
}
#endif
//scell config not yet
if(mac_cell_group_configP->schedulingRequestConfig != NULL ){
mac->schedulingRequestConfig = mac_cell_group_configP->schedulingRequestConfig;
}
if(mac_cell_group_configP->bsr_Config != NULL ){
mac->bsr_Config = mac_cell_group_configP->bsr_Config;
}
if(mac_cell_group_configP->tag_Config != NULL ){
mac->tag_Config = mac_cell_group_configP->tag_Config;
}
if(mac_cell_group_configP->phr_Config != NULL ){
switch(mac_cell_group_configP->phr_Config->present){
case NR_SetupRelease_PHR_Config_PR_NOTHING:
break;
case NR_SetupRelease_PHR_Config_PR_release:
mac->phr_Config = NULL;
break;
case NR_SetupRelease_PHR_Config_PR_setup:
mac->phr_Config = mac_cell_group_configP->phr_Config->choice.setup;
break;
default:
break;
}
}
}
if(phy_cell_group_configP != NULL ){
if(phy_cell_group_configP->cs_RNTI != NULL ){
switch(phy_cell_group_configP->cs_RNTI->present){
case NR_SetupRelease_RNTI_Value_PR_NOTHING:
break;
case NR_SetupRelease_RNTI_Value_PR_release:
mac->cs_RNTI = NULL;
break;
case NR_SetupRelease_RNTI_Value_PR_setup:
mac->cs_RNTI = &phy_cell_group_configP->cs_RNTI->choice.setup;
break;
default:
break;
}
}
}
*/
}
return 0;
}
openair2/LAYER2/NR_MAC_UE/mac_defs.h
+153 -6
View File
@@ -56,6 +56,7 @@
#include "NR_ServingCellConfig.h"
#include "fapi_nr_ue_interface.h"
#include "NR_IF_Module.h"
#include "../NR_MAC_gNB/nr_mac_common.h"
#include "PHY/defs_nr_common.h"
@@ -68,6 +69,13 @@ typedef enum {
} SFN_C_TYPE;
#define MAX_NUM_BWP 2
typedef enum {
RA_IDLE=0,
WAIT_RAR=1,
WAIT_CONTENTION_RESOLUTION=2
} RA_state_t;
/*!\brief Top level UE MAC structure */
typedef struct {
@@ -82,20 +90,27 @@ typedef struct {
NR_PHR_Config_t *phr_Config;
NR_RNTI_Value_t *cs_RNTI;
NR_MIB_t *mib;
NR_BWP_Downlink_t *DLbwp[MAX_NUM_BWP];
NR_BWP_Uplink_t *ULbwp[MAX_NUM_BWP];
NR_ControlResourceSet_t *coreset[MAX_NUM_BWP][FAPI_NR_MAX_CORESET_PER_BWP];
NR_SearchSpace_t *SSpace[MAX_NUM_BWP][FAPI_NR_MAX_CORESET_PER_BWP][FAPI_NR_MAX_SS_PER_CORESET];
/// Type0-PDCCH seach space
fapi_nr_dl_config_dci_dl_pdu_rel15_t type0_pdcch_dci_config;
uint32_t type0_pdcch_ss_mux_pattern;
SFN_C_TYPE type0_pdcch_ss_sfn_c;
uint32_t type0_pdcch_ss_n_c;
uint32_t type0_pdcch_consecutive_slots;
/// Random access parameter
/// state of RA procedure
RA_state_t ra_state;
/// RA-rnti
uint16_t ra_rnti;
//BWP params
NR_BWP_PARMS initial_bwp_dl;
NR_BWP_PARMS initial_bwp_ul;
/// Temporary CRNTI
uint16_t t_crnti;
/// CRNTI
uint16_t crnti;
//// FAPI-like interface message
fapi_nr_tx_request_t tx_request;
@@ -138,7 +153,139 @@ typedef enum frequency_range_e {
FR2
} frequency_range_t;
typedef struct {
uint8_t identifier_dci_formats ; // 0 IDENTIFIER_DCI_FORMATS:
uint8_t carrier_ind ; // 1 CARRIER_IND: 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213]
uint8_t sul_ind_0_1 ; // 2 SUL_IND_0_1:
uint8_t slot_format_ind ; // 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213]
uint8_t pre_emption_ind ; // 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits
uint8_t block_number ; // 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3
uint8_t close_loop_ind ; // 6 CLOSE_LOOP_IND:
uint8_t bandwidth_part_ind ; // 7 BANDWIDTH_PART_IND:
uint8_t short_message_ind ; // 8 SHORT_MESSAGE_IND:
uint8_t short_messages ; // 9 SHORT_MESSAGES:
uint16_t freq_dom_resource_assignment_UL; // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
// (NOTE 1) If DCI format 0_0 is monitored in common search space
// and if the number of information bits in the DCI format 0_0 prior to padding
// is larger than the payload size of the DCI format 1_0 monitored in common search space
// the bitwidth of the frequency domain resource allocation field in the DCI format 0_0
// is reduced such that the size of DCI format 0_0 equals to the size of the DCI format 1_0
uint16_t freq_dom_resource_assignment_DL; // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
uint8_t time_dom_resource_assignment ; // 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
// where I the number of entries in the higher layer parameter pusch-AllocationList
uint8_t vrb_to_prb_mapping ; // 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
uint8_t prb_bundling_size_ind ; // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214]
uint8_t rate_matching_ind ; // 15 RATE_MATCHING_IND: 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set
uint8_t zp_csi_rs_trigger ; // 16 ZP_CSI_RS_TRIGGER:
uint8_t freq_hopping_flag ; // 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
uint8_t tb1_mcs ; // 18 TB1_MCS:
uint8_t tb1_ndi ; // 19 TB1_NDI:
uint8_t tb1_rv ; // 20 TB1_RV:
uint8_t tb2_mcs ; // 21 TB2_MCS:
uint8_t tb2_ndi ; // 22 TB2_NDI:
uint8_t tb2_rv ; // 23 TB2_RV:
uint8_t mcs ; // 24 MCS:
uint8_t ndi ; // 25 NDI:
uint8_t rv ; // 26 RV:
uint8_t harq_process_number ; // 27 HARQ_PROCESS_NUMBER:
uint8_t dai ; // 28 DAI: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
// 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI
// 0 otherwise
uint8_t first_dai ; // 29 FIRST_DAI: (1 or 2 bits) 1 bit for semi-static HARQ-ACK
uint8_t second_dai ; // 30 SECOND_DAI: (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks
uint8_t tb_scaling ; // 31 TB_SCALING:
uint8_t tpc_pusch ; // 32 TPC_PUSCH:
uint8_t tpc_pucch ; // 33 TPC_PUCCH:
uint8_t pucch_resource_ind ; // 34 PUCCH_RESOURCE_IND:
uint8_t pdsch_to_harq_feedback_time_ind ; // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
uint8_t srs_resource_ind ; // 36 SRS_RESOURCE_IND:
uint8_t precod_nbr_layers ; // 37 PRECOD_NBR_LAYERS:
uint8_t antenna_ports ; // 38 ANTENNA_PORTS:
uint8_t tci ; // 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits
uint8_t srs_request ; // 40 SRS_REQUEST:
uint8_t tpc_cmd ; // 41 TPC_CMD:
uint8_t csi_request ; // 42 CSI_REQUEST:
uint8_t cbgti ; // 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH
uint8_t cbgfi ; // 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator
uint8_t ptrs_dmrs ; // 45 PTRS_DMRS:
uint8_t beta_offset_ind ; // 46 BETA_OFFSET_IND:
uint8_t dmrs_seq_ini ; // 47 DMRS_SEQ_INI: 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding
// is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise
uint8_t ul_sch_ind ; // 48 UL_SCH_IND: value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH
uint16_t padding_nr_dci ; // 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
// and if the number of information bits in the DCI format 0_0 prior to padding
// is less than the payload size of the DCI format 1_0 monitored in common search space
// zeros shall be appended to the DCI format 0_0
// until the payload size equals that of the DCI format 1_0
uint8_t sul_ind_0_0 ; // 50 SUL_IND_0_0:
uint8_t ra_preamble_index ; // 51 RA_PREAMBLE_INDEX:
uint8_t sul_ind_1_0 ; // 52 SUL_IND_1_0:
uint8_t ss_pbch_index ; // 53 SS_PBCH_INDEX
uint8_t prach_mask_index ; // 54 PRACH_MASK_INDEX
uint8_t reserved_nr_dci ; // 55 RESERVED_NR_DCI
} nr_dci_pdu_rel15_t;
#define NUM_SLOT_FRAME 10
#define NBR_NR_FORMATS 8 // The number of formats is 8 (0_0, 0_1, 1_0, 1_1, 2_0, 2_1, 2_2, 2_3)
#define NBR_NR_DCI_FIELDS 56 // The number of different dci fields defined in TS 38.212 subclause 7.3.1
#define IDENTIFIER_DCI_FORMATS 0
#define CARRIER_IND 1
#define SUL_IND_0_1 2
#define SLOT_FORMAT_IND 3
#define PRE_EMPTION_IND 4
#define BLOCK_NUMBER 5
#define CLOSE_LOOP_IND 6
#define BANDWIDTH_PART_IND 7
#define SHORT_MESSAGE_IND 8
#define SHORT_MESSAGES 9
#define FREQ_DOM_RESOURCE_ASSIGNMENT_UL 10
#define FREQ_DOM_RESOURCE_ASSIGNMENT_DL 11
#define TIME_DOM_RESOURCE_ASSIGNMENT 12
#define VRB_TO_PRB_MAPPING 13
#define PRB_BUNDLING_SIZE_IND 14
#define RATE_MATCHING_IND 15
#define ZP_CSI_RS_TRIGGER 16
#define FREQ_HOPPING_FLAG 17
#define TB1_MCS 18
#define TB1_NDI 19
#define TB1_RV 20
#define TB2_MCS 21
#define TB2_NDI 22
#define TB2_RV 23
#define MCS 24
#define NDI 25
#define RV 26
#define HARQ_PROCESS_NUMBER 27
#define DAI_ 28
#define FIRST_DAI 29
#define SECOND_DAI 30
#define TB_SCALING 31
#define TPC_PUSCH 32
#define TPC_PUCCH 33
#define PUCCH_RESOURCE_IND 34
#define PDSCH_TO_HARQ_FEEDBACK_TIME_IND 35
#define SRS_RESOURCE_IND 36
#define PRECOD_NBR_LAYERS 37
#define ANTENNA_PORTS 38
#define TCI 39
#define SRS_REQUEST 40
#define TPC_CMD 41
#define CSI_REQUEST 42
#define CBGTI 43
#define CBGFI 44
#define PTRS_DMRS 45
#define BETA_OFFSET_IND 46
#define DMRS_SEQ_INI 47
#define UL_SCH_IND 48
#define PADDING_NR_DCI 49
#define SUL_IND_0_0 50
#define RA_PREAMBLE_INDEX 51
#define SUL_IND_1_0 52
#define SS_PBCH_INDEX 53
#define PRACH_MASK_INDEX 54
#define RESERVED_NR_DCI 55
/*@}*/
#endif /*__LAYER2_MAC_DEFS_H__ */
openair2/LAYER2/NR_MAC_UE/mac_proto.h
+23 -14
View File
@@ -20,7 +20,7 @@
*/
/* \file proto.h
* \brief MAC functions prototypes for eNB and UE
* \brief MAC functions prototypes for gNB and UE
* \author R. Knopp, K.H. HSU
* \date 2018
* \version 0.1
@@ -64,18 +64,14 @@ int8_t nr_ue_decode_mib(
\param gNB_index gNB index
\param mibP pointer to RRC message MIB
\param sccP pointer to ServingCellConfigCommon structure,
\param mac_cell_group_configP pointer to RRC message MAC-related in cell group config
\param phy_cell_group_configP pointer to RRC message PHY-related in cell group config
\param spcell_configP pointer to RRC message serving cell config*/
int nr_rrc_mac_config_req_ue(
module_id_t module_id,
int cc_id,
uint8_t gNB_index,
NR_MIB_t *mibP,
int nr_rrc_mac_config_req_ue(
module_id_t module_id,
int cc_idP,
uint8_t gNB_index,
NR_MIB_t *mibP,
NR_ServingCellConfigCommon_t *sccP,
NR_MAC_CellGroupConfig_t *mac_cell_group_configP,
NR_PhysicalCellGroupConfig_t *phy_cell_group_configP,
NR_SpCellConfig_t *spcell_configP );
NR_SpCellConfig_t *spCell_ConfigP);
/**\brief initialization NR UE MAC instance(s), total number of MAC instance based on NB_NR_UE_MAC_INST*/
int nr_l2_init_ue(void);
@@ -118,7 +114,8 @@ uint32_t ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP,
int8_t nr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe);
int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format);
int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_format);
int nr_ue_process_dci_indication_pdu(module_id_t module_id,int cc_id, int gNB_index,fapi_nr_dci_indication_pdu_t *dci);
uint32_t get_ssb_frame(uint32_t test);
uint32_t get_ssb_slot(uint32_t ssb_index);
@@ -132,11 +129,23 @@ void nr_ue_process_mac_pdu(
uint8_t CC_id,
uint8_t *pduP,
uint16_t mac_pdu_len,
uint8_t eNB_index);
uint8_t gNB_index);
int8_t nr_ue_process_dlsch(module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_indication_t *dci_ind, void *pduP, uint32_t pdu_len);
void nr_ue_send_sdu(module_id_t module_idP, uint8_t CC_id, frame_t frameP, sub_frame_t subframeP, uint8_t * sdu, uint16_t sdu_len, uint8_t eNB_index);
void nr_ue_send_sdu(module_id_t module_idP, uint8_t CC_id, frame_t frameP, sub_frame_t subframeP, uint8_t * sdu, uint16_t sdu_len, uint8_t gNB_index);
void ue_dci_configuration(NR_UE_MAC_INST_t *mac,fapi_nr_dl_config_request_t *dl_config,int frame,int slot);
int nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
int dci_format,
uint8_t dci_length,
uint16_t rnti,
uint64_t *dci_pdu,
nr_dci_pdu_rel15_t *nr_pdci_info_extracted);
#endif
/** @}*/
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
+3073 -2084
View File
File diff suppressed because it is too large Load Diff
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
+1 -1
View File
@@ -328,7 +328,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
// Check if there are downlink symbols in the slot, if not return, no scheduling opportunities
if (is_nr_DL_slot(cc,slot_txP)==0) return;
if (is_nr_DL_slot(cc->ServingCellConfigCommon,slot_txP)==0) return;
RC.nrmac[module_idP]->frame = frame_rxP;
RC.nrmac[module_idP]->slot = slot_rxP;
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
+41 -34
View File
@@ -126,7 +126,7 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
pdsch_pdu_rel15->transmissionScheme = 0;
pdsch_pdu_rel15->refPoint = 0; // Point A
pdsch_pdu_rel15->dmrsConfigType = 1; // 1 by default for InitialBWP
pdsch_pdu_rel15->dmrsConfigType = 0; // Type 1 by default for InitialBWP
pdsch_pdu_rel15->dlDmrsScramblingId = *scc->physCellId;
pdsch_pdu_rel15->SCID = 0;
pdsch_pdu_rel15->numDmrsCdmGrpsNoData = 1;
@@ -173,9 +173,9 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
dlBWP_carrier_bandwidth);
pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbStart,
pdsch_pdu_rel15->rbSize,
dlBWP_carrier_bandwidth);
pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
pdsch_pdu_rel15->rbStart,
dlBWP_carrier_bandwidth);
pdu_rel15->time_domain_assignment = time_domain_assignment;
pdu_rel15->vrb_to_prb_mapping = 1;
@@ -248,7 +248,10 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
int configure_fapi_dl_Tx(int Mod_idP,
int *CCEIndex,
nfapi_nr_dl_tti_request_body_t *dl_req,
nfapi_nr_pdu_t *TX_req) {
nfapi_nr_pdu_t *TX_req,
int *mcsIndex,
int *rbSize,
int *rbStart) {
gNB_MAC_INST *nr_mac = RC.nrmac[Mod_idP];
@@ -266,8 +269,6 @@ int configure_fapi_dl_Tx(int Mod_idP,
NR_UE_list_t *UE_list = &RC.nrmac[Mod_idP]->UE_list;
LOG_I(PHY,"UE_id %d\n",UE_id);
NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id];
AssertFatal(secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count == 1,
"downlinkBWP_ToAddModList has %d BWP!\n",
@@ -301,10 +302,10 @@ int configure_fapi_dl_Tx(int Mod_idP,
else pdsch_pdu_rel15->CyclicPrefix=0;
pdsch_pdu_rel15->NrOfCodewords = 1;
int mcsIndex = 9;
int mcs = (mcsIndex!=NULL) ? *mcsIndex : 9;
pdsch_pdu_rel15->targetCodeRate[0] = nr_get_code_rate_dl(mcsIndex,0);
pdsch_pdu_rel15->qamModOrder[0] = 2;
pdsch_pdu_rel15->mcsIndex[0] = mcsIndex;
pdsch_pdu_rel15->mcsIndex[0] = mcs;
pdsch_pdu_rel15->mcsTable[0] = 0;
pdsch_pdu_rel15->rvIndex[0] = 0;
pdsch_pdu_rel15->dataScramblingId = *scc->physCellId;
@@ -312,14 +313,14 @@ int configure_fapi_dl_Tx(int Mod_idP,
pdsch_pdu_rel15->transmissionScheme = 0;
pdsch_pdu_rel15->refPoint = 0; // Point A
pdsch_pdu_rel15->dmrsConfigType = 1; // 1 by default for InitialBWP
pdsch_pdu_rel15->dmrsConfigType = bwp->bwp_Dedicated->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup->dmrs_Type == NULL ? 0 : 1;
pdsch_pdu_rel15->dlDmrsScramblingId = *scc->physCellId;
pdsch_pdu_rel15->SCID = 0;
pdsch_pdu_rel15->numDmrsCdmGrpsNoData = 1;
pdsch_pdu_rel15->dmrsPorts = 1;
pdsch_pdu_rel15->resourceAlloc = 1;
pdsch_pdu_rel15->rbStart = 0;
pdsch_pdu_rel15->rbSize = 50;
pdsch_pdu_rel15->rbStart = (rbStart!=NULL) ? *rbStart : 0;
pdsch_pdu_rel15->rbSize = (rbSize!=NULL) ? *rbSize : pdsch_pdu_rel15->BWPSize;
pdsch_pdu_rel15->VRBtoPRBMapping = 1; // non-interleaved, check if this is ok for initialBWP
// choose shortest PDSCH
int startSymbolAndLength=0;
@@ -333,14 +334,14 @@ int configure_fapi_dl_Tx(int Mod_idP,
pdsch_pdu_rel15->NrOfSymbols = NrOfSymbols;
// k0 = *bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList->list.array[i]->k0;
pdsch_pdu_rel15->dlDmrsSymbPos = fill_dmrs_mask(NULL,
pdsch_pdu_rel15->dlDmrsSymbPos = fill_dmrs_mask(bwp->bwp_Dedicated->pdsch_Config->choice.setup,
scc->dmrs_TypeA_Position,
pdsch_pdu_rel15->NrOfSymbols);
dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET];
dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbStart,
pdsch_pdu_rel15->rbSize,
dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
pdsch_pdu_rel15->rbStart,
NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275));
dci_pdu_rel15[0].time_domain_assignment = time_domain_assignment; // row index used here instead of SLIV;
dci_pdu_rel15[0].vrb_to_prb_mapping = 1;
@@ -357,7 +358,7 @@ int configure_fapi_dl_Tx(int Mod_idP,
dci_pdu_rel15[0].pucch_resource_indicator = 7;
dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator = 7;
LOG_I(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n",
LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n",
dci_pdu_rel15[0].frequency_domain_assignment,
pdsch_pdu_rel15->rbStart,
pdsch_pdu_rel15->rbSize,
@@ -392,8 +393,9 @@ int configure_fapi_dl_Tx(int Mod_idP,
rnti_types[0] = NR_RNTI_C;
pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
LOG_I(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \
fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \
coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n",
pdcch_pdu_rel15->RNTI[0],
rnti_types[0],
@@ -407,7 +409,7 @@ int configure_fapi_dl_Tx(int Mod_idP,
x_Overhead);
// Hardcode it for now
TBS = dl_tti_pdsch_pdu->pdsch_pdu.pdsch_pdu_rel15.TBSize[0];
LOG_I(MAC, "DLSCH PDU: start PRB %d n_PRB %d startSymbolAndLength %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d TBS: %d\n",
LOG_D(MAC, "DLSCH PDU: start PRB %d n_PRB %d startSymbolAndLength %d start symbol %d nb_symbols %d nb_layers %d nb_codewords %d mcs %d TBS: %d\n",
pdsch_pdu_rel15->rbStart,
pdsch_pdu_rel15->rbSize,
startSymbolAndLength,
@@ -433,8 +435,8 @@ int configure_fapi_dl_Tx(int Mod_idP,
void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types) {
dci_pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_start,
pusch_pdu->rb_size,
dci_pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size,
pusch_pdu->rb_start,
NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275));
dci_pdu_rel15->time_domain_assignment = 2; // row index used here instead of SLIV;
@@ -447,7 +449,7 @@ void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr
dci_pdu_rel15->harq_pid = 0;
dci_pdu_rel15->tpc = 2;
LOG_I(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n",
LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n",
pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci],
dci_pdu_rel15->frequency_domain_assignment,
dci_pdu_rel15->time_domain_assignment,
@@ -633,8 +635,10 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
TBS_bytes = configure_fapi_dl_Tx(module_idP,
CCEIndices,
dl_req,
TX_req);
TX_req,
dlsch_config!=NULL ? dlsch_config->mcsIndex : NULL,
dlsch_config!=NULL ? &dlsch_config->rbSize : NULL,
dlsch_config!=NULL ? &dlsch_config->rbStart : NULL);
#if defined(ENABLE_MAC_PAYLOAD_DEBUG)
LOG_I(MAC, "Printing first 10 payload bytes at the gNB side, Frame: %d, slot: %d, , TBS size: %d \n \n", frameP, slotP, TBS_bytes);
for(int i = 0; i < 10; i++) { // TBS_bytes dlsch_pdu_rel15->transport_block_size/8 6784/8
@@ -668,10 +672,13 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
int CCEIndices[2];
CCEIndices[0] = CCEIndex;
LOG_I(MAC,"Configuring DL_TX in %d.%d\n",frameP,slotP);
TBS_bytes = configure_fapi_dl_Tx(module_idP,CCEIndices,dl_req, TX_req);
// HOT FIX for all zero pdu problem
// ------------------------------------------------------------------------------------------------
LOG_D(MAC,"Configuring DL_TX in %d.%d\n",frameP,slotP);
TBS_bytes = configure_fapi_dl_Tx(module_idP,CCEIndices,dl_req, TX_req,
dlsch_config!=NULL ? dlsch_config->mcsIndex : NULL,
dlsch_config!=NULL ? &dlsch_config->rbSize : NULL,
dlsch_config!=NULL ? &dlsch_config->rbStart : NULL);
// HOT FIX for all zero pdu problem
// ------------------------------------------------------------------------------------------------
for(int i = 0; i < TBS_bytes; i++) { //
((uint8_t *)nr_mac->UE_list.DLSCH_pdu[0][0].payload[0])[i] = (unsigned char) rand();
@@ -679,10 +686,10 @@ void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
}
#if defined(ENABLE_MAC_PAYLOAD_DEBUG)
if (frameP%100 == 0){
LOG_I(MAC, "Printing first 10 payload bytes at the gNB side, Frame: %d, slot: %d, TBS size: %d \n", frameP, slotP, TBS_bytes);
for(int i = 0; i < 10; i++) {
LOG_I(MAC, "%x. ", ((uint8_t *)nr_mac->UE_list.DLSCH_pdu[CC_id][0][0].payload[0])[i]);
}
LOG_I(MAC, "Printing first 10 payload bytes at the gNB side, Frame: %d, slot: %d, TBS size: %d \n", frameP, slotP, TBS_bytes);
for(int i = 0; i < 10; i++) {
LOG_I(MAC, "%x. ", ((uint8_t *)nr_mac->UE_list.DLSCH_pdu[CC_id][0][0].payload[0])[i]);
}
}
#endif
@@ -827,7 +834,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
dci_formats[0] = NR_UL_DCI_FORMAT_0_0;
rnti_types[0] = NR_RNTI_C;
LOG_I(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frameP,slotP);
LOG_D(MAC,"Configuring ULDCI/PDCCH in %d.%d\n", frameP,slotP);
nr_configure_pdcch(pdcch_pdu_rel15,
1, // ue-specific,
scc,
@@ -839,7 +846,7 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
AssertFatal(CCEIndex>=0,"CCEIndex is negative \n");
pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci] = CCEIndex;
LOG_I(PHY,"CCEIndex %d\n",pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci]);
LOG_D(PHY,"CCEIndex %d\n",pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci]);
config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types);
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+1 -139
View File
@@ -39,6 +39,7 @@
#include "LAYER2/NR_MAC_gNB/mac_proto.h"
#include "common/utils/LOG/log.h"
#include "common/utils/LOG/vcd_signal_dumper.h"
#include "common/utils/nr/nr_common.h"
#include "UTIL/OPT/opt.h"
#include "OCG.h"
#include "OCG_extern.h"
@@ -64,7 +65,6 @@
#define ENABLE_MAC_PAYLOAD_DEBUG
#define DEBUG_gNB_SCHEDULER 1
#define CEILIDIV(a,b) ((a+b-1)/b)
#include "common/ran_context.h"
@@ -1367,146 +1367,8 @@ int add_new_nr_ue(module_id_t mod_idP,
}
}
*/
int16_t fill_dmrs_mask(NR_PDSCH_Config_t *pdsch_Config,int dmrs_TypeA_Position,int NrOfSymbols) {
int l0;
if (dmrs_TypeA_Position == NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos2) l0=2;
else if (dmrs_TypeA_Position == NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos3) l0=3;
else AssertFatal(1==0,"Illegal dmrs_TypeA_Position %d\n",(int)dmrs_TypeA_Position);
if (pdsch_Config == NULL) { // Initial BWP
return(1<<l0);
}
else {
if (pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA &&
pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->present == NR_SetupRelease_DMRS_DownlinkConfig_PR_setup) {
// Relative to start of slot
NR_DMRS_DownlinkConfig_t *dmrs_config = (NR_DMRS_DownlinkConfig_t *)pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup;
AssertFatal(NrOfSymbols>1 && NrOfSymbols < 15,"Illegal NrOfSymbols %d\n",NrOfSymbols);
int pos2=0;
if (dmrs_config->maxLength == NULL) {
// this is Table 7.4.1.1.2-3: PDSCH DM-RS positions l for single-symbol DM-RS
if (dmrs_config->dmrs_AdditionalPosition == NULL) pos2=1;
else if (dmrs_config->dmrs_AdditionalPosition && *dmrs_config->dmrs_AdditionalPosition == NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0 )
return(1<<l0);
switch (NrOfSymbols) {
case 2 :
case 3 :
case 4 :
case 5 :
case 6 :
case 7 :
AssertFatal(1==0,"Incoompatible NrOfSymbols %d and dmrs_Additional_Position %d\n",
NrOfSymbols,(int)*dmrs_config->dmrs_AdditionalPosition);
break;
case 8 :
case 9:
return(1<<l0 | 1<<7);
break;
case 10:
case 11:
if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1)
return(1<<l0 | 1<<9);
else
return(1<<l0 | 1<<6 | 1<<9);
break;
case 12:
if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1)
return(1<<l0 | 1<<9);
else if (pos2==1)
return(1<<l0 | 1<<6 | 1<<9);
else if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos3)
return(1<<l0 | 1<<5 | 1<<8 | 1<<11);
break;
case 13:
case 14:
if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1)
return(1<<l0 | 1<<11);
else if (pos2==1)
return(1<<l0 | 1<<7 | 1<<11);
else if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos3)
return(1<<l0 | 1<<5 | 1<<8 | 1<<11);
break;
}
}
else {
// Table 7.4.1.1.2-4: PDSCH DM-RS positions l for double-symbol DM-RS.
AssertFatal(NrOfSymbols>3,"Illegal NrOfSymbols %d for len2 DMRS\n",NrOfSymbols);
if (NrOfSymbols < 10) return(1<<l0);
if (NrOfSymbols < 13 && *dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0) return(1<<l0);
if (NrOfSymbols < 13 && *dmrs_config->dmrs_AdditionalPosition!=NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0) return(1<<l0 || 1<<8);
if (*dmrs_config->dmrs_AdditionalPosition!=NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0) return(1<<l0);
if (*dmrs_config->dmrs_AdditionalPosition!=NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1) return(1<<l0 || 1<<10);
}
}
else if (pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeB &&
pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->present == NR_SetupRelease_DMRS_DownlinkConfig_PR_setup) {
// Relative to start of PDSCH resource
AssertFatal(1==0,"TypeB DMRS not supported yet\n");
}
}
AssertFatal(1==0,"Shouldn't get here\n");
return(-1);
}
int tdd_period_to_num[8] = {500,625,1000,1250,2000,2500,5000,10000};
int is_nr_DL_slot(NR_COMMON_channels_t *cc,slot_t slot) {
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
int period,period1,period2=0;
if (scc->tdd_UL_DL_ConfigurationCommon==NULL) return(1);
if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1 &&
scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530)
period1 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530;
else
period1 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity];
if (scc->tdd_UL_DL_ConfigurationCommon->pattern2) {
if (scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1 &&
scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530)
period2 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530;
else
period2 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern2->dl_UL_TransmissionPeriodicity];
}
period = period1+period2;
int scs=scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing;
int slots=period*(1<<scs)/1000;
int slots1=period1*(1<<scs)/1000;
int slot_in_period = slot % slots;
if (slot_in_period < slots1) return(slot_in_period <= scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots ? 1 : 0);
else return(slot_in_period <= slots1+scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofDownlinkSlots ? 1 : 0);
}
int is_nr_UL_slot(NR_COMMON_channels_t *cc,slot_t slot) {
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
int period,period1,period2=0;
if (scc->tdd_UL_DL_ConfigurationCommon==NULL) return(1);
if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1 &&
scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530)
period1 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530;
else
period1 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity];
if (scc->tdd_UL_DL_ConfigurationCommon->pattern2) {
if (scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1 &&
scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530)
period2 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530;
else
period2 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern2->dl_UL_TransmissionPeriodicity];
}
period = period1+period2;
int scs=scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing;
int slots=period*(1<<scs)/1000;
int slots1=period1*(1<<scs)/1000;
int slot_in_period = slot % slots;
if (slot_in_period < slots1) return(slot_in_period >= scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots ? 1 : 0);
else return(slot_in_period >= slots1+scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofDownlinkSlots ? 1 : 0);
}
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+6 -3
View File
@@ -67,7 +67,10 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
int configure_fapi_dl_Tx(int Mod_id,
int *CCEIndeces,
nfapi_nr_dl_tti_request_body_t *dl_req,
nfapi_nr_pdu_t *TX_req);
nfapi_nr_pdu_t *TX_req,
int *mcsIndex,
int *rbSize,
int *rbStart);
void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types);
void nr_schedule_uss_dlsch_phytest(module_id_t module_idP,
@@ -160,7 +163,7 @@ int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
int m
);
int is_nr_DL_slot(NR_COMMON_channels_t *cc,slot_t slotP);
int is_nr_UL_slot(NR_COMMON_channels_t *cc,slot_t slotP);
int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP);
int is_nr_UL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP);
#endif /*__LAYER2_NR_MAC_PROTO_H__*/
openair1/PHY/CODING/nr_compute_tbs.c → openair2/LAYER2/NR_MAC_gNB/nr_compute_tbs_common.c
+3 -2
View File
@@ -23,9 +23,10 @@
purpose: Compute NR TBS
author: Hongzhi WANG (TCL)
*/
#include "PHY/defs_nr_UE.h"
#define INDEX_MAX_TBS_TABLE (93)
#include "common/utils/nr/nr_common.h"
//Table 5.1.2.2-2
uint16_t Tbstable_nr[INDEX_MAX_TBS_TABLE] = {24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,208,224,240,256,272,288,304,320,336,352,368,384,408,432,456,480,504,528,552,576,608,640,672,704,736,768,808,848,888,928,984,1032,1064,1128,1160,1192,1224,1256,1288,1320,1352,1416,1480,1544,1608,1672,1736,1800,1864,1928,2024,2088,2152,2216,2280,2408,2472,2536,2600,2664,2728,2792,2856,2976,3104,3240,3368,3496,3624,3752,3824};
@@ -45,7 +46,7 @@ uint32_t nr_compute_tbs(uint16_t Qm,
uint32_t Ninfo, Np_info, C;
uint8_t n, scale;
nbp_re = NR_NB_SC_PER_RB * nb_symb_sch - nb_dmrs_prb - nb_rb_oh;
nbp_re = 12 * nb_symb_sch - nb_dmrs_prb - nb_rb_oh;
nb_re = min(156, nbp_re) * nb_rb;
openair2/LAYER2/NR_MAC_gNB/nr_mac_common.c
+142 -2
View File
@@ -211,7 +211,7 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu,
N_sh_symb,
N_PRB_DMRS,
N_PRB_oh,
pdsch_rel15->nrOfLayers);
pdsch_rel15->nrOfLayers)>>3;
pdsch_rel15->targetCodeRate[0] = R;
pdsch_rel15->qamModOrder[0] = Qm;
@@ -219,7 +219,7 @@ void nr_get_tbs_dl(nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu,
// pdsch_rel15->nb_mod_symbols = N_RE_prime*pdsch_rel15->n_prb*pdsch_rel15->nb_codewords;
pdsch_rel15->mcsTable[0] = table_idx;
LOG_D(MAC, "TBS %d : N_PRB_DMRS %d N_sh_symb %d N_PRB_oh %d R %d Qm %d table %d nb_symbols %d\n",
LOG_D(MAC, "TBS %d bytes: N_PRB_DMRS %d N_sh_symb %d N_PRB_oh %d R %d Qm %d table %d nb_symbols %d\n",
TBS, N_PRB_DMRS, N_sh_symb, N_PRB_oh, R, Qm, table_idx,N_RE_prime*pdsch_rel15->rbSize*pdsch_rel15->NrOfCodewords );
}
@@ -455,3 +455,143 @@ uint16_t nr_dci_size(nr_dci_format_t format,
return size;
}
int tdd_period_to_num[8] = {500,625,1000,1250,2000,2500,5000,10000};
int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slot) {
int period,period1,period2=0;
if (scc->tdd_UL_DL_ConfigurationCommon==NULL) return(1);
if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1 &&
scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530)
period1 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530;
else
period1 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity];
if (scc->tdd_UL_DL_ConfigurationCommon->pattern2) {
if (scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1 &&
scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530)
period2 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530;
else
period2 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern2->dl_UL_TransmissionPeriodicity];
}
period = period1+period2;
int scs=scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing;
int slots=period*(1<<scs)/1000;
int slots1=period1*(1<<scs)/1000;
int slot_in_period = slot % slots;
if (slot_in_period < slots1) return(slot_in_period <= scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots ? 1 : 0);
else return(slot_in_period <= slots1+scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofDownlinkSlots ? 1 : 0);
}
int is_nr_UL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slot) {
int period,period1,period2=0;
if (scc->tdd_UL_DL_ConfigurationCommon==NULL) return(1);
if (scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1 &&
scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530)
period1 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern1.ext1->dl_UL_TransmissionPeriodicity_v1530;
else
period1 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern1.dl_UL_TransmissionPeriodicity];
if (scc->tdd_UL_DL_ConfigurationCommon->pattern2) {
if (scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1 &&
scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530)
period2 = 3000+*scc->tdd_UL_DL_ConfigurationCommon->pattern2->ext1->dl_UL_TransmissionPeriodicity_v1530;
else
period2 = tdd_period_to_num[scc->tdd_UL_DL_ConfigurationCommon->pattern2->dl_UL_TransmissionPeriodicity];
}
period = period1+period2;
int scs=scc->tdd_UL_DL_ConfigurationCommon->referenceSubcarrierSpacing;
int slots=period*(1<<scs)/1000;
int slots1=period1*(1<<scs)/1000;
int slot_in_period = slot % slots;
if (slot_in_period < slots1) return(slot_in_period >= scc->tdd_UL_DL_ConfigurationCommon->pattern1.nrofDownlinkSlots ? 1 : 0);
else return(slot_in_period >= slots1+scc->tdd_UL_DL_ConfigurationCommon->pattern2->nrofDownlinkSlots ? 1 : 0);
}
int16_t fill_dmrs_mask(NR_PDSCH_Config_t *pdsch_Config,int dmrs_TypeA_Position,int NrOfSymbols) {
int l0;
if (dmrs_TypeA_Position == NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos2) l0=2;
else if (dmrs_TypeA_Position == NR_ServingCellConfigCommon__dmrs_TypeA_Position_pos3) l0=3;
else AssertFatal(1==0,"Illegal dmrs_TypeA_Position %d\n",(int)dmrs_TypeA_Position);
if (pdsch_Config == NULL) { // Initial BWP
return(1<<l0);
}
else {
if (pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA &&
pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->present == NR_SetupRelease_DMRS_DownlinkConfig_PR_setup) {
// Relative to start of slot
NR_DMRS_DownlinkConfig_t *dmrs_config = (NR_DMRS_DownlinkConfig_t *)pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->choice.setup;
AssertFatal(NrOfSymbols>1 && NrOfSymbols < 15,"Illegal NrOfSymbols %d\n",NrOfSymbols);
int pos2=0;
if (dmrs_config->maxLength == NULL) {
// this is Table 7.4.1.1.2-3: PDSCH DM-RS positions l for single-symbol DM-RS
if (dmrs_config->dmrs_AdditionalPosition == NULL) pos2=1;
else if (dmrs_config->dmrs_AdditionalPosition && *dmrs_config->dmrs_AdditionalPosition == NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0 )
return(1<<l0);
switch (NrOfSymbols) {
case 2 :
case 3 :
case 4 :
case 5 :
case 6 :
case 7 :
AssertFatal(1==0,"Incoompatible NrOfSymbols %d and dmrs_Additional_Position %d\n",
NrOfSymbols,(int)*dmrs_config->dmrs_AdditionalPosition);
break;
case 8 :
case 9:
return(1<<l0 | 1<<7);
break;
case 10:
case 11:
if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1)
return(1<<l0 | 1<<9);
else
return(1<<l0 | 1<<6 | 1<<9);
break;
case 12:
if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1)
return(1<<l0 | 1<<9);
else if (pos2==1)
return(1<<l0 | 1<<6 | 1<<9);
else if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos3)
return(1<<l0 | 1<<5 | 1<<8 | 1<<11);
break;
case 13:
case 14:
if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1)
return(1<<l0 | 1<<11);
else if (pos2==1)
return(1<<l0 | 1<<7 | 1<<11);
else if (*dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos3)
return(1<<l0 | 1<<5 | 1<<8 | 1<<11);
break;
}
}
else {
// Table 7.4.1.1.2-4: PDSCH DM-RS positions l for double-symbol DM-RS.
AssertFatal(NrOfSymbols>3,"Illegal NrOfSymbols %d for len2 DMRS\n",NrOfSymbols);
if (NrOfSymbols < 10) return(1<<l0);
if (NrOfSymbols < 13 && *dmrs_config->dmrs_AdditionalPosition==NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0) return(1<<l0);
if (NrOfSymbols < 13 && *dmrs_config->dmrs_AdditionalPosition!=NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0) return(1<<l0 || 1<<8);
if (*dmrs_config->dmrs_AdditionalPosition!=NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos0) return(1<<l0);
if (*dmrs_config->dmrs_AdditionalPosition!=NR_DMRS_DownlinkConfig__dmrs_AdditionalPosition_pos1) return(1<<l0 || 1<<10);
}
}
else if (pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeB &&
pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA->present == NR_SetupRelease_DMRS_DownlinkConfig_PR_setup) {
// Relative to start of PDSCH resource
AssertFatal(1==0,"TypeB DMRS not supported yet\n");
}
}
AssertFatal(1==0,"Shouldn't get here\n");
return(-1);
}
openair2/LAYER2/NR_MAC_gNB/nr_mac_common.h
+62
View File
@@ -0,0 +1,62 @@
/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.1 (the "License"); you may not use this file
* except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*-------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
/*! \file mac.h
* \brief MAC data structures, constant, and function prototype
* \author Navid Nikaein and Raymond Knopp, WIE-TAI CHEN
* \date Dec. 2019
* \version 0.1
* \company Eurecom
* \email raymond.knopp@eurecom.fr
*/
#ifndef __LAYER2_NR_MAC_COMMON_H__
#define __LAYER2_NR_MAC_COMMON_H__
typedef enum {
NR_DL_DCI_FORMAT_1_0 = 0,
NR_DL_DCI_FORMAT_1_1,
NR_DL_DCI_FORMAT_2_0,
NR_DL_DCI_FORMAT_2_1,
NR_DL_DCI_FORMAT_2_2,
NR_DL_DCI_FORMAT_2_3,
NR_UL_DCI_FORMAT_0_0,
NR_UL_DCI_FORMAT_0_1
} nr_dci_format_t;
typedef enum {
NR_RNTI_new = 0,
NR_RNTI_C,
NR_RNTI_RA,
NR_RNTI_P,
NR_RNTI_CS,
NR_RNTI_TC,
NR_RNTI_SP_CSI,
NR_RNTI_SI,
NR_RNTI_SFI,
NR_RNTI_INT,
NR_RNTI_TPC_PUSCH,
NR_RNTI_TPC_PUCCH,
NR_RNTI_TPC_SRS
} nr_rnti_type_t;
#endif
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+2 -25
View File
@@ -59,6 +59,8 @@
#include "PHY/TOOLS/time_meas.h"
#include "targets/ARCH/COMMON/common_lib.h"
#include "nr_mac_common.h"
#define MAX_NUM_BWP 2
#define MAX_NUM_CORESET 2
#define MAX_NUM_CCE 90
@@ -241,31 +243,6 @@ uint16_t padding;
} dci_pdu_rel15_t;
typedef enum {
NR_DL_DCI_FORMAT_1_0 = 0,
NR_DL_DCI_FORMAT_1_1,
NR_DL_DCI_FORMAT_2_0,
NR_DL_DCI_FORMAT_2_1,
NR_DL_DCI_FORMAT_2_2,
NR_DL_DCI_FORMAT_2_3,
NR_UL_DCI_FORMAT_0_0,
NR_UL_DCI_FORMAT_0_1
} nr_dci_format_t;
typedef enum {
NR_RNTI_new = 0,
NR_RNTI_C,
NR_RNTI_RA,
NR_RNTI_P,
NR_RNTI_CS,
NR_RNTI_TC,
NR_RNTI_SP_CSI,
NR_RNTI_SI,
NR_RNTI_SFI,
NR_RNTI_INT,
NR_RNTI_TPC_PUSCH,
NR_RNTI_TPC_PUCCH,
NR_RNTI_TPC_SRS
} nr_rnti_type_t;
#endif /*__LAYER2_NR_MAC_GNB_H__ */
openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
+17 -56
View File
@@ -64,22 +64,22 @@ int handle_bcch_dlsch(module_id_t module_id, int cc_id, unsigned int gNB_index,
return 0;
}
// L2 Abstraction Layer
int handle_dci(module_id_t module_id, int cc_id, unsigned int gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_type){
int handle_dci(module_id_t module_id, int cc_id, unsigned int gNB_index, fapi_nr_dci_indication_pdu_t *dci){
//printf("handle_dci: rnti %x,dci_type %d\n",rnti,dci_type);
return nr_ue_process_dci(module_id, cc_id, gNB_index, dci, rnti, dci_type);
return nr_ue_process_dci_indication_pdu(module_id, cc_id, gNB_index, dci);
}
// L2 Abstraction Layer
int8_t handle_dlsch (module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_indication_t *dci_ind, uint8_t *pduP, uint32_t pdu_len, frame_t frame, int slot){
LOG_I(MAC, "handle_dlsch at MAC layer \n");
if (IS_SOFTMODEM_NOS1)
nr_ue_send_sdu(module_id, 0, frame, slot,
pduP,
pdu_len,
LOG_D(MAC, "handle_dlsch at MAC layer \n");
if (IS_SOFTMODEM_NOS1)
nr_ue_send_sdu(module_id, 0, frame, slot,
pduP,
pdu_len,
0);
return 0;
return 0;
/*
return nr_ue_process_dlsch( module_id,
cc_id,
@@ -154,15 +154,13 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info){
LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][DCI_IND]\n");
for(i=0; i<dl_info->dci_ind->number_of_dcis; ++i){
LOG_D(MAC,">>>NR_IF_Module i=%d, dl_info->dci_ind->number_of_dcis=%d\n",i,dl_info->dci_ind->number_of_dcis);
fapi_nr_dci_pdu_rel15_t *dci = &dl_info->dci_ind->dci_list[i].dci;
// fapi_nr_dci_pdu_rel15_t *dci = &dl_info->dci_ind->dci_list[i].dci;
ret_mask |= (handle_dci(
dl_info->module_id,
dl_info->cc_id,
dl_info->gNB_index,
dci,
(dl_info->dci_ind->dci_list+i)->rnti,
(dl_info->dci_ind->dci_list+i)->dci_format)) << FAPI_NR_DCI_IND;
dl_info->dci_ind->dci_list+i)<< FAPI_NR_DCI_IND);
AssertFatal( nr_ue_if_module_inst[module_id] != NULL, "IF module is void!\n" );
nr_ue_if_module_inst[module_id]->scheduled_response(&mac->scheduled_response);
@@ -216,7 +214,7 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info){
}
if(dl_info->rx_ind != NULL){
LOG_I(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
for(i=0; i<dl_info->rx_ind->number_pdus; ++i){
switch(dl_info->rx_ind->rx_indication_body[i].pdu_type){
case FAPI_NR_RX_PDU_TYPE_MIB:
@@ -227,7 +225,7 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info){
(dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_index,
(dl_info->rx_ind->rx_indication_body+i)->mib_pdu.ssb_length,
(dl_info->rx_ind->rx_indication_body+i)->mib_pdu.cell_id )) << FAPI_NR_RX_PDU_TYPE_MIB;
LOG_I(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], MIB case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], MIB case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
/*ret_mask |= (handle_bcch_bch( dl_info->proc,
dl_info->module_id, dl_info->cc_id, dl_info->gNB_index,
dl_info->rx_ind->rx_indication_body[i].mib_pdu.pdu,
@@ -248,7 +246,7 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info){
(dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu,
(dl_info->rx_ind->rx_indication_body+i)->pdsch_pdu.pdu_length, dl_info->frame, dl_info->slot)) << FAPI_NR_RX_PDU_TYPE_DLSCH;
LOG_I(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], DLSCH case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
LOG_D(MAC,"[L2][IF MODULE][DL INDICATION][RX_IND], DLSCH case Number of PDUs: %d \n", dl_info->rx_ind->number_pdus);
/*
// dl_config structure just stores what was received - not really needed
@@ -307,48 +305,11 @@ int nr_ue_dcireq(nr_dcireq_t *dcireq) {
fapi_nr_dl_config_request_t *dl_config=&dcireq->dl_config_req;
NR_UE_MAC_INST_t *UE_mac = get_mac_inst(0);
// Type0 PDCCH search space
dl_config->number_pdus = 1;
dl_config->dl_config_list[0].pdu_type = FAPI_NR_DL_CONFIG_TYPE_DCI;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.rnti = 0x1234; // to be set
uint64_t mask = 0x0;
uint16_t num_rbs=24;
uint16_t rb_offset=0;
uint16_t cell_id=0;
uint16_t num_symbols=2;
for(int i=0; i<(num_rbs/6); ++i){ // 38.331 Each bit corresponds a group of 6 RBs
mask = mask >> 1;
mask = mask | 0x100000000000;
}
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.frequency_domain_resource = mask;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.rb_offset = rb_offset; // additional parameter other than coreset
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.duration = num_symbols;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_mapping_type =CCE_REG_MAPPING_TYPE_NON_INTERLEAVED;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_reg_bundle_size = 0; // L 38.211 7.3.2.2
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_interleaver_size = 0; // R 38.211 7.3.2.2
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.cce_reg_interleaved_shift_index = cell_id;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.precoder_granularity = PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.coreset.pdcch_dmrs_scrambling_id = cell_id;
uint32_t number_of_search_space_per_slot=1;
uint32_t first_symbol_index=0;
uint32_t search_space_duration=0; // element of search space
uint32_t coreset_duration; // element of coreset
coreset_duration = num_symbols * number_of_search_space_per_slot;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[0] = table_38213_10_1_1_c2[0];
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[1] = table_38213_10_1_1_c2[1];
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[2] = table_38213_10_1_1_c2[2]; // CCE aggregation level = 4
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[3] = table_38213_10_1_1_c2[3]; // CCE aggregation level = 8
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.number_of_candidates[4] = table_38213_10_1_1_c2[4]; // CCE aggregation level = 16
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.duration = search_space_duration;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.monitoring_symbols_within_slot = (0x3fff << first_symbol_index) & (0x3fff >> (14-coreset_duration-first_symbol_index)) & 0x3fff;
dl_config->dl_config_list[0].dci_config_pdu.dci_config_rel15.N_RB_BWP = UE_mac->initial_bwp_dl.N_RB;
dl_config->number_pdus=0;
ue_dci_configuration(UE_mac,dl_config,dcireq->frame,dcireq->slot);
return 0;
openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.h
+1 -1
View File
@@ -223,7 +223,7 @@ int handle_bcch_bch(UE_nr_rxtx_proc_t *proc, module_id_t module_id, int cc_id, u
\param pduP pointer to pdu*/
int handle_bcch_dlsch(module_id_t module_id, int cc_id, unsigned int gNB_index, uint32_t sibs_mask, uint8_t *pduP, uint32_t pdu_len);
int handle_dci(module_id_t module_id, int cc_id, unsigned int gNB_index, fapi_nr_dci_pdu_rel15_t *dci, uint16_t rnti, uint32_t dci_type);
int handle_dci(module_id_t module_id, int cc_id, unsigned int gNB_index, fapi_nr_dci_indication_pdu_t *dci);
#endif
openair2/RRC/NR/rrc_gNB_nsa.c
+1 -3
View File
@@ -41,7 +41,6 @@
void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerList_t *UE_CapabilityRAT_ContainerList) {
struct rrc_gNB_ue_context_s *ue_context_p = NULL;
int rnti = taus()&65535;
OCTET_STRING_t *ueCapabilityRAT_Container_nr;
OCTET_STRING_t *ueCapabilityRAT_Container_MRDC;
int list_size;
@@ -56,7 +55,6 @@ void rrc_parse_ue_capabilities(gNB_RRC_INST *rrc,LTE_UE_CapabilityRAT_ContainerL
AssertFatal(ueCapabilityRAT_Container_MRDC!=NULL,"ueCapabilityRAT_Container_MRDC is NULL\n");
// decode and store capabilities
ue_context_p = rrc_gNB_allocate_new_UE_context(rrc);
ue_context_p->ue_id_rnti = rnti;
asn_dec_rval_t dec_rval = uper_decode(NULL,
&asn_DEF_NR_UE_NR_Capability,
@@ -127,7 +125,7 @@ void rrc_add_nsa_user(gNB_RRC_INST *rrc,struct rrc_gNB_ue_context_s *ue_context_
ue_context_p->ue_context.rb_config = calloc(1,sizeof(NR_RRCReconfiguration_t));
fill_default_rbconfig(ue_context_p->ue_context.rb_config);
ue_context_p->ue_id_rnti = ue_context_p->ue_context.secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity;
NR_CG_Config_t *CG_Config = calloc(1,sizeof(*CG_Config));
memset((void*)CG_Config,0,sizeof(*CG_Config));
generate_CG_Config(rrc,CG_Config,ue_context_p->ue_context.reconfig,ue_context_p->ue_context.rb_config);