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Testing of NR PDCCH/PDSCH with RRC Configuration. added RRC configuration to NR UE. Updates to UE DCI procedures (moved to MAC) and updates to FAPI interfaces for UE. nr_dlsim is functional, added profiling information for gNB TX.

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This commit is contained in:
Raymond Knopp
2020-01-01 21:16:56 +01:00
parent 6bf81627e0
commit ad2667fbd5
55 changed files with 4704 additions and 5825 deletions
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nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_constants.h
+5 -2
View File
@@ -8,6 +8,9 @@
#define FAPI_NR_MAX_NUM_ZP_CSI_RS_RESOURCE_PER_SET 16
#define FAPI_NR_MAX_NUM_CANDIDATE_BEAMS 16
#define FAPI_NR_MAX_RA_OCCASION_PER_CSIRS 64
// Constants Defined in 38.213
#define FAPI_NR_MAX_CORESET_PER_BWP 3
#define FAPI_NR_MAX_SS_PER_CORESET 10
/// RX_IND
@@ -41,8 +44,8 @@
#define FAPI_NR_DL_CONFIG_TYPE_DLSCH 0x02
#define CCE_REG_MAPPING_TYPE_INTERLEAVED 0x01
#define CCE_REG_MAPPING_TYPE_NON_INTERLEAVED 0x02
#define FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED 0x01
#define FAPI_NR_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED 0x02
#define PRECODER_GRANULARITY_SAME_AS_REG_BUNDLE 0x01
#define PRECODER_GRANULARITY_ALL_CONTIGUOUS_RBS 0x02
nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
+26 -92
View File
@@ -31,77 +31,7 @@
typedef signed char int8_t;
*/
typedef struct {
uint8_t identifier_dci_formats ; // 0 IDENTIFIER_DCI_FORMATS:
uint8_t carrier_ind ; // 1 CARRIER_IND: 0 or 3 bits, as defined in Subclause x.x of [5, TS38.213]
uint8_t sul_ind_0_1 ; // 2 SUL_IND_0_1:
uint8_t slot_format_ind ; // 3 SLOT_FORMAT_IND: size of DCI format 2_0 is configurable by higher layers up to 128 bits, according to Subclause 11.1.1 of [5, TS 38.213]
uint8_t pre_emption_ind ; // 4 PRE_EMPTION_IND: size of DCI format 2_1 is configurable by higher layers up to 126 bits, according to Subclause 11.2 of [5, TS 38.213]. Each pre-emption indication is 14 bits
uint8_t block_number ; // 5 BLOCK_NUMBER: starting position of a block is determined by the parameter startingBitOfFormat2_3
uint8_t close_loop_ind ; // 6 CLOSE_LOOP_IND:
uint8_t bandwidth_part_ind ; // 7 BANDWIDTH_PART_IND:
uint8_t short_message_ind ; // 8 SHORT_MESSAGE_IND:
uint8_t short_messages ; // 9 SHORT_MESSAGES:
uint16_t freq_dom_resource_assignment_UL; // 10 FREQ_DOM_RESOURCE_ASSIGNMENT_UL: PUSCH hopping with resource allocation type 1 not considered
// (NOTE 1) If DCI format 0_0 is monitored in common search space
// and if the number of information bits in the DCI format 0_0 prior to padding
// is larger than the payload size of the DCI format 1_0 monitored in common search space
// the bitwidth of the frequency domain resource allocation field in the DCI format 0_0
// is reduced such that the size of DCI format 0_0 equals to the size of the DCI format 1_0
uint16_t freq_dom_resource_assignment_DL; // 11 FREQ_DOM_RESOURCE_ASSIGNMENT_DL:
uint8_t time_dom_resource_assignment ; // 12 TIME_DOM_RESOURCE_ASSIGNMENT: 0, 1, 2, 3, or 4 bits as defined in Subclause 6.1.2.1 of [6, TS 38.214]. The bitwidth for this field is determined as log2(I) bits,
// where I the number of entries in the higher layer parameter pusch-AllocationList
uint8_t vrb_to_prb_mapping ; // 13 VRB_TO_PRB_MAPPING: 0 bit if only resource allocation type 0
uint8_t prb_bundling_size_ind ; // 14 PRB_BUNDLING_SIZE_IND:0 bit if the higher layer parameter PRB_bundling is not configured or is set to 'static', or 1 bit if the higher layer parameter PRB_bundling is set to 'dynamic' according to Subclause 5.1.2.3 of [6, TS 38.214]
uint8_t rate_matching_ind ; // 15 RATE_MATCHING_IND: 0, 1, or 2 bits according to higher layer parameter rate-match-PDSCH-resource-set
uint8_t zp_csi_rs_trigger ; // 16 ZP_CSI_RS_TRIGGER:
uint8_t freq_hopping_flag ; // 17 FREQ_HOPPING_FLAG: 0 bit if only resource allocation type 0
uint8_t tb1_mcs ; // 18 TB1_MCS:
uint8_t tb1_ndi ; // 19 TB1_NDI:
uint8_t tb1_rv ; // 20 TB1_RV:
uint8_t tb2_mcs ; // 21 TB2_MCS:
uint8_t tb2_ndi ; // 22 TB2_NDI:
uint8_t tb2_rv ; // 23 TB2_RV:
uint8_t mcs ; // 24 MCS:
uint8_t ndi ; // 25 NDI:
uint8_t rv ; // 26 RV:
uint8_t harq_process_number ; // 27 HARQ_PROCESS_NUMBER:
uint8_t dai ; // 28 DAI: For format1_1: 4 if more than one serving cell are configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 MSB bits are the counter DAI and the 2 LSB bits are the total DAI
// 2 if one serving cell is configured in the DL and the higher layer parameter HARQ-ACK-codebook=dynamic, where the 2 bits are the counter DAI
// 0 otherwise
uint8_t first_dai ; // 29 FIRST_DAI: (1 or 2 bits) 1 bit for semi-static HARQ-ACK
uint8_t second_dai ; // 30 SECOND_DAI: (0 or 2 bits) 2 bits for dynamic HARQ-ACK codebook with two HARQ-ACK sub-codebooks
uint8_t tb_scaling ; // 31 TB_SCALING:
uint8_t tpc_pusch ; // 32 TPC_PUSCH:
uint8_t tpc_pucch ; // 33 TPC_PUCCH:
uint8_t pucch_resource_ind ; // 34 PUCCH_RESOURCE_IND:
uint8_t pdsch_to_harq_feedback_time_ind ; // 35 PDSCH_TO_HARQ_FEEDBACK_TIME_IND:
uint8_t srs_resource_ind ; // 36 SRS_RESOURCE_IND:
uint8_t precod_nbr_layers ; // 37 PRECOD_NBR_LAYERS:
uint8_t antenna_ports ; // 38 ANTENNA_PORTS:
uint8_t tci ; // 39 TCI: 0 bit if higher layer parameter tci-PresentInDCI is not enabled; otherwise 3 bits
uint8_t srs_request ; // 40 SRS_REQUEST:
uint8_t tpc_cmd ; // 41 TPC_CMD:
uint8_t csi_request ; // 42 CSI_REQUEST:
uint8_t cbgti ; // 43 CBGTI: 0, 2, 4, 6, or 8 bits determined by higher layer parameter maxCodeBlockGroupsPerTransportBlock for the PDSCH
uint8_t cbgfi ; // 44 CBGFI: 0 or 1 bit determined by higher layer parameter codeBlockGroupFlushIndicator
uint8_t ptrs_dmrs ; // 45 PTRS_DMRS:
uint8_t beta_offset_ind ; // 46 BETA_OFFSET_IND:
uint8_t dmrs_seq_ini ; // 47 DMRS_SEQ_INI: 1 bit if the cell has two ULs and the number of bits for DCI format 1_0 before padding
// is larger than the number of bits for DCI format 0_0 before padding; 0 bit otherwise
uint8_t ul_sch_ind ; // 48 UL_SCH_IND: value of "1" indicates UL-SCH shall be transmitted on the PUSCH and a value of "0" indicates UL-SCH shall not be transmitted on the PUSCH
uint16_t padding_nr_dci ; // 49 PADDING_NR_DCI: (Note 2) If DCI format 0_0 is monitored in common search space
// and if the number of information bits in the DCI format 0_0 prior to padding
// is less than the payload size of the DCI format 1_0 monitored in common search space
// zeros shall be appended to the DCI format 0_0
// until the payload size equals that of the DCI format 1_0
uint8_t sul_ind_0_0 ; // 50 SUL_IND_0_0:
uint8_t ra_preamble_index ; // 51 RA_PREAMBLE_INDEX:
uint8_t sul_ind_1_0 ; // 52 SUL_IND_1_0:
uint8_t ss_pbch_index ; // 53 SS_PBCH_INDEX
uint8_t prach_mask_index ; // 54 PRACH_MASK_INDEX
uint8_t reserved_nr_dci ; // 55 RESERVED_NR_DCI
} fapi_nr_dci_pdu_rel15_t;
@@ -120,16 +50,14 @@ typedef struct {
typedef struct {
/// frequency_domain_resource;
//uint32_t rb_start;
//uint32_t rb_end;
uint64_t frequency_domain_resource;
uint16_t rb_offset;
uint8_t frequency_domain_resource[6];
uint8_t StartSymbolIndex;
uint8_t duration;
uint8_t cce_reg_mapping_type; // interleaved or noninterleaved
uint8_t cce_reg_interleaved_reg_bundle_size; // valid if CCE to REG mapping type is interleaved type
uint8_t cce_reg_interleaved_interleaver_size; // valid if CCE to REG mapping type is interleaved type
uint8_t cce_reg_interleaved_shift_index; // valid if CCE to REG mapping type is interleaved type
uint8_t CceRegMappingType; // interleaved or noninterleaved
uint8_t RegBundleSize; // valid if CCE to REG mapping type is interleaved type
uint8_t InterleaverSize; // valid if CCE to REG mapping type is interleaved type
uint8_t ShiftIndex; // valid if CCE to REG mapping type is interleaved type
uint8_t CoreSetType;
uint8_t precoder_granularity;
uint16_t pdcch_dmrs_scrambling_id;
@@ -154,13 +82,16 @@ typedef struct {
int n_CCE;
// N_CCE is L, or number of CCEs for DCI
int N_CCE;
fapi_nr_dci_pdu_rel15_t dci;
uint8_t payloadSize;
uint8_t payloadBits[16];
//fapi_nr_dci_pdu_rel15_t dci;
} fapi_nr_dci_indication_pdu_t;
///
typedef struct {
uint32_t sfn_slot;
uint16_t SFN;
uint8_t slot;
uint16_t number_of_dcis;
fapi_nr_dci_indication_pdu_t dci_list[10];
} fapi_nr_dci_indication_t;
@@ -381,16 +312,15 @@ typedef struct {
typedef struct {
uint16_t rnti;
uint16_t BWPSize;
uint16_t BWPStart;
uint8_t SubcarrierSpacing;
fapi_nr_coreset_t coreset;
uint16_t N_RB_BWP;
uint32_t duration;
uint8_t number_of_candidates[5]; // aggregation level 1, 2, 4, 8, 16
uint16_t monitoring_symbols_within_slot;
// DCI foramt-specific
uint8_t format_2_0_number_of_candidates[5]; // aggregation level 1, 2, 4, 8, 16
uint8_t format_2_3_monitorying_periodicity;
uint8_t format_2_3_number_of_candidates;
uint8_t number_of_candidates;
uint16_t CCE[64];
uint8_t L[64];
uint8_t dci_length;
uint8_t dci_format;
} fapi_nr_dl_config_dci_dl_pdu_rel15_t;
typedef struct {
@@ -403,12 +333,16 @@ typedef struct{
typedef enum{vrb_to_prb_mapping_non_interleaved = 0, vrb_to_prb_mapping_interleaved = 1} vrb_to_prb_mapping_t;
//typedef fapi_nr_dci_pdu_rel15_t fapi_nr_dl_config_dlsch_pdu_rel15_t;
typedef struct {
uint8_t bandwidth_part_ind;
uint16_t BWPSize;
uint16_t BWPStart;
uint8_t SubcarrierSpacing;
uint16_t number_rbs;
uint16_t start_rb;
uint8_t frame_offset;
uint16_t number_symbols;
uint16_t start_symbol;
uint16_t dlDmrsSymbPos;
uint8_t dmrsConfigType;
uint8_t prb_bundling_size_ind;
uint8_t rate_matching_ind;
uint8_t zp_csi_rs_trigger;